Industrial protocol heterogeneous acceleration system based on FPGA

Abstract

The invention discloses a field programmable gate array (FPGA)-based industrial protocol heterogeneous acceleration system, which adopts a configurable protocol state table to perform protocol analysis, and can dynamically adjust an analysis rule according to different industrial protocol standards, so that the FPGA-based industrial protocol heterogeneous acceleration system can flexibly process different types of industrial protocols, thereby increasing the use flexibility; meanwhile, a heterogeneous acceleration engine is further arranged, software and hardware with the lowest load in software and hardware units for processing the tasks in the FPGA can be determined according to different task types, and the software and hardware with the lowest load are dispatched for protocol analysis; therefore, efficient processing of the industrial protocol can be realized through cooperative work accelerated by software and hardware; on the basis, different types of industrial protocols can be flexibly processed, efficient acceleration of processing of various industrial protocols can be achieved at the same time, and on the basis, the application scene with the high requirement for the real-time performance of an industrial site can be met, so that the overall stability and reliability of an industrial system can be improved.

Description

Technical Field

[0001] The present invention relates to the fields of industrial automation and communication technologies, and particularly relates to an industrial protocol heterogeneous acceleration system based on FPGA. Background Art

[0002] Under the development trend of Industry 4.0, there are a large number of different types of devices and systems in the industrial field, and they communicate according to different industrial protocols respectively, such as Modbus, Profibus, Ethernet / IP, etc.; this heterogeneity of industrial protocols has brought great challenges to the integration and interaction of industrial data.

[0003] Currently, existing industrial protocol processing solutions are mainly based on general-purpose processors (CPUs) or application-specific integrated circuits (ASICs). Among them, the CPU-based solution has high flexibility, but its processing speed is limited and it is difficult to meet application scenarios with high real-time requirements in the industrial field; while the ASIC solution has a fast processing speed, but lacks flexibility. Once designed, it is very difficult to modify and expand its functions and cannot adapt to the constantly changing industrial protocol standards. Therefore, due to the above-mentioned deficiencies, how to provide an FPGA-based industrial protocol heterogeneous acceleration system with high flexibility and fast processing speed has become an urgent problem to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present invention is the problem that industrial protocol processing flexibility and processing speed cannot be achieved at the same time. The purpose is to provide an industrial protocol heterogeneous acceleration system based on FPGA, which solves the problems that the processing speed of the traditional CPU-based industrial protocol processing solution is limited and the ASIC-based industrial protocol processing solution lacks flexibility.

[0005] The present invention is realized through the following technical solutions:

[0006] In a first aspect, an industrial protocol heterogeneous acceleration system based on FPGA is provided, including:

[0007] A protocol parsing module, configured to receive industrial data sent by industrial devices and generate corresponding protocol parsing tasks;

[0008] A heterogeneous acceleration engine, configured to receive the protocol parsing tasks sent by the protocol parsing module and, according to the protocol parsing tasks, determine the best protocol parsing unit for processing the protocol parsing tasks, where the best protocol parsing unit is the software unit and hardware unit with the lowest load among the software units and hardware units for processing protocol parsing in the FPGA chip;

[0009] The protocol parsing module is further configured to call the optimal protocol parsing unit to identify the communication protocol type of the industrial data, and match the parsing rule corresponding to the communication protocol type from the stored protocol status table, so as to parse the industrial data according to the matched parsing rule to obtain a data parsing result;

[0010] Wherein, the protocol parsing module is configured with a protocol writing port, so as to write the parsing rule corresponding to the new communication protocol type into the protocol status table through the protocol writing port.

[0011] Based on the above disclosed content, the industrial protocol heterogeneous acceleration system provided by the present invention is provided with a protocol parsing module. Among them, the protocol parsing module is configured with a protocol writing port, and this protocol writing port is used to write the parsing rule corresponding to the new communication protocol type into the protocol status table in the protocol parsing module; thus, the present invention uses a configurable protocol status table for protocol parsing, and can dynamically adjust the parsing rule according to different industrial protocol standards. Based on this, the present invention can flexibly process different types of industrial protocols, thereby increasing the flexibility of use; at the same time, the present invention is also provided with a heterogeneous acceleration engine, which can determine the software and hardware with the lowest load among the software and hardware units for processing the task in the FPGA according to different task types, and schedule the software and hardware with the lowest load to perform protocol parsing; thus, through the collaborative work of software and hardware acceleration, the efficient processing of industrial protocols can be realized, and the processing speed can be improved.

[0012] Through the above design, the present invention provides a brand-new industrial protocol processing solution, which has the function of protocol parsing expansion, can flexibly process different types of industrial protocols, and can simultaneously achieve the efficient acceleration of multiple industrial protocol processing. Based on this, the overall stability and reliability of the industrial system can be improved, so it is very suitable for large-scale application and promotion.

[0013] In a possible design, the heterogeneous acceleration engine is configured to determine all hardware units and all software units corresponding to the protocol parsing task from the FPGA chip to form a running unit set according to the protocol parsing task;

[0014] The heterogeneous acceleration engine is configured to calculate the resource utilization rates of each hardware unit and each software unit in the running unit set, and screen out the hardware units and software units with resource utilization rates less than the utilization threshold from the running unit set to form an alternative unit set;

[0015] The heterogeneous acceleration engine is further configured to calculate the load balancing metrics of each alternative hardware unit and each alternative software unit in the set of alternative units, and determine the optimal protocol parsing unit based on the load balancing metrics of each alternative hardware unit and each alternative software unit. Among them, the larger the load balancing metric of any alternative hardware unit and any alternative software unit, the lower the load of the any alternative hardware unit and the any alternative software unit is characterized.

[0016] In a possible design, for any hardware unit, the heterogeneous acceleration engine is configured to obtain the first current processing task amount and the maximum computing amount of the any hardware unit, and calculate the resource utilization rate of the any hardware unit based on the first current processing task amount and the maximum computing amount.

[0017] For any software unit, the heterogeneous acceleration engine is configured to obtain the second current task amount and the performance metric of the any software unit, and calculate the resource utilization rate of the any software unit based on the performance metric and the second current task amount.

[0018] For any alternative hardware unit, the heterogeneous acceleration engine is further configured to sum the resource utilization rate and the load balancing coefficient of the any alternative hardware unit to obtain a summation result, and use the ratio between the load balancing coefficient and the summation result as the load balancing metric of the any alternative hardware unit.

[0019] In a possible design, the hardware unit in the optimal protocol parsing unit includes: a CRC calculation IP core, and each parsing rule in the protocol state table is in an encrypted state; wherein, the protocol parsing module is configured to call the optimal protocol parsing unit to detect the preamble in the industrial data, and call the optimal protocol parsing unit to parse the preamble to obtain a data frame header.

[0020] The protocol parsing module is configured to call the optimal protocol parsing unit to parse the data frame header to obtain the communication protocol type corresponding to the industrial data, and match the encrypted parsing rule corresponding to the communication protocol type from the protocol state table, so as to perform decryption processing on the encrypted parsing rule to obtain the parsing rule corresponding to the communication protocol type.

[0021] The protocol parsing module is configured to call the optimal protocol parsing unit and parse the industrial data through a state machine and the parsing rule to obtain a parsed data field.

[0022] The protocol parsing module is further configured to call the CRC calculation IP core to perform data verification processing on the parsed data field, and after the data verification passes, generate the data parsing result by using the parsed data field.

[0023] In a possible design, a protocol parsing module is configured to call the optimal protocol parsing unit to extract first feature data of the industrial data and second feature data of specified data, where the specified data is data sent by an industrial device received by the protocol parsing module at the (t - τ)th moment, and the tth moment is the receiving moment of the industrial data, and τ represents a time delay parameter;

[0024] The protocol parsing module is configured to call the optimal protocol parsing unit to obtain a device physical location code, and generate a first protocol feature vector of the industrial data based on the first feature data, the second feature data, and the device physical location code;

[0025] The protocol parsing module is configured to call the optimal protocol parsing unit and use the protocol feature vector to identify the communication protocol type of the industrial data; or

[0026] The protocol parsing module is configured to call the optimal protocol parsing unit to perform feature extraction processing on the industrial data to obtain a frame header feature, a frame structure feature, and a semantic feature of the industrial data;

[0027] The protocol parsing module is configured to call the optimal protocol parsing unit to perform feature integration on the frame header feature, the frame structure feature, and the semantic feature to obtain a second protocol feature vector;

[0028] The protocol parsing module is further configured to call the optimal protocol parsing unit to input the second protocol feature vector into a protocol type recognition model to obtain the communication protocol type of the industrial data.

[0029] In a possible design, the protocol parsing module includes: a dual-port RAM, a configuration controller, and a protocol parsing unit;

[0030] The dual-port RAM is configured with a protocol read port and the protocol write port. The configuration controller is configured to obtain a protocol description packet through the protocol write port and write the protocol description packet into a protocol status table in the dual-port RAM, and the protocol description packet contains parsing rules corresponding to a new communication protocol type;

[0031] The protocol parsing unit is configured to access the protocol status table in the dual-port RAM through the protocol read port based on a base address pointer to read out parsing rules corresponding to the communication protocol type of the industrial data from the protocol status table.

[0032] In a possible design, it further includes: a data cache and scheduling module;

[0033] The data caching and scheduling module is used to receive the data parsing result sent by the protocol parsing module and determine the processing time limit of the data parsing result;

[0034] The data caching and scheduling module is used to, when it is determined that the processing time limit is less than the time limit threshold, cache the data parsing result on-chip according to the multi-level caching strategy, or when it is determined that the processing time limit is greater than or equal to the time limit threshold, cache the data parsing result off-chip;

[0035] The data caching and scheduling module is used to calculate the scheduling priorities of the respective stored data in the on-chip cache and the off-chip cache;

[0036] The data caching and scheduling module is used to obtain the scheduling task requirements and, according to the scheduling task requirements, screen out at least one stored data corresponding to the scheduling task requirements from the on-chip cache and / or the off-chip cache as the scheduling data;

[0037] The data caching and scheduling module is further used to read and transfer the respective scheduling data from the on-chip cache and / or the off-chip cache in descending order of the scheduling priority and remove the respective scheduling data from the on-chip cache and / or the off-chip cache;

[0038] Wherein, when the scheduling priorities of the respective scheduling data are the same, the data caching and scheduling module is used to read and transfer the respective scheduling data from the on-chip cache and / or the off-chip cache according to the caching order of the respective scheduling data.

[0039] In a possible design, the data caching and scheduling module includes: a data caching unit;

[0040] The data caching unit is used to, when it is determined that the processing time limit is less than the time limit threshold, store the data parsing result in the first-level cache in the on-chip cache area according to the hybrid caching strategy;

[0041] The data caching unit is used to calculate the caching priorities of the respective data stored in the first-level cache, wherein the data stored in the first-level cache includes the data parsing result;

[0042] The data caching unit is further used to migrate the respective data stored in the first-level cache to the second-level cache in the on-chip cache area and perform data storage based on the caching priority and the hybrid caching strategy. The higher the caching priority of the data in the first-level cache, the more forward the position in the caching list in the second-level cache, and the faster the access speed at the more forward position.

[0043] In a possible design, the data caching unit is used to divide both the first-level cache and the second-level cache into a FIFO cache area and an LRU cache area;

[0044] A data cache unit, configured to determine whether there is free space in the FIFO cache area in the first-level cache, and when it is determined that there is no free space in the FIFO cache area in the first-level cache, determine whether there is free space in the LRU cache area in the first-level cache;

[0045] The data cache unit is configured to, when it is determined that there is no free space in the LRU cache area in the first-level cache, screen out first target data from the LRU cache area in the first-level cache or screen out second target data from the FIFO cache area in the first-level cache, and use the data parsing result to replace the first target data or the second target data, so as to complete the caching of the data parsing result after replacement;

[0046] Wherein, the first target data is data in the LRU cache area in the first-level cache whose usage times are less than a times threshold, and the second target data is the data that was written first in the FIFO cache area in the first-level cache.

[0047] In a possible design, it further includes: a network interface module;

[0048] The network interface module is configured to receive scheduling data sent by the data cache and scheduling module in the industrial protocol heterogeneous acceleration system, and generate a data transmission task to be sent to the heterogeneous acceleration engine;

[0049] The heterogeneous acceleration engine is configured to determine the best data processing unit for processing the data transmission task, wherein the best data processing unit includes a software unit for protocol conversion and data compression;

[0050] The network interface module is configured to call the best data processing unit to perform protocol conversion and data compression processing on the received scheduling data to obtain data to be transmitted;

[0051] The network interface module is further configured to send the data to be transmitted to a receiving device through a transmission interface, wherein the transmission interface includes an Ethernet interface, a CAN bus interface, and / or a WIFI interface.

[0052] In a second aspect, there is provided a method for industrial protocol heterogeneous acceleration based on an FPGA, wherein the method is executed by an industrial protocol heterogeneous acceleration system based on an FPGA, and the method includes:

[0053] The protocol parsing module receives industrial data sent by an industrial device and generates a corresponding protocol parsing task;

[0054] The heterogeneous acceleration engine receives the protocol parsing tasks sent by the protocol parsing module, and determines the optimal protocol parsing unit for processing the protocol parsing tasks according to the protocol parsing tasks, where the optimal protocol parsing unit is the software unit and the hardware unit with the lowest load among the software units and hardware units for processing protocol parsing in the FPGA chip;

[0055] The protocol parsing module calls the optimal protocol parsing unit to identify the communication protocol type of the industrial data, and matches the parsing rules corresponding to the communication protocol type from the stored protocol status table, so as to parse the industrial data according to the matched parsing rules to obtain a data parsing result;

[0056] Among them, the protocol parsing module is configured with a protocol writing port, so as to write the parsing rules corresponding to the new communication protocol type into the protocol status table through the protocol writing port.

[0057] In a third aspect, an FPGA-based industrial protocol heterogeneous acceleration device is provided. Taking the device as an electronic device as an example, it includes a memory, a processor, and a transceiver that are communicatively connected in sequence. Among them, the memory is used to store computer programs, the transceiver is used to send and receive messages, and the processor is used to read the computer programs and execute the FPGA-based industrial protocol heterogeneous acceleration method as described in the second aspect or any one of the possible designs in the second aspect.

[0058] In a fourth aspect, a storage medium is provided. Instructions are stored on the storage medium. When the instructions are run on a computer, they execute the FPGA-based industrial protocol heterogeneous acceleration method as described in the second aspect or any one of the possible designs in the second aspect.

[0059] In a fifth aspect, a computer program product containing instructions is provided. When the instructions are run on a computer, the computer is caused to execute the FPGA-based industrial protocol heterogeneous acceleration method as described in the first aspect or any one of the possible designs in the first aspect.

[0060] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0061] (1) The present invention provides a brand-new industrial protocol processing solution, which has a protocol parsing and extension function, can flexibly process different types of industrial protocols, and can simultaneously achieve efficient acceleration of multiple industrial protocol processing. Based on this, it can meet the application scenarios with high real-time requirements in the industrial field, thereby improving the overall stability and reliability of the industrial system. Therefore, the present invention is very suitable for large-scale application and promotion.

[0062] (2) The present invention adopts a multi-level cache structure, including on-chip cache and off-chip cache. Among them, the on-chip cache is used to temporarily store the data processed recently (i.e., the data with a processing time limit less than the time limit threshold) to improve the data access speed; while the off-chip cache is used to store a large amount of data with lower timeliness, so as to meet the storage requirements of big data volume in the industrial field. At the same time, the data cache and scheduling module can also schedule the data in the cache according to the priority requirements of the data. In this way, it can ensure that important data can be processed and transmitted in time. Based on this, the multi-level cache and intelligent scheduling strategy can effectively meet the storage and processing requirements of big data volume in the industrial field, avoid data backlog and loss, and thus improve the efficiency and reliability of data processing.

[0063] (3) The network interface module provided by the present invention adopts an integrated design with multiple network interfaces. In this way, the architecture can select a suitable network interface for data transmission according to the network environment and requirements in the industrial field. In this way, it can adapt to different network environments, thereby improving the versatility and scalability of the system.

[0064] (4) Compared with the traditional industrial protocol processing solutions based on CPU or ASIC, the FPGA-based architecture of the present invention has higher cost performance. That is, the reconfigurability of FPGA enables the system to be flexibly configured and upgraded according to different requirements, thus reducing the development and maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0066] Figure 1 is a schematic diagram of the architecture of the FPGA-based industrial protocol heterogeneous acceleration system provided by the embodiment of the present invention;

[0067] Figure 2 is a flowchart of the operation of the protocol parsing module provided by the embodiment of the present invention;

[0068] Figure 3 is a timing diagram of the protocol parsing provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to embodiments and the accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention; it should be understood that although terms such as first and second may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, the first unit may be referred to as the second unit, and similarly, the second unit may be referred to as the first unit, without departing from the scope of the exemplary embodiments of the present invention.

[0070] Embodiment:

[0071] Referring to Figure 1 As shown, the industrial protocol heterogeneous acceleration system based on FPGA provided in this embodiment may, but is not limited to, include: a protocol parsing module and a heterogeneous acceleration engine (which can be integrated in the FPGA chip). Among them, the protocol parsing module is responsible for parsing industrial protocol data of different types. It adopts a configurable state machine structure and can dynamically adjust the parsing rules according to different industrial protocol standards; in this way, the flexibility of use can be improved; and the heterogeneous acceleration engine realizes efficient acceleration of industrial protocol processing through the collaborative acceleration of software and hardware units, thereby ensuring the data processing speed.

[0072] In specific applications, for example, the protocol parsing module is configured with a protocol writing port; in this way, the parsing rules corresponding to the new communication protocol type can be written into the protocol state table through the protocol writing port, so as to dynamically adjust the parsing rules according to different industrial protocol standards, so as to realize the dynamic expansion of the parsing rules in the protocol state table.

[0073] Optionally, one of the module architectures of the following disclosed protocol parsing modules:

[0074] In this embodiment, for example, the protocol parsing module may, but is not limited to, include: a dual-port RAM, a configuration controller, and a protocol parsing unit; among them, the dual-port RAM is configured with a protocol reading port and the aforementioned protocol writing port. The configuration controller is used to obtain a protocol description packet through the protocol writing port and write the protocol description packet into the protocol state table in the dual-port RAM (the protocol description packet contains the parsing rules corresponding to the new communication protocol type); in this way, the dynamic writing of parsing rules corresponding to different industrial protocols can be realized; at the same time, the protocol parsing unit is used to access the protocol state table in the dual-port RAM through the protocol reading port and based on the base address pointer, so as to read out the parsing rules corresponding to the communication protocol type of the industrial data from the protocol state table.

[0075] Further, for example, the foregoing protocol status table stores parsing rules corresponding to different communication protocol types, and each parsing rule is in an encrypted state. For example, AES-128 encryption is used and HMAC verification is performed during each loading to ensure the immutability of the protocol status table. Specifically, for each industrial protocol, its data frame format, field meaning, and parsing process can be predefined, and this information is stored in the on-chip memory of the FPGA (i.e., the buffer area of the dual-port RAM) in the form of a lookup table (i.e., the protocol status table). In this way, the protocol parsing module can match the parsing rules based on this table, and then realize the parsing of different types of industrial data.

[0076] Further, for example, the foregoing protocol write port can but is not limited to adopt a JTAG (Joint Test Action Group) interface or an SPI interface (Serial Peripheral Interface, a synchronous serial communication interface). In this way, it is equivalent to using the method of dual-port RAM + configuration controller to enable the entire system to support the function of updating the protocol parsing rules through the JTAG or SPI interface during operation, that is, to support adding, modifying, or deleting protocol parsing rules (such as adding new protocols such as MQTT industrial version) during the system operation process without stopping the machine or hardware modification.

[0077] At the same time, since a dual-port RAM is used to implement the writing and reading of the parsing rules, and the two ports in the dual-port RAM are independent of each other, that is, the protocol write port can write new parsing rules in real time, while the protocol read port is used for the protocol parsing module to read the parsing rules in real time. Therefore, the system supports parallel execution of read and write operations, and then can achieve the function of not interrupting the current parsing task when updating the rules.

[0078] In addition, in this embodiment, the protocol parsing unit is used to access the protocol status table in the dual-port RAM through the protocol read port and based on the base address pointer, so as to read out the parsing rules corresponding to the communication protocol type of the industrial data from the protocol status table. In this way, accessing the dual-port RAM based on the base address pointer (such as base_addr) enables the system to automatically read the updated state transition table only by updating base_addr = 0x14 after loading the new rules without restarting. Based on this, the real-time performance of the parsing can be ensured. Among them, the base address pointer refers to a specific memory address, which is used as the starting point for accessing the dual-port RAM. Through this base address pointer, the protocol parsing module can locate the position of the dual-port RAM in the memory and perform read and write operations on it.

[0079] With the above design, this embodiment adopts the dual-port independent operation and dual-buffer strategy of dual-port RAM, which can realize the "hot loading" of parsing rules. In this way, the problems of low efficiency and poor timeliness caused by the need to reconfigure the entire bitstream in traditional FPGAs can be avoided; at the same time, for the newly added protocol, only the corresponding state table needs to be written, and it supports unlimited expansion of protocol types (the prior art usually fixedly supports 3-5 protocols). Therefore, the flexibility of use is greatly improved; in addition, for example, three-level checksum and CRC check can also be set (it is more appropriate for the configuration controller to perform checks on resources and compatibility) to ensure zero errors in the dynamic loading process, so as to be applicable to industrial-grade high-reliability scenarios.

[0080] In this way, through the protocol parsing module with configurable parsing rules described above, the parsing of industrial protocols in different application scenarios can be satisfied, thus improving the flexibility of use.

[0081] After elaborating on the configuration process of the parsing protocol of the protocol parsing module, the protocol parsing process of industrial data can be elaborated. Among them, this embodiment provides a protocol parsing method based on software and hardware acceleration, that is, through a heterogeneous acceleration engine, the software and hardware units with the lowest load in the FPGA chip are selected to process the protocol parsing task to achieve efficient acceleration of industrial protocol processing.

[0082] In specific implementation, the protocol parsing module is used to receive industrial data sent by industrial devices and generate corresponding protocol parsing tasks and send them to the heterogeneous acceleration engine; the heterogeneous acceleration engine is used to, based on the protocol parsing tasks, screen out the software and hardware units that process the tasks and have the lowest load from each hardware unit and software unit of the FPGA chip, so that the protocol parsing module can perform the protocol parsing of industrial data by calling the aforementioned software and hardware units with the lowest load, thereby realizing efficient data processing to ensure the data processing speed.

[0083] In this embodiment, the following provides the specific working process of the heterogeneous acceleration engine:

[0084] In practical applications, the heterogeneous acceleration engine is used to determine all the hardware units and all the software units corresponding to processing the protocol parsing task from the FPGA chip according to the protocol parsing task, so as to form a set of running units; in this embodiment, it is equivalent to determining all the software and hardware units participating in the execution of the task in the FPGA chip according to the task type, and then using the selected software and hardware units to form a set of running units, so as to perform software and hardware acceleration according to the load of the software and hardware units subsequently, that is, selecting the software and hardware units with the lowest load from the software and hardware units executing the task to execute the current task; specifically, the input tasks can be classified into hardware-sensitive tasks (such as encryption calculation, high-speed data verification), software-sensitive tasks (such as dynamic data compression), and general tasks (such as complex protocol parsing, etc.) according to different tasks; therefore, the corresponding software units and / or hardware units for the corresponding tasks can be screened out in the FPGA chip according to different task types, so as to facilitate the subsequent screening of software and hardware units.

[0085] Furthermore, for example, the foregoing hardware units are implemented using the logic resources of the FPGA, that is: the basic units inside the FPGA (Field Programmable Gate Array) chip for implementing various digital logic functions can include, but are not limited to: logic units (such as one or more look-up tables (which are devices for implementing any logic function and are essentially a small RAM) and flip-flops, etc.), digital signal processing modules, block RAMs, clock management units, dedicated hard cores (such as processor cores, Ethernet MAC cores, PCIe cores, dedicated CRC calculation IP cores, etc.); in this way, the foregoing hardware units can be customized for specific industrial protocol processing tasks, such as data encryption, verification calculation, data conversion, etc.

[0086] At the same time, the software units are implemented based on the soft-core processor on the FPGA (such as MicroBlaze or Nios II) and are responsible for processing some complex protocol logics and algorithms, such as protocol conversion, data compression, etc.; in this way, through the accelerated collaborative work of software and hardware units, efficient acceleration of industrial protocol processing can be achieved.

[0087] After screening out the software and hardware units required for the current protocol parsing task, preliminary screening of the software and hardware units can be performed, that is: the heterogeneous acceleration engine is used to calculate the resource utilization rates of each hardware unit and each software unit in the set of running units, and screen out the hardware units and software units with resource utilization rates less than the utilization threshold from the set of running units to form a set of alternative units; in this embodiment, it is equivalent to performing real-time monitoring of the resource status of software and hardware units, so as to perform preliminary screening based on their resource status.

[0088] Optionally, one of the following calculation methods for publicly disclosing resource utilization rate:

[0089] Taking any hardware unit in the set of operating units as an example, the heterogeneous acceleration engine is first used to obtain the first current processing task volume and the maximum computing volume of the any hardware unit; then, based on the first current processing task volume and the maximum computing volume, the resource utilization rate of the any hardware unit is calculated; where, for example, the first current processing task volume includes the number of floating-point operations completed by the any hardware unit in unit time, and the maximum computing volume is the floating-point operation ability of the any hardware unit; for example, assuming that the any hardware unit has a floating-point operation ability of 1 TFLOPS and the actual number of floating-point operations completed per second is 0.3 TFLOPS, then the resource utilization rate of the any hardware unit is: 0.3 / 1 = 0.3; of course, the calculation process of the resource utilization of the remaining each hardware unit is the same as the foregoing example, and will not be elaborated here.

[0090] Similarly, for any software unit in the set of operating units, the heterogeneous acceleration engine is used to obtain the second current task volume and the performance index of the any software unit, and based on the performance index and the second current task volume, the resource utilization rate of the any software unit is calculated; in this embodiment, the performance index may but is not limited to include the maximum processing ability of the any software unit in unit time (i.e., the data processing volume in unit time), and the second current task volume is the actual processed data volume of the any software unit at present; for example, assuming that the maximum processing ability of the any software unit is to process 1000 protocol instructions per second and its current processed data volume is 400 pieces / second; then the resource utilization rate of the any software unit is: 400 / 1000 = 0.4; of course, the calculation process of the resource utilization rate of the remaining software units is also the same, and will not be elaborated here.

[0091] After calculating the resource utilization rates of each software and hardware unit in the set of operating units, the resource utilization rate can be used for preliminary screening, that is, screening out the hardware units and software units with resource utilization rates less than the utilization rate threshold from the set of operating units to form an alternative unit set; where, for example, the utilization rate threshold may but is not limited to be set to 0.8, that is, the software and hardware units with resource utilization rates less than 0.8 in the set of operating units are used as alternative hardware units and alternative software units.

[0092] After the preliminary screening of software and hardware units, the resource utilization rate can be used to calculate the load balancing metrics of each alternative software unit and each alternative hardware unit, so as to select the best protocol parsing unit for the current task (i.e., the protocol parsing task) based on the load balancing metrics, that is: the heterogeneous acceleration engine is also used to calculate the load balancing metrics of each alternative hardware unit and each alternative software unit in the set of alternative units, and determine the best protocol parsing unit based on the load balancing metrics of each alternative hardware unit and each alternative software unit. Among them, the larger the load balancing metric of any alternative hardware unit and any alternative software unit, the lower the load of the any alternative hardware unit and the any alternative software unit is characterized.

[0093] In specific applications, taking any alternative hardware unit as an example, the calculation process of the load balancing metric is described. Among them, for any alternative hardware unit, the heterogeneous acceleration engine is used to sum the resource utilization rate and the load balancing coefficient of the any alternative hardware unit to obtain a summation result, and use the ratio between the load balancing coefficient and the summation result as the load balancing metric of the any alternative hardware unit; in this embodiment, it is exemplified that the load balancing coefficient takes a value of 1; thus, through the foregoing method, the load balancing metrics of each alternative hardware unit and each alternative software unit can be calculated.

[0094] Then, the alternative software units and alternative hardware units can be screened based on the load balancing metrics. Among them, in this embodiment, according to the processing flow of the protocol parsing task, the alternative software and hardware units can be divided into different node units (for example, node 1 can use hardware unit A, hardware unit B, software unit C, etc.). Then, in the node unit, the software unit and / or hardware unit with the largest load balancing metric is selected, so as to use the software and / or hardware units selected by each node to form the best protocol parsing unit for the protocol parsing task; based on this, it can be ensured that during the execution of each task, the software and / or hardware units with the lowest load can be used on the corresponding execution nodes, thereby greatly improving the speed of data protocol processing.

[0095] Furthermore, in this embodiment, if the load balancing metrics of multiple alternative hardware units or multiple alternative software units are the same, then, priority is given to allocating to the unit whose processing capacity is more matched with the task requirements (for example, the encryption task is preferentially assigned to the hardware unit rich in multiplier resources).

[0096] Furthermore, in this embodiment, when the heterogeneous acceleration engine receives more than one data processing task, the heterogeneous acceleration engine is configured to determine the processing priorities of the respective data processing tasks according to the source data of each data processing task. Among them, the priorities corresponding to different data types are stored in the heterogeneous acceleration engine. For example, the priority of an emergency instruction in industrial control is high. Based on this, the processing priorities of the data processing tasks can be determined according to the data types of the source data of each data processing task. Then, the heterogeneous acceleration engine is configured to determine the optimal processing unit corresponding to each data processing task in the order from the highest to the lowest processing priority. In this way, it can ensure that high-priority tasks are executed first, thus ensuring the real-time performance of task execution.

[0097] In addition, when executing the current data processing task (such as executing a protocol parsing task), if the heterogeneous acceleration engine receives a new data processing task, the heterogeneous acceleration engine is configured to determine whether the priority of the new data processing task is higher than that of the current data processing task (the determination method of the priority is the same as the foregoing and will not be elaborated here). Among them, if it is determined that the priority of the new data processing task is higher than that of the current data processing task, at this time, the heterogeneous acceleration engine is configured to interrupt the execution of the current data processing task and re-determine all the hardware units and all the software units corresponding to the processing of the new data processing task from the FPGA chip to preferentially execute the new data processing task. In this way, it can ensure that high-priority tasks are executed first and allocate the software unit and / or hardware unit with the lowest load.

[0098] In specific applications, for example, this embodiment also sets up a dynamic adjustment and feedback optimization process, that is: during the task execution process, the resource utilization rates of each software and hardware unit are detected in real time, and when the change value of the resource utilization rate of any software unit and / or any hardware unit exceeds the threshold, the load balancing indicators of each software and hardware are recalculated to re-adjust and allocate the software and hardware units corresponding to the task. At the same time, periodic optimization can also be performed. For example, every T time (such as 100 ms), the average latency and throughput of task processing of each software and hardware unit are statistically analyzed to feedback and adjust the utilization rate threshold to adapt to the change of the workload.

[0099] Thus, the heterogeneous acceleration engine can utilize the software and hardware screening function to achieve the acceleration of data protocol processing, thereby ensuring the data processing speed. At the same time, for example, data interaction and collaborative work are carried out between each hardware unit and software unit through the internal bus of the FPGA to cooperate to achieve efficient industrial protocol processing.

[0100] After the software and hardware acceleration of the current task is completed using the heterogeneous acceleration engine, the current task can be executed, that is, the data protocol parsing is performed. Among them, the protocol parsing module is also used to call the best protocol parsing unit to identify the communication protocol type of the industrial data, and match the parsing rule corresponding to the communication protocol type from the stored protocol status table, so as to parse the industrial data according to the matched parsing rule to obtain a data parsing result.

[0101] In this embodiment, for example, the hardware unit in the best protocol parsing unit may include, but is not limited to, a CRC calculation IP core, which is used to perform verification on the parsed data to achieve error detection of the data.

[0102] See Figure 2 As shown, the protocol parsing module (executed by the protocol parsing unit in this module) is used to call the best protocol parsing unit to detect the preamble in the industrial data, and call the best protocol parsing unit to parse the preamble to obtain a data frame header. Specifically, it detects 0XAA55 in the industrial data to obtain the preamble. Then, the protocol parsing module is used to call the best protocol parsing unit to parse the data frame header to obtain the communication protocol type corresponding to the industrial data, and match the encryption parsing rule corresponding to the communication protocol type from the protocol status table, so as to perform decryption processing on the encryption parsing rule to obtain the parsing rule corresponding to the communication protocol type.

[0103] Next, the protocol parsing module is used to call the best protocol parsing unit and parse the industrial data through the state machine and the parsing rule to obtain a parsed data field (in this embodiment, a configurable state machine can be implemented using Verilog or VHDL hardware description language). Among them, see Figure 3 As shown, it is to parse the slave address (1 byte), function code (1 byte), and data area (8 bytes), so as to obtain a 10-byte parsed data field (that is, Figure 3 the check data in). Then, the protocol parsing module is also used to call the CRC calculation IP core to perform data verification processing on the parsed data field, and after the data verification passes, use the parsed data field to generate the data parsing result. In this way, the CRC calculation IP core ( Figure 3 the C0C check IP in) returns a 2-byte CRC value and compares it with the check value, then the check result can be obtained. If the two are the same, the check passes; otherwise, the check fails and data parsing needs to be performed again. Through the foregoing design, a dedicated CRC calculation IP core is used for CRC32 verification, and the processing speed reaches 1 Gbps, which can accelerate the verification and thus improve the data parsing speed.

[0104] In this embodiment, if the protocol parsing module fails to match the corresponding parsing rule in the protocol status table, it indicates that the currently input industrial data is an unknown protocol. At this time, an exception can be triggered and the currently received data can be discarded.

[0105] Furthermore, this embodiment also additionally provides two identification methods for the communication protocol types of industrial data:

[0106] Among them, the first identification method is:

[0107] The protocol parsing module is used to call the optimal protocol parsing unit to extract the first feature data of the industrial data and the second feature data of the specified data. Among them, the specified data is the data sent by the industrial device received by the protocol parsing module at the (t - τ)th moment, and the tth moment is the receiving moment of the industrial data, and τ represents the time delay parameter; in this embodiment, it is assumed that the historical industrial data of the Profibus protocol is received at the (t - τ)th moment, then the feature data of the historical industrial data using the Profibus protocol is extracted; at the same time, for example, the foregoing feature data may include, but is not limited to, data values, register statuses, function code-related features, etc.; in addition, the role of extracting the second feature data is: to capture the features of the remaining data at a certain moment in the past, reflecting the consideration of the temporal correlation or hysteresis between protocols.

[0108] After completing the feature extraction of the data received at different moments, the protocol parsing module is used to call the optimal protocol parsing unit to obtain the device physical location code, and generate the first protocol feature vector of the industrial data according to the first feature data, the second feature data, and the device physical location code; in this embodiment, for example, the device physical location code represents a set of fixed parameters or additional features, which are inherent attributes related to the protocol, such as static information such as device addresses, protocol versions, communication configurations, etc., and are used to supplement the description of data features; at the same time, for example, the foregoing first feature data, second feature data, and device physical location code can be concatenated into a vector to obtain the first protocol feature vector.

[0109] After completing the feature splicing, the communication protocol type can be identified based on the first protocol feature vector, that is: the protocol parsing module is used to call the optimal protocol parsing unit and use the protocol feature vector to identify the communication protocol type of the industrial data; in specific applications, for example, but not limited to, machine learning methods can be used to identify the communication protocol type of industrial data; such as, pre-collecting the first protocol feature vectors of multiple sample data, and labeling the communication protocol types of multiple sample data; then, using the first protocol feature vector of each sample data as input and the communication protocol type identification result of each sample data as output to train the neural network model, so as to obtain the trained model after the training is completed; finally, in actual use, the first protocol feature vector of the industrial data is input into the aforementioned trained model to obtain the communication protocol type of the industrial data.

[0110] Of course, the aforementioned neural network model can be, but is not limited to, a BNN model.

[0111] At the same time, since the data formats and semantics of different protocols in industrial scenarios are quite different, direct processing is difficult; therefore, converting the aforementioned industrial data into a unified protocol feature vector also has the following benefits: (1) eliminating heterogeneity, mapping different protocol data to the same feature space, facilitating unified analysis and processing; (2) fusing multi-source information, that is, integrating the features of different protocols, retaining their respective key information, and mining potential correlations between protocols; (3) adapting subsequent algorithms: providing standardized input for data-driven analysis methods such as machine learning and deep learning, improving model training efficiency and accuracy (such as when used for industrial equipment fault diagnosis and performance optimization, the model can learn data patterns more efficiently); for example, in addition to being used for the aforementioned communication protocol type identification, the first protocol feature vector can also be used for real-time monitoring and anomaly detection (by analyzing the dynamic changes of the first protocol feature vector, abnormal behavior in the industrial system (such as protocol communication anomalies, equipment operation failures, etc.) can be detected), as well as industrial decision support (i.e., based on the analysis results of the first protocol feature vector, optimizing workflows, adjusting equipment configurations, or formulating maintenance strategies); of course, the aforementioned uses are only for illustration and are not to be regarded as limitations of this application.

[0112] In addition to identifying the common protocol type of industrial data based on the aforementioned correlation features between the data, this embodiment provides a second protocol type identification method as follows:

[0113] The protocol parsing module is used to call the best protocol parsing unit to perform feature extraction processing on the industrial data to obtain the frame header features, frame structure features, and semantic features of the industrial data. In this embodiment, for example, the frame header features may include, but are not limited to, the protocol identification field, version number, control flag bits, etc. in the frame header (such as some protocol frame headers contain fixed magic numbers or protocol IDs), and the frame structure features may include, but are not limited to, the data frame length, the number of fields, the layout of specified fields (such as the position of the function code in Modbus, the address field in Profibus, etc.); while the semantic features include: the binary quantization of the semantic information of the specified data in the industrial data, such as read / write operation identifiers, response / request types, etc.; thus, through the foregoing feature extraction, the obtained frame header features, frame structure features, and semantic features can be used to form a second protocol feature vector, and the process is as follows:

[0114] The protocol parsing module is used to call the best protocol parsing unit to perform feature integration on the frame header features, the frame structure features, and the semantic features to obtain a second protocol feature vector; in specific applications, for example, the foregoing frame header features, frame structure features, and semantic features can be integrated into a binary feature vector, rather than relying solely on the frame header parsing result; thus, after obtaining the second protocol feature vector, it can be input into the protocol type recognition model to identify the communication protocol type of the industrial data, that is: the protocol parsing module is also used to call the best protocol parsing unit to input the second protocol feature vector into the protocol type recognition model to obtain the communication protocol type of the industrial data.

[0115] In specific implementation, for example, the protocol type recognition model may adopt, but is not limited to, a trained BNN model, which has three layers. The input layer is used to receive binary features (i.e., the foregoing second protocol feature vector). The hidden layer performs a dot product operation on the input features through a binary weight matrix, and then, after passing through a binary activation function (such as the sign function), outputs intermediate features; finally, the output layer further operates on the results of the hidden layer to output a binary classification result; among them, the number of output nodes in the last layer corresponds to the number of protocol types, and the activation state of the node represents the protocol to which it belongs; therefore, the binary result output by the BNN, after decoding, directly corresponds to a specific communication protocol type, such as output node 1 being activated representing Modbus, node 2 being activated representing Profibus, etc.; it should be understood that this process is classification, rather than "obtaining protocol rules", that is, judging which type of protocol the data frame "belongs to", rather than parsing out the complete rules of the protocol (such as message format, interaction logic, etc.)

[0116] Furthermore, compared with the CNN model, using the BNN model as the protocol type recognition model has the following advantages: By restricting weights and activation values to binary (0 or 1), BNN can significantly reduce the computational load and storage requirements (resource occupancy is only 1 / 10 of that of CNN). At the same time, on FPGA, hardware parallelism can be utilized to quickly implement binary operations (such as exclusive OR and bitwise operations). Ultimately, on the premise of ensuring high accuracy (99.2%), it meets the requirements of industrial scenarios for real-time performance and low resource consumption.

[0117] Of course, the training of the protocol type recognition model is as follows: Using the second protocol feature vectors of each sample data as the input and the communication protocol type recognition results of each sample data as the output, the BNN network is trained. Thus, after the training is completed, the aforementioned protocol type recognition model is obtained.

[0118] In summary, BNN realizes protocol type recognition through binary encoding of comprehensive features and efficient computing, and it is a lightweight industrial protocol classification scheme suitable for FPGA deployment.

[0119] Optionally, in this embodiment, any one of the aforementioned three protocol type recognition methods can be selected, and different recognition schemes can be flexibly deployed according to actual use, thereby improving the flexibility of use.

[0120] Through the above elaboration, the present invention provides a brand-new industrial protocol processing solution, which has a protocol parsing and extension function, can flexibly process different types of industrial protocols, and can simultaneously achieve efficient acceleration of multiple industrial protocol processing. Based on this, it can meet the application scenarios with high real-time requirements in industrial fields, thereby improving the overall stability and reliability of industrial systems. Therefore, the present invention is very suitable for large-scale application and promotion.

[0121] See Figure 1 As shown, in a possible design, in the second aspect of this embodiment, based on the first aspect of the foregoing embodiment, the data caching and scheduling are optimized, that is: The industrial protocol heterogeneous acceleration system based on FPGA further includes: a data caching and scheduling module; In specific applications, this module is used to cache and schedule the parsed data; Specifically, it adopts a multi-level caching structure, including on-chip caching and off-chip caching; Among them, on-chip caching is used to temporarily store recently processed data to improve data access speed; while off-chip caching is used to store a large amount of data to meet the storage requirements of big data in industrial fields; At the same time, when performing data scheduling, this module can also schedule the data in the cache according to the priority requirements of the data to ensure that important data can be processed and transmitted in a timely manner; In this way, the application of this module can effectively cope with the storage and processing requirements of big data in industrial fields, thereby avoiding data backlog and loss, and further improving the efficiency and reliability of data processing.

[0122] Among them, the working process of the data cache and scheduling module is as follows:

[0123] The data cache and scheduling module is used to receive the data parsing result sent by the protocol parsing module and determine the processing time limit of the data parsing result; in this embodiment, for example, data classification can be performed according to the data type in the data parsing result, such as being divided into control instruction data, monitoring data, status feedback data, etc., and different types of processing time limits can be set in advance, so as to determine the processing time limit of the data parsing result based on the parsed data type; further, the judgment of the data type can be realized according to the specified identification bit or protocol header information of the data. For example, the control instruction data has a specified protocol header encoding, and by parsing this encoding, it can be classified as control instruction data.

[0124] Among them, after obtaining the processing time limit of the data parsing result output by the foregoing protocol parsing module, the data parsing result can be stored on-chip or off-chip according to the processing time limit, that is: the data cache and scheduling module is used to, when it is judged that the processing time limit is less than the time limit threshold, cache the data parsing result on-chip according to the multi-level cache strategy, or when it is judged that the processing time limit is greater than or equal to the time limit threshold, cache the data parsing result off-chip; in this embodiment, for example, on-chip caching is implemented using Block RAM in the FPGA chip, and off-chip caching is implemented using an external DDR memory.

[0125] In specific applications, for example, the data cache and scheduling module may include, but is not limited to, a data cache unit and a data scheduling unit. Among them, the data cache unit is responsible for performing the data caching task, specifically:

[0126] The data cache unit is used to, when it is judged that the processing time limit is less than the time limit threshold, store the data parsing result in the first-level cache in the on-chip cache area according to the hybrid cache strategy; among them, this embodiment provides a hybrid cache strategy different from the traditional cache method, and its implementation process is as follows:

[0127] The data cache unit is used to divide the first-level cache into a FIFO cache area and an LRU cache area; among them, the storage spaces of the FIFO cache area and the LRU cache area in the first-level cache are different. For example, the FIFO cache area occupies 40% of the cache space of the first-level cache, while the LRU cache area occupies 60% of the cache space of the first-level cache; of course, the size ratio of the two areas can be adjusted according to the actual situation, and it is not limited to the foregoing example here.

[0128] Then, when caching the data parsing result in the first-level cache, the data cache unit is used to first determine whether there is free space in the FIFO cache area in the first-level cache, and when it is determined that there is no free space in the FIFO cache area in the first-level cache, determine whether there is free space in the LRU cache area in the first-level cache.

[0129] Wherein, when the data cache unit determines that there is no free space in the LRU cache area in the first-level cache, it screens out the first target data from the LRU cache area in the first-level cache or screens out the second target data from the FIFO cache area in the first-level cache, and uses the data parsing result to replace the first target data or the second target data, so as to complete the caching of the data parsing result after replacement.

[0130] In this embodiment, the first target data is the data with the number of usage times less than the threshold in the LRU cache area in the first-level cache, and the second target data is the data written first in the FIFO cache area in the first-level cache.

[0131] In specific implementation, when new data needs to be written into the first-level cache, it is first necessary to check whether there is free space in the FIFO cache area in the first-level cache. Among them, if there is no free space, check whether there is free space in the LRU cache area; similarly, when there is no free space in the LRU cache area, cache replacement is required.

[0132] Specifically, when cache replacement is required, the least recently used data is preferentially screened out from the LRU cache area in the first-level cache for replacement (such as the data with the number of usage times less than the threshold within 10 minutes or 1 hour as the first target data); in this embodiment, the selection of the first target data can be achieved by maintaining an access linked list. Among them, the head of the linked list represents the most recently used data, the tail of the linked list represents the least recently used data, and the number of usage times can be associated; in this way, the first target data can be selected based on this access linked list; based on this, using the data parsing result to replace the first target data in the LRU cache area can complete the storage of the data parsing result.

[0133] At the same time, when the number of usage times of the data in the LRU cache area is less than the threshold, that is, all the data in the LRU cache area are frequently used recently, at this time, it is necessary to select the data written first in the FIFO cache area in the first-level cache for replacement (that is, the data written first is used as the second target data) for replacement.

[0134] In this embodiment, if the data cache unit determines that there is free space in the FIFO buffer area of the first-level cache, it writes the data parsing result to the end of the FIFO buffer area in the first-level cache and records its writing time. Similarly, if it determines that there is free space in the LRU buffer area of the first-level cache, it moves the second target data in the FIFO buffer area of the first-level cache to the head of the LRU buffer area and writes the data parsing result to the end of the FIFO buffer area in the first-level cache (that is, when it determines that there is free space in the LRU buffer area, it moves the data written earliest in the FIFO buffer area to the head of the LRU buffer area (indicating most recently used), and then writes the new data to the end of the FIFO buffer area).

[0135] In this way, the aforementioned hybrid strategy combines the advantages of FIFO and LRU. Among them, the FIFO area can quickly process newly entered data, while the LRU area can retain the data that is frequently accessed. Based on this, by reasonably adjusting the sizes of the two areas and the data movement rules, the cache space can be utilized more effectively, thereby increasing the cache hit rate to 92%.

[0136] In this embodiment, the first-level cache usually has a relatively small capacity and a relatively fast access speed, and is used to temporarily store the data that has just entered the system. Therefore, a unique identifier can be assigned to each data in the first-level cache for subsequent management and search.

[0137] At the same time, after the first-level cache of the data parsing result is completed, the second-level cache can be performed, and the process is as follows:

[0138] The data cache unit is used to calculate the cache priority of each data stored in the first-level cache, where the data stored in the first-level cache includes the data parsing result. In specific applications, the data is cached at the second level through the cache priority of the data. The calculation formula for the cache priority of any data stored in the first-level cache is:

[0139] P = α × R + β × I + γ × U;

[0140] Wherein, P represents the cache priority of any one of the data, R represents the real-time index of the any one of the data, which can be obtained according to the data type of the any one of the data, that is, different data types are preset with different real-time indexes. For example, for data with high real-time requirements such as control instruction data, it can be set to 1, etc. I represents the importance index of the any one of the data, and this importance index is also obtained according to its data type. Different data types are also preset with different importance indexes; U represents the urgency index of the any one of the data, which can be obtained according to the generation time or preset processing time of the any one of the data (for example, the shorter the preset processing time, the more urgent the data, and different urgency index values can be set for different preset processing times); and α, β, and γ all represent weight coefficients.

[0141] After calculating the cache priorities of the respective data stored in the primary cache based on the foregoing formula, based on this, the respective data in the primary cache can be migrated to the secondary cache, and the process is as follows:

[0142] The data cache unit is further configured to migrate the respective data stored in the primary cache to the secondary cache in the on-chip cache area and perform data storage based on the cache priority and the hybrid cache policy. Among them, the higher the cache priority of the data in the primary cache, the more forward the position in the cache list of the secondary cache, and the more forward the position, the faster the access speed.

[0143] In this embodiment, the data cache unit also divides the secondary cache into a FIFO cache area and an LRU cache area; in this way, in the secondary cache, the respective data in the primary cache are sorted according to the priority, and the data with high cache priority are ranked in the front for priority processing; of course, when storing, it is also necessary to first determine whether there is free space in the FIFO cache area. If not, it is necessary to determine whether there is free space in the LRU cache area. If not, cache replacement is performed. The storage process can refer to the foregoing primary cache storage process. Only in the secondary cache, the cache priority is also added, that is, the data with high cache priority is stored first and stored in the front of the cache list; in this way, in the secondary cache (L2 Cache), the more forward the cache position, the closer the data is to the CPU core in the cache, or the data is ranked in the front in the access order of the cache. Based on this, the data with high cache priority can have a faster access speed.

[0144] In this way, through the foregoing description, the recently processed data can be cached on-chip by combining the hybrid cache policy and the cache priority, thereby improving the data access speed.

[0145] Of course, if the data cache unit determines that the processing time limit is greater than or equal to the time limit threshold, the data parsing result will be cached outside the chip (i.e., the tertiary cache); that is, for some data that does not need to be processed immediately, it can be stored in the tertiary cache. The tertiary cache usually has a large capacity but the slowest access speed. Among them, the tertiary cache can be used as a long-term storage area for data. When the system resources are idle, the data in the tertiary cache can be batch processed.

[0146] In this way, through the foregoing description, the caching of the data parsing data can be completed. Based on the foregoing multi-level cache structure, it can meet the data access speed while also meeting the storage requirements of the large amount of data in the industrial field.

[0147] Then, data scheduling can be performed. Among them, in this embodiment, data scheduling is performed according to the scheduling priorities of the stored data in the cache, that is:

[0148] The data cache and scheduling module (specifically, the data scheduling unit executes the data scheduling task) is used to calculate the scheduling priorities of the stored data in the on-chip cache and the off-chip cache. In specific applications, this embodiment calculates the scheduling priorities of the stored data based on the industrial 4.0 time-sensitive network standard, that is, uses the real-time nature of the stored data to obtain its corresponding scheduling priority.

[0149] Optionally, taking any stored data as an example for illustration:

[0150] For example, but not limited to, first obtain the current system time and the deadline of the any stored data. Among them, the deadline is used to represent the time limit when the any stored data needs to be processed or transmitted, and is usually a preset value. Then, obtain the maximum data transmission delay. Next, calculate the difference between the deadline and the current system time, and use the ratio between the difference and the maximum data transmission delay as the real-time value of the any stored data. Among them, the smaller the real-time value, the more urgent the data and the higher the real-time requirement. Finally, the scheduling priority of the any stored data can be divided according to the calculated real-time value. Specifically, when the real-time value is less than or equal to 0.2, the scheduling priority of the any stored data can be divided into 1 (indicating high priority). When the real-time value is greater than 0.2 and less than or equal to 0.5, the scheduling priority of the any stored data is divided into 2 (indicating medium priority); and when the real-time value is greater than 0.5, the scheduling priority of the any stored data is divided into 3 (indicating low priority).

[0151] Thus, after calculating the scheduling priorities of each stored data in the on-chip and off-chip caches, data scheduling can be performed based on this, that is: The data cache and scheduling module is used to obtain the scheduling task requirements, and according to the scheduling task requirements, filter out at least one stored data corresponding to the scheduling task requirements from the on-chip cache and / or off-chip cache as the scheduling data; then, the data cache and scheduling module is further used to read each scheduling data from the on-chip cache and / or off-chip cache for transmission in the order of decreasing scheduling priority, and remove each scheduling data from the on-chip cache and / or off-chip cache.

[0152] In this embodiment, it is equivalent to filtering data according to the scheduling task requirements, that is, filtering out the data that needs to be scheduled this time from the on-chip cache and / or off-chip cache; then, according to the scheduling priorities of the filtered data, data scheduling is performed, that is, preferentially reading the stored data with a high scheduling priority from the cache and transmitting it to the corresponding processing unit for processing; in this way, it can be ensured that important data can be processed and transmitted in a timely manner; of course, when transmitting, it is also necessary to ensure the integrity and accuracy of the data.

[0153] Furthermore, this embodiment is also provided with arbitration logic processing, that is, when multiple data requests compete for limited processing resources at the same time, arbitration is required, and the arbitration logic can adopt various strategies, such as fixed-priority arbitration, round-robin arbitration, etc.

[0154] This embodiment is described by taking fixed-priority arbitration as an example, that is: Check the scheduling priorities of the data requested to be processed, and preferentially process the data requests with high scheduling priorities. When the scheduling priorities of each scheduling data are the same, the data cache and scheduling module is used to read each scheduling data from the on-chip cache and / or off-chip cache for transmission according to the cache order of each scheduling data; in addition, after completing data scheduling, it is necessary to update the data status and cache status, such as removing the processed data from the cache or updating its priority information.

[0155] Thus, through the above multi-level cache process and scheduling process, industrial protocol data can be effectively managed, and the processing efficiency and real-time performance of the system can be improved.

[0156] After the data scheduling is completed, data transmission can be carried out. For example, this system can also be but is not limited to being provided with: a network interface module; among them, the network interface module is used to receive the scheduling data sent by the data caching and scheduling module in the industrial protocol heterogeneous acceleration system, and generate a data transmission task to be sent to the heterogeneous acceleration engine; then, the heterogeneous acceleration engine is used to determine the best data processing unit for processing the data transmission task, where the best data processing unit includes a software unit for protocol conversion and data compression; next, the network interface module is used to call the best data processing unit to perform protocol conversion and data compression processing on the received scheduling data to obtain the data to be transmitted; finally, the network interface module is also used to send the data to be transmitted to the receiving device through a transmission interface, and for example, the transmission interface can be but is not limited to including: an Ethernet interface, a CAN bus interface, and / or a WIFI interface.

[0157] In specific implementation, the network interface module is responsible for transmitting the processed data through the network; it supports multiple network interface standards, such as Ethernet, CAN bus, WiFi, etc.; in this way, the appropriate network interface can be selected for data transmission according to the network environment and requirements of the industrial site. At the same time, the network interface module also has the functions of data encapsulation and decapsulation, encapsulating the processed data into data packets that meet the requirements of the network protocol for sending, and decapsulating the data packets to restore them to the original data when receiving.

[0158] Furthermore, when sending data, protocol conversion and data compression are usually involved; among them, the heterogeneous acceleration engine can screen out the software unit with the lowest load in the software units for protocol conversion and data compression, so as to quickly complete protocol conversion and data compression; for example, according to the predefined protocol conversion rules, the structure, address format, control field, etc. of the data are adjusted specifically. For example, map and convert specific function codes in the Modbus protocol to the corresponding service instructions of the Profinet protocol, and re-encapsulate key information such as the data frame header and address mapping table to achieve the adaptation and conversion of data formats and interaction logics between different protocols.

[0159] Similarly, for data compression, the application program on the soft-core processor uses efficient compression algorithms (such as LZ77, Huffman coding, etc.) to process the data; taking LZ77 as an example, the software first scans the input data to identify repeatedly occurring data blocks, replaces the repeated blocks with pointers and length identifiers pointing to the already existing data blocks, greatly reducing data redundancy; during the compression process, the software dynamically maintains a dictionary table or index table, updates the data mapping relationship in real time, and finally outputs the compressed data to improve data storage and transmission efficiency.

[0160] After that, after the software unit completes protocol conversion or data compression preprocessing, it quickly transmits the data to the hardware unit through the bus for encryption or verification calculation, forming an efficient heterogeneous acceleration processing flow; finally, the data to be transmitted can be sent to the receiving device through the transmission interface, see Figure 1 As shown, for example, the receiving device can include but is not limited to the cloud and / or the host computer.

[0161] Through the foregoing design, the present invention has the following beneficial effects:

[0162] (1) The configured protocol parsing mechanism and the integrated design of multiple network interfaces enable the architecture to flexibly process different types of industrial protocols and adapt to different network environments, improving the versatility and scalability of the system.

[0163] (2) Through the collaborative work of the heterogeneous acceleration engine, combined with software and hardware acceleration, the processing speed of industrial protocols can be significantly improved, meeting the application scenarios with high real-time requirements in industrial fields.

[0164] (3) The multi-level cache and intelligent scheduling strategy can effectively handle the storage and processing requirements of large amounts of data in industrial fields, avoid data backlog and loss, and improve the efficiency and reliability of data processing.

[0165] (4) Compared with the traditional industrial protocol processing solutions based on CPU or ASIC, the FPGA-based architecture of the present invention has higher cost performance. The reconfigurability of FPGA enables the system to be flexibly configured and upgraded according to different requirements, reducing the development and maintenance costs.

[0166] In a possible design, the third aspect of this embodiment provides the performance comparison data between this system and the traditional industrial protocol processing system; among them, Table 1 below gives the performance comparison data of different protocol processing;

[0167] Table 1 is the performance comparison table of different protocol processing under the same standard

[0168] Table 1

[0169]

[0170]

[0171] It can be seen from Table 1 above that the total parsing time of this system is 105 ns (1000 frames / ms can be processed at a rate of 10 Mbps), and its processing time is much less than 210 μs in the traditional technology, which greatly improves the processing speed.

[0172] Table 2 is the performance comparison data of the multi-level cache

[0173] Table 2

[0174] Cache Hierarchy Capacity Access Latency Hit Rate Hit Rate of Traditional Solution Register Cache 64KB 1ns 92％ 75％ On-Chip RAM 512KB 5ns 85％ 68％ Off-Chip DDR4 8GB 80ns 99％ 95％

[0175] As can be seen from Table 2 above, by adopting the multi-level cache strategy, the present invention can reduce access latency and improve the hit rate.

[0176] Thus, the present invention can solve the deficiencies of existing industrial protocol processing solutions in terms of flexibility, processing speed, and data processing efficiency, realize the efficient processing of multiple industrial protocols and the rapid transmission of data, thereby improving the overall performance and reliability of industrial systems.

[0177] The fourth aspect of this embodiment provides an FPGA-based heterogeneous acceleration method for industrial protocols. Among them, the method is executed by the FPGA-based heterogeneous acceleration system in the first aspect of the embodiment, and the method includes:

[0178] The protocol parsing module receives industrial data sent by industrial devices and generates corresponding protocol parsing tasks.

[0179] The heterogeneous acceleration engine receives the protocol parsing tasks sent by the protocol parsing module, and determines the best protocol parsing unit for processing the protocol parsing tasks according to the protocol parsing tasks. Among them, the best protocol parsing unit is the software unit and hardware unit with the lowest load among the software units and hardware units for processing protocol parsing in the FPGA chip.

[0180] The protocol parsing module calls the best protocol parsing unit, identifies the communication protocol type of the industrial data, and matches the parsing rule corresponding to the communication protocol type from the stored protocol status table, so as to parse the industrial data according to the matched parsing rule to obtain a data parsing result.

[0181] Among them, the protocol parsing module is configured with a protocol writing port, so as to write the parsing rule corresponding to the new communication protocol type into the protocol status table through the protocol writing port.

[0182] For the working process, working details, and technical effects of the method provided in this embodiment, reference can be made to the first aspect of the embodiment, which will not be elaborated here.

[0183] The fifth aspect of this embodiment provides an FPGA-based heterogeneous acceleration device for industrial protocols. Taking the device as an electronic device as an example, it includes: a memory, a processor, and a transceiver that are communicatively connected in sequence. Among them, the memory is used to store computer programs, the transceiver is used to send and receive messages, and the processor is used to read the computer programs and execute the FPGA-based heterogeneous acceleration method described in the fourth aspect of the embodiment.

[0184] For the working process, working details, and technical effects of the electronic device provided in this embodiment, reference may be made to the first aspect of the embodiment, which will not be elaborated here.

[0185] In the sixth aspect of this embodiment, there is provided a storage medium storing instructions for the FPGA-based industrial protocol heterogeneous acceleration method described in the fourth aspect of the embodiment, that is, instructions are stored on the storage medium, and when the instructions run on a computer, they execute the FPGA-based industrial protocol heterogeneous acceleration method described in the fourth aspect of the embodiment.

[0186] Among them, the storage medium refers to a carrier for storing data, and may include, but is not limited to, floppy disks, optical discs, hard disks, flash memories, USB flash drives, and / or Memory Sticks, etc. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0187] For the working process, working details, and technical effects of the storage medium provided in this embodiment, reference may be made to the first aspect of the embodiment, which will not be elaborated here.

[0188] In the seventh aspect of this embodiment, there is provided a computer program product containing instructions, and when the instructions run on a computer, the computer is caused to execute the FPGA-based industrial protocol heterogeneous acceleration method described in the fourth aspect of the embodiment, where the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices

[0189] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An FPGA-based industrial protocol heterogeneous acceleration system, characterized in that, Including: A protocol parsing module, configured to receive industrial data sent by industrial devices and generate corresponding protocol parsing tasks; A heterogeneous acceleration engine, configured to receive the protocol parsing tasks sent by the protocol parsing module and, according to the protocol parsing tasks, determine the optimal protocol parsing unit for processing the protocol parsing tasks, wherein the optimal protocol parsing unit is the software unit and the hardware unit with the lowest load among the software units and hardware units for processing protocol parsing in the FPGA chip; The protocol parsing module is further configured to call the optimal protocol parsing unit, identify the communication protocol type of the industrial data, and match the parsing rules corresponding to the communication protocol type from the stored protocol status table, so as to parse the industrial data according to the matched parsing rules to obtain a data parsing result; Wherein, the protocol parsing module is configured with a protocol writing port, so as to write the parsing rules corresponding to the new communication protocol type into the protocol status table through the protocol writing port.

2. The industrial protocol heterogeneous acceleration system based on FPGA according to claim 1, wherein The heterogeneous acceleration engine is configured to determine all the hardware units and all the software units corresponding to processing the protocol parsing tasks from the FPGA chip according to the protocol parsing tasks, so as to form a set of operating units; The heterogeneous acceleration engine is configured to calculate the resource utilization rates of each hardware unit and each software unit in the set of operating units, and filter out the hardware units and software units with resource utilization rates less than the utilization threshold from the set of operating units, so as to form a set of alternative units; The heterogeneous acceleration engine is further configured to calculate the load balancing metrics of each alternative hardware unit and each alternative software unit in the set of alternative units, and determine the optimal protocol parsing unit based on the load balancing metrics of each alternative hardware unit and each alternative software unit, wherein the larger the load balancing metric of any alternative hardware unit and any alternative software unit, the lower the load of the any alternative hardware unit and the any alternative software unit.

3. The industrial protocol heterogeneous acceleration system based on FPGA according to claim 2, wherein For any hardware unit, the heterogeneous acceleration engine is configured to obtain the first current processing task amount and the maximum computing amount of the any hardware unit, and calculate the resource utilization rate of the any hardware unit based on the first current processing task amount and the maximum computing amount; For any software unit, the heterogeneous acceleration engine is configured to obtain the second current task amount and the performance metric of the any software unit, and calculate the resource utilization rate of the any software unit based on the performance metric and the second current task amount; For any alternative hardware unit, the heterogeneous acceleration engine is further configured to sum the resource utilization rate and the load balancing coefficient of the any alternative hardware unit to obtain a summation result, and use the ratio between the load balancing coefficient and the summation result as the load balancing metric of the any alternative hardware unit.

4. An FPGA-based industrial protocol heterogeneous acceleration system according to claim 1, characterized in that The hardware unit in the optimal protocol parsing unit includes: a CRC calculation IP core, and each parsing rule in the protocol status table is in an encrypted state; wherein, the protocol parsing module is configured to call the optimal protocol parsing unit to detect the preamble in the industrial data, and call the optimal protocol parsing unit to parse the preamble to obtain a data frame header; The protocol parsing module is used to call the optimal protocol parsing unit to parse the data frame header, obtain the communication protocol type corresponding to the industrial data, and match the encryption parsing rule corresponding to the communication protocol type from the protocol status table, so as to perform decryption processing on the encryption parsing rule to obtain the parsing rule corresponding to the communication protocol type; The protocol parsing module is used to call the optimal protocol parsing unit, and parse the industrial data through the state machine and the parsing rule to obtain the parsed data field; The protocol parsing module is further used to call the CRC calculation IP core to perform data verification processing on the parsed data field, and after the data verification passes, generate the data parsing result by using the parsed data field.

5. The industrial protocol heterogeneous acceleration system based on FPGA according to claim 4, wherein The protocol parsing module is used to call the optimal protocol parsing unit to extract the first feature data of the industrial data and the second feature data of the specified data, where the specified data is the data sent by the industrial device received by the protocol parsing module at the (t - τ)th moment, and the tth moment is the receiving moment of the industrial data, and τ represents the time delay parameter; The protocol parsing module is used to call the optimal protocol parsing unit to obtain the device physical location code, and generate the first protocol feature vector of the industrial data according to the first feature data, the second feature data, and the device physical location code; The protocol parsing module is used to call the optimal protocol parsing unit, and use the protocol feature vector to identify the communication protocol type of the industrial data; or The protocol parsing module is used to call the optimal protocol parsing unit to perform feature extraction processing on the industrial data to obtain the frame header feature, the frame structure feature, and the semantic feature of the industrial data; The protocol parsing module is used to call the optimal protocol parsing unit to perform feature integration on the frame header feature, the frame structure feature, and the semantic feature to obtain the second protocol feature vector; The protocol parsing module is further used to call the optimal protocol parsing unit to input the second protocol feature vector into the protocol type recognition model to obtain the communication protocol type of the industrial data.

6. The industrial protocol heterogeneous acceleration system based on FPGA according to claim 1, characterized in that The protocol parsing module includes: a dual-port RAM, a configuration controller, and a protocol parsing unit; The dual-port RAM is configured with a protocol read port and the protocol write port. Among them, the configuration controller is used to obtain the protocol description packet through the protocol write port and write the protocol description packet into the protocol status table in the dual-port RAM, and the protocol description packet contains the parsing rule corresponding to the new communication protocol type; The protocol parsing unit is used to access the protocol status table in the dual-port RAM through the protocol read port based on the base address pointer to read the parsing rule corresponding to the communication protocol type of the industrial data from the protocol status table.

7. A heterogeneous acceleration system for industrial protocols based on FPGA according to claim 1, characterized in that, It further includes: The data cache and scheduling module; The data cache and scheduling module is used to receive the data parsing result sent by the protocol parsing module and determine the processing timeliness of the data parsing result; A data caching and scheduling module, configured to, when it is determined that the processing time limit is less than the time limit threshold, perform on-chip caching of the data parsing result according to a multi-level caching strategy, or perform off-chip caching of the data parsing result when it is determined that the processing time limit is greater than or equal to the time limit threshold; A data caching and scheduling module, configured to calculate the scheduling priorities of each stored data in the on-chip cache and the off-chip cache; A data caching and scheduling module, configured to obtain scheduling task requirements, and according to the scheduling task requirements, screen at least one stored data corresponding to the scheduling task requirements from the on-chip cache and / or the off-chip cache as scheduling data; A data caching and scheduling module is further configured to read and transfer each scheduling data from the on-chip cache and / or the off-chip cache in descending order of scheduling priority, and remove each scheduling data from the on-chip cache and / or the off-chip cache; Wherein, when the scheduling priorities of each scheduling data are the same, the data caching and scheduling module is configured to read and transfer each scheduling data from the on-chip cache and / or the off-chip cache according to the caching order of each scheduling data.

8. An industrial protocol heterogeneous acceleration system based on FPGA according to claim 7, characterized in that, The data caching and scheduling module includes: a data caching unit; The data caching unit is configured to, when it is determined that the processing time limit is less than the time limit threshold, store the data parsing result in the first-level cache in the on-chip cache area according to a hybrid caching strategy; The data caching unit is configured to calculate the caching priorities of each data stored in the first-level cache, wherein the data stored in the first-level cache includes the data parsing result; The data caching unit is further configured to migrate each data stored in the first-level cache to the second-level cache in the on-chip cache area and perform data storage based on the caching priority and the hybrid caching strategy. The data with a higher caching priority in the first-level cache is ranked higher in the caching list in the second-level cache, and the higher the ranking, the faster the access speed.

9. The industrial protocol heterogeneous acceleration system based on FPGA according to claim 8, characterized in that, The data caching unit is configured to divide both the first-level cache and the second-level cache into a FIFO cache area and an LRU cache area; The data caching unit is configured to determine whether there is free space in the FIFO cache area of the first-level cache, and when it is determined that there is no free space in the FIFO cache area of the first-level cache, determine whether there is free space in the LRU cache area of the first-level cache; The data caching unit is configured to, when it is determined that there is no free space in the LRU cache area of the first-level cache, screen out a first target data from the LRU cache area of the first-level cache or screen out a second target data from the FIFO cache area of the first-level cache, and replace the first target data or the second target data with the data parsing result to complete the caching of the data parsing result after replacement; Wherein, the first target data is the data with the number of usage times less than the number threshold in the LRU cache area of the first-level cache, and the second target data is the data written first in the FIFO cache area of the first-level cache.

10. A heterogeneous acceleration system for industrial protocols based on FPGA according to claim 1, characterized in that, It further includes: A network interface module; A network interface module, configured to receive scheduling data sent by a data caching and scheduling module in an industrial protocol heterogeneous acceleration system and generate a data transmission task to be sent to a heterogeneous acceleration engine; A heterogeneous acceleration engine, configured to determine an optimal data processing unit for processing the data transmission task, wherein the optimal data processing unit includes a software unit for protocol conversion and data compression; A network interface module, configured to call the optimal data processing unit to perform protocol conversion and data compression processing on the received scheduling data to obtain data to be transmitted; The network interface module is further configured to send the data to be transmitted to a receiving device through a transmission interface, wherein the transmission interface includes an Ethernet interface, a CAN bus interface, and / or a WIFI interface.

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