Silicon carbide MOSFET with low on-resistance and optimized electromagnetism

Abstract

The invention relates to the field of semiconductors, in particular to a silicon carbide MOSFET with low on-resistance and optimized electromagnetism, a high-conductivity region is arranged in a junction field effect transistor region on the side of a Schottky barrier diode, the on-resistance is reduced, the current density uniformity is improved, Schottky barrier diode metal and a source electrode metal electrode are connected through a diversion slope, and the current density uniformity is improved. A junction field effect transistor region is integrated with a grounding metal shielding layer, gate source parasitic capacitance is reduced, inductive coupling is reduced, high-frequency stability is improved, a P-type shielding doping layer is arranged between a source groove and the junction field effect transistor region and between the source groove and an epitaxial layer, double isolation with the metal shielding layer is achieved, and electromagnetic interference is reduced. The high-conductivity region, the diversion slope and the P-type shielding doping layer cooperate to reduce the amplification of short-circuit resistance, prolong the short-circuit tolerance time and avoid the risk of thermal breakdown.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a silicon carbide MOSFET with low on-resistance and electromagnetic optimization. Background Art

[0002] In high-voltage and high-frequency scenarios such as new energy vehicles, industrial control, and renewable energy conversion, silicon carbide metal-oxide semiconductor MOSFETs have become core power devices due to their high breakdown field strength, low on-state loss, and high-temperature resistance. However, the existing MOSFETs with embedded Schottky barrier diodes have the following key problems in their structural design, which restrict the improvement of device performance:

[0003] In traditional silicon carbide MOSFETs, the horizontal length of the Schottky barrier diode is limited by the process accuracy, resulting in a narrow current path in the junction field-effect transistor region below it and a significant increase in resistance (15%-20% higher than the theoretical value). At the same time, the planar contact design of the metal of the Schottky barrier diode and the source metal electrode causes the current to concentrate at the contact edge, forming local hot spots (the temperature rises by more than 20°C), exacerbating the increase in contact resistance and device heating. Especially in the short-circuit condition, the current concentration effect is likely to cause local overheating failure.

[0004] The parasitic capacitance (Cgs) between the gate and the source and the inductive coupling effect are significantly enhanced, resulting in distorted drive signals, increased switching losses (accounting for about 30% of the total losses), and even parasitic oscillations, affecting the system stability.

[0005] In a short-circuit fault, the sudden increase in the resistance of the junction field-effect transistor region and the epitaxial layer will lead to overvoltage and overcurrent stress (the peak current can reach more than 10 times the rated value). Due to the single current path and low heat dissipation efficiency of the existing structure, it is difficult to achieve energy balance in a short time, resulting in a short-circuit withstand time of the device less than 5 μs, which cannot meet the requirements of high-reliability scenarios.

[0006] To address the above problems, the prior art has tried to increase the horizontal size of the Schottky barrier diode or optimize the gate insulating layer, but the former will increase the chip area (by 10%-15%), and the latter has limited improvement on parasitic parameters. Therefore, there is an urgent need for an innovative structure that takes into account low on-resistance, electromagnetic optimization, and short-circuit tolerance to fully utilize the advantages of silicon carbide MOSFETs in high-voltage and high-frequency scenarios. Summary of the Invention

[0007] To solve the problems mentioned in the above background art, the present invention provides a silicon carbide MOSFET with low on-resistance and electromagnetic optimization.

[0008] A silicon carbide MOSFET with low on-resistance and electromagnetic optimization provided by the present invention adopts the following technical solutions: It includes a junction field effect transistor region formed on an N-epitaxy for forming a junction field effect transistor region to regulate current; a P-type doped well adjacent to the junction field effect transistor region participates in forming a channel structure. The P-type doped well is a rectangular region. One long side and one short side of the region adjacent to the P-type doped well are adjacent to the junction field effect transistor region, and the other short side of the P-type doped well is adjacent to the gate trench. A gate metal layer is arranged inside the gate trench, and the device conduction is regulated through the gate voltage. The junction field effect transistor region is an octagonal region. When the first region side of the junction field effect transistor region forms a boundary with the N-epitaxy, the second region side of the junction field effect transistor region forms a boundary with the gate trench, the third region side of the junction field effect transistor region forms a boundary with the P-type doped well, the fourth region side of the junction field effect transistor region forms a boundary with the P-type doped well and the P-type ohmic contact region, and the fifth and sixth region sides of the junction field effect transistor region are coated with Schottky barrier diode metal on the outside. The Schottky barrier diode metal forms a junction with both the source metal electrode and the source trench, and the junction of the Schottky barrier diode metal and the source metal electrode is a diversion bevel.

[0009] Further, a metal shielding layer is introduced into the junction field effect transistor region and connected to the source metal electrode to form electromagnetic shielding, reducing the gate-source parasitic capacitance and inductive coupling.

[0010] Further, a high-conductivity region is arranged on one side of the junction field effect transistor region close to the Schottky barrier diode metal to broaden the current path and reduce the on-resistance.

[0011] Further, P-type shielding doping layers are arranged between the source trench and the junction field effect transistor region and between the source trench and the N-epitaxy.

[0012] Further, the P-type ohmic contact region is adjacent to both the P-type doped well, the N-type doped source contact region, and the source metal electrode.

[0013] Further, the N-type doped source contact region is adjacent to the P-type doped well, the gate trench, and the source metal electrode.

[0014] Further, an interlayer insulating layer is arranged between the gate metal layer and the source metal electrode.

[0015] Further, the N-epitaxy is formed on an N-type substrate, and the N-type substrate is connected to the drain metal electrode.

[0016] The beneficial effects of the present invention are as follows: The silicon carbide MOSFET with low on-resistance and electromagnetic optimization provided by the present invention systematically solves the bottlenecks of existing devices in terms of on-resistance, electromagnetic compatibility, and short-circuit resistance through innovative designs of the junction field effect transistor region, the Schottky barrier diode connection structure, and the electromagnetic shielding layer. The specific beneficial effects are as follows:

[0017] A highly conductive region with locally high-concentration N-type doping is introduced into the junction field-effect transistor region on one side of the Schottky barrier diode. By laterally expanding the current channel, the on-resistance of the junction field-effect transistor region is reduced, effectively offsetting the problem of increased resistance caused by the limited lateral length of the Schottky barrier diode. Compared with the traditional structure, the uniformity of the current density distribution during normal conduction is improved, avoiding the sudden increase in resistance caused by the narrow path, and ensuring that the device maintains low conduction loss in high-voltage and high-frequency scenarios.

[0018] The metal of the Schottky barrier diode and the source metal electrode form an inclined contact surface through a diversion slope. The contact area is increased compared with the traditional planar design, guiding the current to flow uniformly into the junction field-effect transistor region, reducing the contact resistance, and eliminating the local hot spots caused by edge current concentration. Under short-circuit conditions, the current concentration effect is weakened, and the thermionic emission current density in the Schottky barrier diode region decreases, effectively suppressing the thermal failure caused by the positive temperature feedback.

[0019] A grounded metal shielding layer (made of Al) is integrated in the junction field-effect transistor region and directly connected to the source metal electrode to form a high-frequency electromagnetic shield, reducing the gate-source parasitic capacitance (Cgs) and weakening the inductive coupling effect. The distortion of the drive signal is reduced, and the proportion of the switching loss is compressed to effectively avoid parasitic oscillation and improve the stability of the device in high-frequency scenarios.

[0020] The P-type shielding doping layer between the source trench, the junction field-effect transistor region, and the epitaxial layer further weakens the electric field coupling between the gate and the source by adjusting the local carrier concentration, and forms a double isolation in cooperation with the metal shielding layer, reducing the electromagnetic interference (EMI) radiation intensity of the device and meeting the strict industrial electromagnetic compatibility (EMC) standard.

[0021] The highly conductive region and the diversion slope cooperate to broaden the short-circuit current path. Combining the carrier regulation effect of the P-type shielding doping layer, the resistance increase in the junction field-effect transistor region and the epitaxial layer during short circuit is reduced, and the peak current stress is reduced. The short-circuit tolerance time of the device is improved, and the temperature drop rate in the Schottky barrier diode region after turn-off is increased, avoiding the risk of thermal breakdown. Brief Description of the Drawings

[0022] Figure 1 It is a schematic diagram of the overall structure of a silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to the present invention;

[0023] Figure 2 It is a schematic diagram of a partial structure of a silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to the present invention. Detailed Embodiments

[0024] An embodiment of the present invention discloses a silicon carbide MOSFET with low on-resistance and electromagnetic optimization. The present application discloses a silicon carbide MOSFET with low on-resistance and electromagnetic optimization, as Figure 1 - Figure 2 shown, including a junction field effect transistor region formed on the N-epitaxy for forming a junction field effect transistor region to regulate current; a P-type doped well adjacent to the junction field effect transistor region, which participates in forming a channel structure. The P-type doped well is a rectangular region. One long side and one short side of the region adjacent to the P-type doped well are adjacent to the junction field effect transistor region, and the other short side of the P-type doped well is adjacent to the gate trench; a gate metal layer is arranged inside the gate trench, and the device conduction is regulated by the gate voltage;

[0025] The junction field effect transistor region is an octagonal region. When the first region side of the junction field effect transistor region forms a boundary with the N-epitaxy, the second region side of the junction field effect transistor region forms a boundary with the gate trench, the third region side of the junction field effect transistor region forms a boundary with the P-type doped well, the fourth region side of the junction field effect transistor region forms a boundary with the P-type doped well and the P-type ohmic contact region, and the fifth and sixth region sides of the junction field effect transistor region are coated with Schottky barrier diode metal on the outside. The Schottky barrier diode metal forms junctions with the source metal electrode and the source trench, and the junction of the Schottky barrier diode metal and the source metal electrode is a diversion bevel.

[0026] Exemplarily, for the junction field effect transistor region, where:

[0027] The first region side maintains the intrinsic doping concentration of the epitaxy (1×10 16 cm -3 ), ensuring conductivity matching with the substrate; the second region side fits the inner wall of the gate trench, so that the gate electric field acts uniformly on the edge of the junction field effect transistor region.

[0028] The third region side is parallel to the long side of the rectangle of the P-type doped well, and a shallow junction (depth 1-2 μm) is formed by ion implantation to promote the lateral transport of channel carriers.

[0029] The fourth region side is connected to the short side of the P-type doped well and the P-type ohmic contact region, and a stepped doping transition is adopted to ensure low-resistance contact with the source metal.

[0030] The fifth and sixth region sides are covered with Schottky barrier diode metal on the outside, and the side lengths are designed according to the device current capacity. The high-conductivity region is located outside the fifth and sixth sides of the junction field effect transistor region close to the Schottky barrier diode metal, and a high-concentration N-type doping is formed by local ion implantation to laterally expand the current channel.

[0031] The diversion inclined plane is the junction region between the Schottky barrier diode metal and the source metal electrode. The inclination angle of the inclined plane is designed to be 30°-60°, and the contact area is increased by 40%-60% compared with the traditional planar structure, guiding the current to flow uniformly into the junction field effect transistor region and avoiding the edge concentration effect.

[0032] The inner wall of the gate trench is thermally oxidized to form a gate oxide layer, and the material is SiO2.

[0033] The gate metal layer is filled in the gate trench, and the material is aluminum (Al), which is connected to the external drive circuit through the metal interconnection process.

[0034] A P-type shielding layer is formed between the source trench and the junction field effect transistor region by ion implantation, and the doping concentration is 1×10 16 cm -3 .

[0035] Specifically, a metal shielding layer is introduced in the junction field effect transistor region and connected to the source metal electrode to form electromagnetic shielding, reducing the gate-source parasitic capacitance and inductive coupling.

[0036] Exemplarily, the source metal electrode material is aluminum (Al), and a nickel (Ni) diffusion barrier layer is deposited on the surface.

[0037] Specifically, a high-conductivity region is arranged on the side of the junction field effect transistor region close to the Schottky barrier diode metal to broaden the current path and reduce the on-resistance.

[0038] Specifically, P-type shielding doping layers are arranged between the source trench and the junction field effect transistor region and between the source trench and the N epitaxy.

[0039] Specifically, the P-type ohmic contact region is adjacent to the P-type doped well, the N-type doped source contact region, and the source metal electrode.

[0040] Exemplarily, the P-type ohmic contact region is adjacent to the P-type doped well, and the doping concentration is 1×10 18 cm -3 , and contacts the source metal electrode to reduce the work function difference at the contact interface.

[0041] Specifically, the N-type doped source contact region is adjacent to the P-type doped well, the gate trench, and the source metal electrode.

[0042] Exemplarily, the N-type doped source contact region is located above the P-type doped well, and the doping concentration is 1×10 19 cm -3 , and is formed by phosphorus ion implantation.

[0043] Specifically, an interlayer insulating layer is arranged between the gate metal layer and the source metal electrode.

[0044] Exemplarily, the interlayer insulating layer between the gate metal layer and the source metal electrode is made of silicon nitride (Si3N4).

[0045] Specifically, N epitaxy is formed on an N-type substrate, and the N-type substrate is connected to the drain metal electrode.

[0046] Exemplarily, the N-type substrate is made of highly doped silicon carbide (SiC) material with a doping concentration of 1×10 18 cm -3 , and titanium / nickel / silver (Ti / Ni / Ag) alloy is evaporated on the bottom surface as the drain metal electrode; N epitaxy grows above the substrate with a doping concentration of 1×10 16 cm -3 , and is prepared by chemical vapor deposition (CVD) process.

[0047] The low on-resistance and electromagnetic optimized silicon carbide MOSFET provided by the present invention systematically solves the bottlenecks of existing devices in on-resistance, electromagnetic compatibility and short-circuit resistance through innovative designs of the junction field effect transistor region, Schottky barrier diode connection structure and electromagnetic shielding layer. The specific beneficial effects are as follows:

[0048] A highly conductive region with local high-concentration N-type doping is introduced into the junction field effect transistor region on one side of the Schottky barrier diode. By laterally expanding the current channel, the on-resistance of the junction field effect transistor region is reduced, effectively offsetting the problem of increased resistance caused by the limited horizontal length of the Schottky barrier diode. Compared with the traditional structure, the uniformity of the current density distribution during normal conduction is improved, avoiding a sudden increase in resistance due to a narrow path, and ensuring that the device maintains low conduction loss in high-voltage and high-frequency scenarios.

[0049] The metal of the Schottky barrier diode and the source metal electrode form an inclined contact surface through a diversion slope, and the contact area is increased compared with the traditional planar design, guiding the current to evenly flow into the junction field effect transistor region, reducing the contact resistance, and eliminating the local hot spot caused by edge current concentration. Under short-circuit conditions, the current concentration effect is weakened, and the hot electron emission current density in the Schottky barrier diode region decreases, effectively suppressing the thermal failure caused by the positive temperature feedback.

[0050] A grounded metal shielding layer (made of Al) is integrated in the junction field effect transistor region and directly connected to the source metal electrode to form high-frequency electromagnetic shielding, reducing the gate-source parasitic capacitance (Cgs) and weakening the inductive coupling effect. The distortion degree of the drive signal is reduced, and the proportion of switching loss is compressed to, effectively avoiding parasitic oscillation and improving the stability of the device in high-frequency scenarios.

[0051] The P-type shielding doping layer between the source trench, the junction field effect transistor region, and the epitaxial layer further weakens the electric field coupling between the gate and the source by adjusting the local carrier concentration, and forms a double isolation in cooperation with the metal shielding layer, reducing the electromagnetic interference (EMI) radiation intensity of the device to meet the stringent industrial electromagnetic compatibility (EMC) standard.

[0052] The high-conductivity region and the diversion inclined plane cooperate to broaden the short-circuit current path. Combining with the regulation of carriers by the P-type shielding doping layer, the resistance increase of the junction field effect transistor region and the epitaxial layer during short circuit is reduced, and the peak current stress is reduced. The short-circuit tolerance time of the device is improved, and the temperature drop rate in the Schottky barrier diode region after turn-off is increased, avoiding the risk of thermal breakdown.

[0053] The manufacturing process of this low on-resistance and electromagnetic-optimized silicon carbide MOSFET includes: N-type substrate treatment: Select a highly doped silicon carbide (SiC) material as the N-type substrate.

[0054] Deposit a titanium / nickel / silver (Ti / Ni / Ag) alloy on the bottom surface of the substrate to form the drain metal electrode, and perform annealing treatment to ensure low-resistance contact.

[0055] N epitaxial layer growth: Use chemical vapor deposition (CVD) process to grow an N epitaxial layer on the N-type substrate and control the surface flatness.

[0056] Define a rectangular area by lithography, use boron ion implantation, and activate it by annealing to form a P-type doped well adjacent to the junction field effect transistor region.

[0057] On the outer sides of the fifth and sixth sides of the junction field effect transistor region close to the Schottky barrier diode metal, lithograph an area and perform phosphorus ion implantation to form a high-conductivity region with high-concentration N-type doping.

[0058] Inject phosphorus ions on one side of the P-type doped well to form an N-type doped source contact region, fabricate a P-type ohmic contact region on one side of the P-type doped well, and perform boron ion implantation to form a low-resistance contact layer.

[0059] Gate trench processing: Use dry etching (SF5 / O2 mixed gas) to form the gate trench, and grow a SiO2 gate oxide layer on the inner wall by thermal oxidation.

[0060] Source trench etching: Etch to form the source trench, leaving a spacing from the junction field effect transistor region and the N epitaxial layer. P-type shielding doping layer injection: In the gaps between the source trench and the junction field effect transistor region, and between the source trench and the N epitaxial layer, perform boron ion implantation after lithography, and form a P-type shielding doping layer after annealing.

[0061] Gate metal layer fabrication: Sputter an aluminum (Al) layer in the gate trench, and form the gate metal layer by lift-off lithography, which is metallically interconnected with the external drive circuit to control the threshold voltage.

[0062] Schottky Barrier Diode Metal and Current-Guiding Inclined Plane Structure: Deposit Schottky barrier diode metal (such as Ti / Pt / Au) outside the fifth and sixth sides of the junction field-effect transistor region, and form a current-guiding inclined plane through inclined photolithography and dry etching to increase the contact area with the source metal electrode.

[0063] Deposit Source Metal Electrode and Metal Shielding Layer: Sputter an aluminum layer as the source metal electrode, and deposit a nickel diffusion barrier layer on the surface; deposit an aluminum layer on the top of the junction field-effect transistor region to form a metal shielding layer, which is connected to the source metal electrode through a via hole to reduce the gate-source parasitic capacitance (Cgs).

[0064] Prepare Interlayer Insulating Layer: Between the gate metal layer and the source metal electrode, grow a silicon nitride (Si3N4) interlayer insulating layer through plasma-enhanced chemical vapor deposition (PECVD).

[0065] The above are all preferred embodiments of the present invention and do not limit the protection scope of the present invention accordingly. Therefore, all equivalent changes made according to the structure, shape, and principle of the present invention shall be covered within the protection scope of the present invention.

Claims

1. A silicon carbide MOSFET with low on-resistance and electromagnetic optimization, characterized in that It includes a junction field effect transistor region (110) formed on an N-epitaxy (111) for forming a junction field effect transistor region to regulate current; a P-type doped well (109) adjacent to the junction field effect transistor region (110) and participating in forming a channel structure. The P-type doped well (109) is a rectangular region. One long side and one short side of the region adjacent to the P-type doped well (109) are adjacent to the junction field effect transistor region (110), and the other short side of the P-type doped well (109) is adjacent to a gate trench (107). A gate metal layer (106) is disposed inside the gate trench (107), and the device conduction is regulated by a gate voltage. The junction field effect transistor region (110) is an octagonal region. When the first region side of the junction field effect transistor region (110) forms a boundary with the N-epitaxy (111), the second region side of the junction field effect transistor region (110) forms a boundary with the gate trench (107), the third region side of the junction field effect transistor region (110) forms a boundary with the P-type doped well (109), the fourth region side of the junction field effect transistor region (110) forms a boundary with the P-type doped well (109) and a P-type ohmic contact region (114). The fifth and sixth region sides of the junction field effect transistor region (110) are coated with a Schottky barrier diode metal (104) on the outside. The Schottky barrier diode metal (104) forms junctions with a source metal electrode (102) and a source trench (105), and the junction of the Schottky barrier diode metal (104) and the source metal electrode (102) is a current guiding inclined surface (115).

2. The silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 1, characterized in that, A metal shielding layer (117) is introduced into the junction field effect transistor region (110) and connected to the source metal electrode (102) to form electromagnetic shielding and reduce gate-source parasitic capacitance and inductive coupling.

3. The silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 2, wherein A high-conductivity region (116) is provided on one side of the junction field effect transistor region (110) close to the Schottky barrier diode metal (104) to broaden the current path and reduce the on-resistance.

4. A silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 3, characterized in that, P-type shielding doped layers (103) are provided between the source trench (105) and the junction field effect transistor region (110) and between the source trench (105) and the N-epitaxy (111).

5. The silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 4, characterized in that, The P-type ohmic contact region (114) is adjacent to the P-type doped well (109), an N-type doped source contact region (108), and the source metal electrode (102).

6. The silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 5, wherein The N-type doped source contact region (108) is adjacent to the P-type doped well (109), the gate trench (107), and the source metal electrode (102).

7. The silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 6, characterized in that, An interlayer insulating layer (101) is provided between the gate metal layer (106) and the source metal electrode (102).

8. A silicon carbide MOSFET with low on-resistance and electromagnetic optimization according to claim 7, characterized in that, The N-epitaxy (111) is formed on an N-type substrate (112), and the N-type substrate (112) is connected to a drain metal electrode.

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