Irradiation-reinforced SiC super-junction MOS structure and preparation process thereof

Abstract

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and particularly to an irradiated-reinforced SiC superjunction MOS structure and a preparation process thereof. Background Art

[0002] In the evolution process of modern power semiconductor devices, silicon carbide (SiC), with its excellent physical properties such as a wide bandgap, high breakdown electric field strength, high saturated electron drift velocity, and excellent thermal conductivity, has become an ideal material for constructing high-performance power devices. The superjunction metal-oxide-semiconductor field effect transistor (MOSFET) based on SiC, that is, the SiC superjunction MOS structure, combines the advantages of the superjunction structure in optimizing the electric field distribution, enhancing the breakdown voltage capability, and reducing the on-resistance, as well as the high-temperature and high-frequency characteristics of the SiC material itself, and shows great application potential in many frontier fields; In the prior art (Publication No.: CN210805778U), a SiC-MOS device structure is disclosed, which includes a metal drain, a silicon carbide N+ substrate, and a silicon carbide N- epitaxial layer arranged in sequence from bottom to top. The upper left and upper right of the silicon carbide N- epitaxial layer both have source trenches. Below the source trenches, there are a silicon carbide P+ doped region and a silicon carbide P-type doped region from top to bottom. The source trenches are all filled with Schottky contact metal. The gate trench has a gate structure inside and on the surface. The first mesa structure and the second mesa structure are both composed of a silicon carbide N- epitaxial layer, a silicon carbide P-type doped region, and a silicon carbide N+ source region. This application can regulate the Schottky barrier height to form a Schottky contact with a lower on-state voltage drop, significantly reduce the volume of the power electronic system, reduce the packaging cost, improve the reliability of system applications, greatly improve the basic performance and long-term application reliability, have a lower specific on-resistance, and have the characteristic of low leakage current; In the above technology, when the device is applied in fields such as aerospace, it needs to face a complex and harsh space radiation environment, and the problem of single-particle irradiation is particularly prominent. When high-energy particles pass through the device, they will collide violently with the lattice atoms inside the device, which may cause serious deterioration of the electrical performance of the device, such as single-event upset, single-event latch-up, or even single-event burnout, greatly limiting its application scope and reliability, and becoming a key problem to be solved urgently. Summary of the Invention

[0003] Object of the Invention: The object of the present invention is to solve the problem that when high-energy particles pass through the device, they will collide violently with the lattice atoms inside the device, which may cause serious deterioration of the electrical performance of the device, and may cause phenomena such as single-event upset, single-event latch-up, or even single-event burnout.

[0004] Technical solution: An irradiated and strengthened SiC superjunction MOS structure, which is composed of a number of juxtaposed MOS cells. A single MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate; the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a P+ layer, an N well layer, and a P well layer. A lightly doped N layer is provided at the middle of the N drift layer of a single MOS cell; Furthermore, on the left and right sides of the N drift layer inside a single MOS cell, symmetric P- layers are provided. The cross-sectional profiles of the two symmetric P- layers are both trapezoidal, and the bottoms of the two symmetric P- layers are both in contact with the upper surface of the N substrate layer.

[0005] Furthermore, a heavily doped N layer is formed by ion implantation at the bottom of the lightly doped N layer. The cross-sectional profile of the heavily doped N layer is concave, and the bottom of the heavily doped N layer is in contact with the upper surface of the N substrate layer.

[0006] Furthermore, an arc-shaped P- layer is formed by ion implantation inside the heavily doped N layer. The bottom of the arc-shaped P- layer is in contact with the upper surface of the N substrate layer.

[0007] Furthermore, lightly doped N-type half-layers are formed by ion implantation on both sides of the arc-shaped P- layer inside the heavily doped N layer.

[0008] Furthermore, the cross-sectional profiles of the lightly doped N-type half-layers are both rectangular, and the bottoms of the lightly doped N-type half-layers are in contact with the upper surface of the N substrate layer.

[0009] Furthermore, semi-circular side lightly doped N layers are formed by ion implantation on both sides inside the heavily doped N layer.

[0010] A preparation process for an irradiated and strengthened SiC superjunction MOS structure includes: S1. Select an N-type SiC substrate as the N substrate layer, check parameters such as the surface flatness and crystal orientation of the substrate to ensure compliance with process requirements. Place the N substrate layer into acetone and ethanol solutions in sequence, and use an ultrasonic cleaner for ultrasonic cleaning to remove organic impurities on the surface. Then soak the N substrate layer in a dilute hydrofluoric acid solution to remove the oxide layer on the surface. Subsequently, rinse it with deionized water and finally dry it with nitrogen or spin-dry it with a spin dryer; S2. Use chemical vapor deposition technology to grow the N drift layer on the cleaned N substrate layer; S3. Apply photoresist coating, exposure, and development to the middle region of the N-drift layer through lithography technology to form a rectangular mask pattern for the lightly doped N layer. Using ion implantation technology, inject nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer. After completing the implantation of the lightly doped N layer, remove the photoresist. Then, use lithography technology again to form a concave mask pattern in the bottom region of the lightly doped N layer, and inject nitrogen ions into the concave mask pattern area to form the heavily doped N layer. After the injection is completed, put it into an annealing furnace to repair lattice damage; S4. Use lithography technology to form trapezoidal mask patterns for the laterally symmetric P- layers on the left and right regions of the N-drift layer respectively. Then, use ion implantation technology to inject boron ions into the trapezoidal mask-covered area to form the laterally symmetric P- layers with a trapezoidal cross-sectional profile. After the injection, perform annealing treatment; S5. Inside the heavily doped N layer, form an arc mask pattern for the arc-shaped P- layer through lithography technology, and inject boron ions using ion implantation technology to form the arc-shaped P- layer. After the injection, perform annealing treatment; S6. Inside the heavily doped N layer and in the regions on both sides of the arc-shaped P- layer, use lithography and ion implantation technology to inject nitrogen ions to form the lightly doped N-type half-layers. After the injection, perform annealing treatment; S7. Define the regions of the P+ layer, the N well layer, and the P well layer respectively through lithography technology. For the P+ layer, use boron ion implantation; for the N well layer, use nitrogen ion implantation; for the P well layer, use boron ion implantation. After the injection is completed, perform annealing treatment to activate impurities and repair lattice damage; S8. Through lithography or sputtering technology, deposit and pattern the metal layer in sequence to form the ohmic contacts and Schottky contacts of the drain, the source, and the gate.

[0011] Beneficial effects: 1. In the present invention, by arranging a lightly doped N layer in the middle of the N-drift layer and arranging laterally symmetric trapezoidal P- layers on both sides of the N-drift layer, it can interact with the electrons in the N-drift layer, accelerate carrier recombination, reduce the influence of excess carriers on the device performance, effectively reduce the performance degradation caused by irradiation, and improve the reliability and stability of the device in the irradiation environment; 2. In the present invention, by forming a concave-shaped heavily doped N layer at the bottom of the lightly doped N layer, the carrier concentration in this region can be greatly increased, and the conductivity can be significantly enhanced. At the same time, it is correlated with the surrounding laterally symmetric P- layers, arc-shaped P- layers and other structures to jointly shape the internal electric field and carrier transmission path of the device, and then can effectively regulate the concentration and distribution of carriers and reduce the on-resistance; 3. By forming an arc-shaped P-layer below the heavily doped N-layer, the present invention reduces the interference of excess carriers on the core region of the device, further reduces the damage degree of irradiation to the device, significantly improves the anti-irradiation performance of the device. At the same time, by forming a lightly doped N-type half-layer with a rectangular cross-sectional profile inside the heavily doped N-layer and outside the arc-shaped P-layer, the over-concentration of the local electric field is avoided, and the overall breakdown voltage of the device is further improved, making the device more stable and reliable when operating in a high-voltage environment; 4. By adopting a semi-circular side lightly doped N-layer, the stress distribution of the internal structure of the device is more uniform, reducing the stress concentration problem caused by structural mismatch, thereby further enhancing the stability of the device and reducing the probability of structural defects occurring during the manufacturing and use of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention; Figure 2 is a schematic structural diagram of Embodiment 2 of the present invention; Figure 3 is a schematic structural diagram of Embodiment 3 of the present invention; Figure 4 is a schematic structural diagram of Embodiment 4 of the present invention; Figure 5 is a schematic structural diagram of Embodiment 5 of the present invention.

[0013] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N substrate layer; 5. N drift layer; 6. P+ layer; 7. N well layer; 8. P well layer; 9. Lightly doped N layer; 10. Side symmetric P-layer; 11. Heavily doped N layer; 12. Arc-shaped P-layer; 13. Lightly doped N-type half-layer; 14. Semi-circular side lightly doped N layer. DETAILED DESCRIPTION OF THE INVENTION

[0014] To make the technical solutions of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] As Figures 1-5 shown, according to one aspect of the present invention, a preparation process for an irradiation-hardened SiC superjunction MOS structure is provided, including: Step 1: Select an N-type SiC substrate as the N substrate layer 4. Check parameters such as the flatness and crystal orientation of the substrate surface to ensure compliance with process requirements. Place the N substrate layer 4 successively into acetone and ethanol solutions, and perform ultrasonic cleaning using an ultrasonic cleaner to remove organic impurities on the surface. Then, immerse the N substrate layer 4 in a dilute hydrofluoric acid solution to remove the surface oxide layer. Subsequently, rinse it thoroughly with deionized water, and finally dry it with nitrogen or spin-dry it with a spin dryer; this can remove organic impurities, oxide layers, and other contaminants on the surface of the N substrate layer 4, avoid these impurities from affecting the arrangement and combination of atoms during subsequent epitaxial growth, ensure that the N substrate layer 4 has good lattice matching and interface characteristics, thereby improving the quality of the subsequently grown semiconductor epitaxial layer, and laying a foundation for the preparation of a high-performance SiC superjunction MOS structure.

[0016] Step 2: Use chemical vapor deposition technology to grow an N drift layer 5 on the cleaned N substrate layer 4. The purpose is to grow an N drift layer 4 with specific thickness, doping concentration, and crystal quality on the N substrate layer 4, which serves as a key component of the MOS structure.

[0017] Step 3: Through photolithography technology, perform photoresist coating, exposure, and development in the middle area of the N drift layer 5 to form a rectangular mask pattern for the lightly doped N layer 9. Using ion implantation technology, inject nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer 9. After completing the implantation of the lightly doped N layer 9, remove the photoresist. Then, use photolithography technology again to form a concave mask pattern at the bottom area of the lightly doped N layer 9, and implant nitrogen ions into the concave mask pattern area to form the heavily doped N layer 11. After the implantation is completed, place it in an annealing furnace to repair lattice damage; by adjusting the doping concentration in the local area, the electrical properties of this area are changed, further optimizing the electric field distribution inside the device. The settings of the lightly doped N layer 9 and the heavily doped N layer 11 can effectively regulate the concentration and distribution of carriers, reduce the on-resistance, and at the same time enhance the stability of the device in an irradiation environment, providing a basis for the subsequent formation of other special structures and improving the overall performance of the device.

[0018] Step 4: Use photolithography technology to form trapezoidal mask patterns for the laterally symmetric P- layers 10 in the left and right areas of the N drift layer 5 respectively. Then, use ion implantation technology to inject boron ions into the area covered by the trapezoidal mask to form laterally symmetric P- layers 10 with a trapezoidal cross-sectional profile. After the injection, perform annealing treatment; through the interaction between the laterally symmetric P- layers 10 and the N drift layer 5, the electric field distribution can be made more uniform, avoiding the occurrence of local electric field concentration. A uniform electric field distribution helps to improve the breakdown voltage ability of the device, enabling the device to operate stably in a high-voltage environment and reducing the breakdown risk caused by uneven electric fields.

[0019] Step Five: Inside the heavily doped N layer 11, form an arc mask pattern of the arc-shaped P-layer 12 through photolithography technology. Inject boron ions using ion implantation technology to form the arc-shaped P-layer 12. After injection, perform annealing treatment. The arc-shaped P-layer 12 can utilize its own structure and doping characteristics to quickly collect and neutralize some of the carriers generated by irradiation, reduce the interference of excess carriers on the core area of the device, thereby effectively reducing the damage degree of irradiation to the device and enhancing the radiation resistance of the device.

[0020] Step Six: In the regions on both sides of the arc-shaped P-layer 12 inside the heavily doped N layer 11, inject nitrogen ions using photolithography and ion implantation technologies to form lightly doped N-type half-layers 13. After injection, perform annealing treatment. Forming lightly doped N-type half-layers 13 in specific regions of the heavily doped N layer 11 changes the charge distribution in this region, further optimizes the internal electric field of the device, thereby further avoiding premature breakdown of the device caused by overly concentrated electric fields, improving the breakdown voltage performance of the device, and enhancing its reliability in high-voltage environments.

[0021] Step Seven: Define the regions of the P+ layer 6, N-well layer 7, and P-well layer 8 respectively through photolithography technology. For the P+ layer 6, inject boron ions. For the N-well layer 7, inject nitrogen ions. For the P-well layer 8, inject boron ions. After injection, perform annealing treatment to activate impurities and repair lattice damage. Then, the core conductive channel and carrier injection region of the MOS device can be constructed. The P+ layer 6 provides a low-resistance carrier injection path. The N-well layer 7 and the P-well layer 8 cooperate with each other to form a conductive channel that can be regulated by the gate voltage, realizing the control of the device current.

[0022] Step Eight: Deposit and pattern the metal layer in sequence through photolithography or sputtering processes to form ohmic contacts and Schottky contacts for the drain 1, source 2, and gate 3.

[0023] Example 1 As Figure 1 shown, a radiation-hardened SiC superjunction MOS structure is provided, which is composed of a plurality of juxtaposed MOS cells. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, a P+ layer 6, an N-well layer 7, and a P-well layer 8. A lightly doped N layer 9 is provided in the middle of the N drift layer 5 of a single MOS cell. On the left and right sides of the N drift layer 5 inside a single MOS cell, side-symmetric P-layers 10 are provided. The cross-sectional profiles of the two side-symmetric P-layers 10 are both trapezoidal, and the bottom ends of the two side-symmetric P-layers 10 are both in contact with the upper surface of the N substrate layer 4. In a single MOS cell, the drain 1 serves as the current outflow terminal and is connected to the N substrate layer 4, responsible for exporting the current within the device. The source 2 and the gate 3 are used to control the conduction and cutoff of the current. The semiconductor epitaxial layer is the core functional area of the device. The N substrate layer 4 provides a stable substrate support and a low-resistance current path. The N drift layer 5 is the main voltage-bearing area and undertakes the role of withstanding high voltage. The lightly doped N layer 9 set in the middle changes the doping characteristics of this area, making the resistance distribution of the N drift layer 5 more reasonable. Side-symmetric P-layers 10 are provided on both sides of the N drift layer 5, and its cross-section is trapezoidal. This shape design enables the combination area of the side-symmetric P-layer 10 and the N drift layer 5 to better regulate the electric field distribution. The bottom end of the side-symmetric P-layer 10 contacts the N substrate layer 4, forming a charge compensation structure from the N substrate layer 4 to the N drift layer 5. In addition, the P+ layer 6, the N well layer 7, and the P well layer 8 cooperate with each other to form a conductive channel under the action of the gate voltage, realizing precise control of the current; That is, the holes in the side-symmetric P-layer 10 can interact with the electrons in the N drift layer 5, accelerating the carrier recombination, reducing the influence of excess carriers on the device performance, effectively reducing the performance degradation caused by irradiation, and improving the reliability and stability of the device in the irradiation environment.

[0024] Example 2 As Figure 2 shown, a heavily doped N layer 11 is formed at the bottom end of the lightly doped N layer 9 by ion implantation. The cross-sectional profiles of the heavily doped N layer 11 are all concave-shaped, and the bottom end of the heavily doped N layer 11 contacts the upper surface of the N substrate layer 4; A heavily doped N layer 11 with a concave cross-sectional profile is formed at the bottom end of the lightly doped N layer 9. The concave design makes the heavily doped N layer 11 present a structure feature with a middle depression and two convex sides in the transverse direction. Its bottom end maintains complete contact with the upper surface of the N substrate layer 4, forming a continuous conductive channel. Thus, it not only retains the high conductivity advantage of the heavily doped region but also specially regulates the electric field distribution through the concave profile, and cooperates with the surrounding side-symmetric P-layers 10 and other structures to construct a complex and orderly charge distribution system, and then can effectively regulate the concentration and distribution of carriers, reduce the on-resistance, and enhance the stability of the device in the irradiation environment.

[0025] Example 3 As Figure 3 shown, an arc-shaped P-layer 12 is formed inside the heavily doped N layer 11 by ion implantation. The bottom end of the arc-shaped P-layer 12 contacts the upper surface of the N substrate layer 4; An ion implantation process is used to implant boron ions at a specific energy and dose to form an arc-shaped P-layer 12 inside the heavily doped N layer 11. The bottom of the arc-shaped P-layer 12 is tightly attached to the upper surface of the N substrate layer 4. Its arc-shaped profile design cooperates with the heavily doped N layer 11 and other structures, changing the originally uniform charge distribution in the area to form an arc-shaped P-layer 12 with a certain thickness and doping concentration. This layer forms a PN junction with the heavily doped N layer 11, and together with the surrounding area, constructs a complex and ordered semiconductor structure system. The arc-shaped P-layer 12 can quickly collect and neutralize some of the carriers generated by radiation due to its doping characteristics and arc-shaped structure. When high-energy particles are incident, the holes in the arc-shaped P-layer 12 can combine with the electrons in the heavily doped N layer 11, reducing the interference of excess carriers on the core area of the device, further reducing the degree of damage to the device caused by radiation, and significantly improving the device's radiation resistance.

[0026] Example 4 like Figure 4 As shown, lightly doped N-type half layers 13 are formed inside the heavily doped N layer 11 and on both sides of the arc-shaped P-layer 12 by ion implantation. The cross-sectional profiles of the lightly doped N-type half layers 13 are all rectangular, and the bottom ends of the lightly doped N-type half layers 13 are in contact with the upper surface of the N substrate layer 4; After the heavily doped N layer 11 and the curved P-layer 12 have been formed, photolithography technology is used to precisely position the mask. A low dose of nitrogen ions is implanted into the area within the heavily doped N layer 11 and outside the curved P-layer 12, forming a lightly doped N-type half-layer 13 with a rectangular cross-section. The bottom of the lightly doped N-type half-layer 13 is in close contact with the upper surface of the N substrate layer 4. During the implantation process, parameters such as the energy and dose of the nitrogen ions are strictly controlled to ensure that the lightly doped N-type half-layer 13 has an appropriate doping concentration and depth. This ensures that the lightly doped N-type half-layer 13 cooperates with the heavily doped N layer 11 and the curved P-layer 12 in terms of electrical properties and spatial structure, jointly constructing a complex and orderly semiconductor internal structure system. This further changes the charge distribution state in the heavily doped N layer 11 region, making the electric field distribution in this region more refined and reasonable. This effectively mitigates the electric field mutation caused by the heavy doping and curved P-layer 12, avoids excessive local electric field concentration, further improves the overall voltage withstand capability of the device, and makes the device more stable and reliable when operating in a high-voltage environment.

[0027] Example 5 like Figure 5 As shown, a semicircular lightly doped N layer 14 is formed on both sides of the heavily doped N layer 11 by ion implantation; Nitrogen ion implantation is performed through a semicircular mask to form a semicircular side lightly doped N layer 14, whose geometric structure matches the electric field distribution and effectively neutralizes the excess electrons in the heavily doped N layer 11; Thus, the stability of the internal structure of the device is enhanced. Its semi-circular design can better adapt to internal stress changes, reduce the stress concentration problem caused by structural mismatch, lower the probability of structural defects occurring during the manufacturing and use of the device, and further ensure the stable performance of the device.

[0028] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. An irradiated and strengthened SiC superjunction MOS structure, which is composed of a plurality of juxtaposed MOS cells. A single MOS cell includes a drain (1), a semiconductor epitaxial layer, a source (2) and a gate (3); the semiconductor epitaxial layer includes an N substrate layer (4), an N drift layer (5), a P+ layer (6), an N well layer (7) and a P well layer (8), and is characterized in that: A lightly doped N layer (9) is provided in the middle of the N drift layer (5) of a single MOS cell.

2. The irradiated and strengthened SiC superjunction MOS structure according to claim 1, characterized in that: On the left and right sides of the N drift layer (5) inside a single MOS cell, laterally symmetric P-layers (10) are provided. The cross-sectional profiles of the two laterally symmetric P-layers (10) are both trapezoidal, and the bottoms of the two laterally symmetric P-layers (10) are both in contact with the upper surface of the N substrate layer (4).

3. The irradiated and strengthened SiC superjunction MOS structure according to claim 1, wherein: A heavily doped N layer (11) is formed by ion implantation at the bottom of the lightly doped N layer (9). The cross-sectional profile of the heavily doped N layer (11) is concave, and the bottom of the heavily doped N layer (11) is in contact with the upper surface of the N substrate layer (4).

4. A radiation-hardened SiC superjunction MOS structure according to claim 3, characterized in that: An arc-shaped P-layer (12) is formed by ion implantation inside the heavily doped N layer (11). The bottom of the arc-shaped P-layer (12) is in contact with the upper surface of the N substrate layer (4).

5. The irradiated and strengthened SiC superjunction MOS structure according to claim 4, characterized in that: Lightly doped N-type half-layers (13) are formed by ion implantation on both sides of the arc-shaped P-layer (12) inside the heavily doped N layer (11).

6. The irradiated and strengthened SiC superjunction MOS structure according to claim 5, characterized in that: The cross-sectional profiles of the lightly doped N-type half-layers (13) are both rectangular, and the bottoms of the lightly doped N-type half-layers (13) are in contact with the upper surface of the N substrate layer (4).

7. A radiation-hardened SiC superjunction MOS structure according to claim 6, characterized in that: Semicircular side lightly doped N layers (14) are formed by ion implantation on both sides inside the heavily doped N layer (11).

8. A preparation process for an irradiated-reinforced SiC superjunction MOS structure, characterized in that, Applied to the irradiated-reinforced SiC superjunction MOS structure according to any one of claims 1-7, the preparation process of the irradiated-reinforced SiC superjunction MOS structure includes the following steps: S1. Select an N-type SiC substrate as the N substrate layer (4), check parameters such as the surface flatness and crystal orientation of the substrate to ensure compliance with process requirements. Place the N substrate layer (4) successively into acetone and ethanol solutions, and use an ultrasonic cleaner for ultrasonic cleaning to remove organic impurities on the surface. Then soak the N substrate layer (4) in a dilute hydrofluoric acid solution to remove the oxide layer on the surface. Subsequently, rinse it with deionized water and finally dry it with nitrogen or spin-dry it with a spin dryer. S2. Use chemical vapor deposition technology to grow the N drift layer (5) on the cleaned N substrate layer (4). S3. Through photolithography technology, apply photoresist, expose, and develop in the middle area of the N drift layer (5) to form a rectangular mask pattern for the lightly doped N layer (9). Use ion implantation technology to inject nitrogen ions into the rectangular mask pattern area to form the lightly doped N layer (9). After completing the injection of the lightly doped N layer (9), remove the photoresist. Again, use photolithography technology to form a concave mask pattern in the bottom area of the lightly doped N layer (9), and inject nitrogen ions into the concave mask pattern area to form the heavily doped N layer (11). After the injection is completed, put it into an annealing furnace to repair lattice damage. S4. Use lithography technology to form a trapezoidal mask pattern that laterally symmetrically defines the P-layer (10) on the left and right regions of the N-drift layer (5) respectively. Then, adopt an ion implantation process to implant boron ions into the region covered by the trapezoidal mask, forming the laterally symmetric P-layer (10) with a trapezoidal cross-sectional profile. After implantation, perform an annealing treatment. S5. Inside the heavily doped N-layer (11), use lithography technology to form an arc mask pattern for the arc-shaped P-layer (12). Adopt an ion implantation process to implant boron ions to form the arc-shaped P-layer (12). After implantation, perform an annealing treatment. S6. Inside the heavily doped N-layer (11) and in the regions on both sides of the arc-shaped P-layer (12), use lithography and ion implantation processes to implant nitrogen ions to form the lightly doped N-type half-layers (13). After implantation, perform an annealing treatment. S7. Use lithography technology to respectively define the regions of the P+ layer (6), the N-well layer (7), and the P-well layer (8). For the P+ layer (6), use boron ion implantation. For the N-well layer (7), use nitrogen ion implantation. For the P-well layer (8), use boron ion implantation. After the implantation is completed, perform an annealing treatment to activate the impurities and repair the lattice damage. S8. Through lithography or sputtering processes, sequentially deposit and pattern a metal layer to form ohmic contacts and Schottky contacts for the drain (1), the source (2), and the gate (3).

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