Frequency calibration method and circuit, electronic equipment, chip and medium

Abstract

The embodiment of the invention provides a frequency calibration method and circuit, electronic equipment, a chip and a medium, and relates to the field of integrated circuits, and the method comprises the steps: determining the input power of a voltage-controlled oscillator group based on a preset calibration interval; traversing a capacitor array of a first voltage-controlled oscillator in the voltage-controlled oscillator group, determining the output power of the first voltage-controlled oscillator under the input power until the input power and the output power meet an injection locking condition, and obtaining a target control value of the capacitor array of the first voltage-controlled oscillator, the target control value is used for determining the calibration frequency of the first voltage-controlled oscillator. According to the method provided by the invention, the calibration efficiency and the frequency switching speed are improved while the calibration precision is ensured, so that the frequency hopping capability of the whole signal chain system is greatly improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of integrated circuits, and in particular to a frequency calibration method and circuit, electronic equipment, chip, and medium. Background Art

[0002] With the development of the integrated circuit industry, clock circuits are increasingly used, especially in the field of low power consumption and low latency. Traditional counting methods are commonly used to measure frequency, converting the frequency value into the digital domain for frequency calibration. However, this method takes a long time to obtain high frequency reading accuracy and is not suitable for scenarios with low startup time and latency requirements. Summary of the Invention

[0003] The present disclosure provides a frequency calibration method and circuit, electronic equipment, chip and medium to solve the problem of excessively long calibration time caused by needing to count the frequency of a voltage-controlled oscillator multiple times and steps.

[0004] A first aspect embodiment of the present disclosure proposes a frequency calibration method, which includes: determining the input power of a voltage-controlled oscillator group based on a preset calibration area; traversing the capacitor array of a first voltage-controlled oscillator in the voltage-controlled oscillator group to determine the output power of the first voltage-controlled oscillator under the input power until the input power and the output power meet the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage-controlled oscillator, and the target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

[0005] In some embodiments of the present disclosure, the input power of the voltage-controlled oscillator group is determined based on a preset calibration interval, including: configuring an initial frequency, using the initial frequency as an input signal of a fractional phase-locked loop, and determining an output signal; performing frequency multiplication processing on the output signal to obtain a first signal; and performing power regulation processing on a first power of the first signal based on the preset calibration interval to obtain the input power of the voltage-controlled oscillator group.

[0006] In some embodiments of the present disclosure, power regulation processing is performed on the first power of the first signal based on a preset calibration interval, including: initializing correction of the theoretical power value to obtain the correction power; when the correction power meets the preset correction power, power regulation processing is performed on the first power according to the preset calibration interval through active filtering and / or passive filtering to obtain the input power.

[0007] In some embodiments of the present disclosure, a capacitor array of a first voltage-controlled oscillator in a voltage-controlled oscillator group is traversed to determine the output power of the first voltage-controlled oscillator under input power, including: determining the first voltage-controlled oscillator based on a first control signal, the first control signal being used to control switches of the voltage-controlled oscillators in the voltage-controlled oscillator group; determining a first control value of the capacitor array of the first voltage-controlled oscillator based on a second control signal, the second control signal being used to determine a traversal position of the capacitor array of the first voltage-controlled oscillator; and determining a first output power of the first voltage-controlled oscillator according to the first control value and the input power.

[0008] In some embodiments of the present disclosure, the method further includes: determining a second control value of the capacitor array of the first voltage-controlled oscillator based on a second control signal when the first output power and input power of the first voltage-controlled oscillator do not satisfy the injection locking condition; determining the second output power of the first voltage-controlled oscillator according to the second control value and the input power until the second output power and the input power satisfy the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage-controlled oscillator.

[0009] In some embodiments of the present disclosure, the method further includes: when the first output power and input power of the first voltage-controlled oscillator meet an injection locking condition, determining the output frequency of the first voltage-controlled oscillator at the first control value as the calibration frequency of the first voltage-controlled oscillator.

[0010] In the above embodiment, power regulation is combined with injection locking detection. Power regulation can determine the input power of the voltage-controlled oscillator group according to the frequency range to be calibrated. Injection locking detection can quickly detect the input power and output power, and quickly lock the target control value when the two are close. This can significantly reduce the time required for voltage-controlled oscillator frequency calibration while maintaining calibration accuracy.

[0011] The second aspect of the present disclosure proposes a frequency calibration circuit, including a power regulation module, a detection module, and a calibration module. The power regulation module is used to determine the input power of the voltage-controlled oscillator group in the calibration module based on a preset calibration interval; the calibration module is connected to the power regulation module and the detection module respectively, and is used to traverse the capacitor array of the first voltage-controlled oscillator in the voltage-controlled oscillator group to determine the output power of the first voltage-controlled oscillator under the input power; the detection module is used to perform injection locking detection on the input power and output power, and when the input power and output power meet the injection locking conditions, obtain the target control value of the capacitor array of the first voltage-controlled oscillator, and the target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

[0012] In some embodiments of the present disclosure, the frequency calibration circuit also includes a clock module, a phase-locked loop module, and a frequency multiplication module: the clock module is used to configure the initial frequency, and the clock module is connected to the phase-locked loop module; the phase-locked loop module is used to use the initial power as an input signal to determine the output signal; the frequency multiplication module is respectively connected to the phase-locked loop module and the detection module, and is used to perform frequency multiplication processing on the output signal output by the phase-locked loop module to obtain a first signal, and send the first signal to the detection module.

[0013] In some embodiments of the present disclosure, the frequency calibration circuit also includes a digital calibration logic module, which is connected to the detection module and the calibration module, and is used to receive the injection locking detection result output by the detection module, and determine a first control signal and a second control signal based on the injection locking detection result, the first control signal is used to control the switch of the voltage-controlled oscillator in the voltage-controlled oscillator group, and the second control signal is used to determine the traversal gear of the capacitor array of the first voltage-controlled oscillator; the power regulation module is also used to initialize and correct the theoretical power value to obtain the corrected power; when the corrected power meets the preset corrected power, the first power of the first signal is power regulated according to the preset calibration interval through active filtering and / or passive filtering to obtain the input power.

[0014] In the above embodiment, the frequency calibration circuit can significantly reduce the time required for voltage-controlled oscillator frequency calibration while maintaining the calibration accuracy.

[0015] The third aspect embodiment of the present disclosure proposes a frequency calibration device, including: a determination module, used to determine the input power of a voltage-controlled oscillator group based on a preset calibration interval; a calibration module, used to traverse the capacitor array of a first voltage-controlled oscillator in the voltage-controlled oscillator group, determine the output power of the first voltage-controlled oscillator under the input power, until the input power and the output power meet the injection locking condition, and obtain a target control value of the capacitor array of the first voltage-controlled oscillator, and the target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

[0016] The fourth aspect embodiment of the present disclosure proposes an electronic device, comprising: a processor and a memory for storing a computer program that can be run on the processor, wherein, when the processor is used to run the computer program, it executes the method described in any one of the first aspects of the present disclosure, or includes the circuit described in any one of the second aspects.

[0017] The fifth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to enable a computer to execute any one of the methods described in the first aspect of the present disclosure.

[0018] A sixth aspect of the present disclosure provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the method as described in any one of the first aspects of the present disclosure.

[0019] The seventh aspect embodiment of the present disclosure proposes a chip, comprising at least one processor and a communication interface; the communication interface is used to receive signals input into the chip or signals output from the chip, the processor communicates with the communication interface and implements any method described in the first aspect of the present disclosure through logic circuits or execution code instructions, or the chip includes a circuit as described in the second aspect of the present disclosure.

[0020] In summary, the frequency calibration method and frequency calibration circuit proposed in the present disclosure can significantly reduce the time required for voltage-controlled oscillator frequency calibration while maintaining the calibration accuracy, thereby improving the calibration efficiency and frequency switching speed, thereby significantly improving the frequency hopping capability of the entire signal chain system.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute an improper limitation of the present disclosure.

[0023] Figure 1A A schematic diagram of a frequency calibration method in the related art;

[0024] Figure 1B is a schematic diagram of a communication signal link;

[0025] Figure 2 A flow chart of a frequency calibration method proposed in an embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of a power regulation process according to an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of a process for determining a target control value according to an embodiment of the present disclosure;

[0028] Figure 5 This is a diagram of the architecture of the frequency calibration circuit proposed in an embodiment of the present disclosure;

[0029] Figure 6A A diagram of a frequency calibration scheme for a voltage-controlled oscillator based on injection locking;

[0030] Figure 6B This is a diagram of the switched capacitor and injection locked architecture of the voltage controlled oscillator;

[0031] Figure 6C This is the calibration flow chart;

[0032] Figure 7 A schematic structural diagram of a frequency calibration device proposed in an embodiment of the present disclosure;

[0033] Figure 8 is a schematic diagram of an electronic device for implementing the above-mentioned frequency calibration method according to an exemplary embodiment;

[0034] Figure 9 FIG. 4 is a schematic structural diagram of a chip for implementing the above-mentioned frequency calibration method according to an exemplary embodiment. DETAILED DESCRIPTION

[0035] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0036] Frequency calibration methods in related technologies are as follows Figure 1A As shown, the voltage-controlled oscillator (VCO) generates a clock by oscillating itself, which is input to the clock counter (CNT) via the path of arrow 2. Within a certain time interval, the clock counter counts the clocks generated by the VCO, and then inputs the count value into the calibration logic via the direction of arrow 3 in the figure. The calibration logic compares the current count value with the theoretical target count value of the required frequency. Through approximation algorithms such as bisection, it obtains the precise VCO frequency control gear value, which is transmitted to the VCO via arrow 1, thus completing the frequency control. This is the traditional frequency calibration method for VCOs. The traditional frequency calibration method requires counting the frequency of the VCO through a frequency counter, but the VCO jitters more severely in the open-loop state. Therefore, in order to obtain an accurate frequency calibration value, multiple steps are required, which ultimately adds up to a long calibration time.

[0037] like Figure 1BThe communication signal chain shown in the figure is a typical architecture for a communication SOC (System on a Chip), primarily consisting of the RF, baseband, and high-speed interface components. The RF phase-locked loop (PLL), baseband phase-locked loop (PLL), and high-speed interface phase-locked loop (PLL) each provide the local oscillator clock for the mixer to achieve spectrum shifting, provide the sampling clock for the digital-to-analog converter (DAC) and analog-to-digital converter (ADC), and provide the data transfer clock for the high-speed interface. Because the clock plays a crucial role in frequency conversion and rapid mode transitions, it places higher demands on fast calibration and locking. Even using traditional frequency calibration methods to achieve frequency switching cannot meet the short switching time requirements.

[0038] Therefore, this disclosure proposes a frequency calibration method and circuit based on a voltage-controlled oscillator (VCO), which can significantly reduce the time required for VCO frequency calibration while maintaining calibration accuracy. This is to meet the increasingly high requirements for clock switching speed in communication SOC signal chains.

[0039] The method disclosed herein is mainly used in scenarios with high requirements for clock locking speed and frequency switching speed, such as 5G RF transceivers, 5G basebands, high-speed interfaces and other chips or modules. The method disclosed herein can also be applied to 6G or future communication systems.

[0040] The frequency calibration method and frequency calibration circuit proposed in this application will be described in detail below with reference to the accompanying drawings.

[0041] Figure 2 A method flow chart of a frequency calibration method proposed in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the method includes the following steps:

[0042] Step 201 : Determine the input power of the voltage controlled oscillator group based on a preset calibration interval.

[0043] In some embodiments, the preset calibration interval can be the current calibration interval or the range requiring frequency discrimination or the target calibration interval. It can be understood that the current calibration interval is the calibration interval corresponding to the voltage-controlled oscillator group. The preset calibration interval is, for example, 3.2GHz to 14.3GHz or 7 to 9GHz. The preset calibration interval can be customized according to different scenarios, and this disclosure is not limited to this.

[0044] In some embodiments, the voltage controlled oscillator group may include a combination of multiple voltage controlled oscillators, and the voltage controlled oscillator currently being calibrated is determined by controlling a switch of each voltage controlled oscillator in the voltage controlled oscillator group.

[0045] For example, Figure 6A As shown in the schematic diagram, the voltage controlled oscillator group includes N voltage controlled oscillators, and calibration of different voltage controlled oscillators is achieved through switch switching.

[0046] In some embodiments, each voltage-controlled oscillator has a capacitor array, and the capacitor array can obtain different capacitance values by changing gears.

[0047] For example, Figure 6B The architecture diagram of the voltage-controlled oscillator shown in the figure injects a signal through an injection point. A capacitor array is provided in the voltage-controlled oscillator. The capacitor array is divided into 6 coarse adjustment positions, 6 medium adjustment positions, and 6 fine adjustment positions. By changing the positions, the capacitance value of the voltage-controlled oscillator can be controlled.

[0048] In some embodiments, determining the input power of the voltage-controlled oscillator group based on a preset calibration interval may include: configuring an initial frequency, using the initial frequency as the input signal of a fractional phase-locked loop, and determining an output signal; performing frequency multiplication processing on the output signal to obtain a first signal; and performing power regulation processing on a first power of the first signal based on a preset calibration interval to obtain the input power of the voltage-controlled oscillator group.

[0049] In some embodiments, configuring the initial frequency may be setting an initial frequency for the clock source. The initial frequency may be customized according to the scenario or specific application requirements, for example, it may be 76.8 MHz or 72 MHZ, etc., which is not limited in this disclosure.

[0050] For example, the typical frequency of the reference clock source is set to 76.8 MHz to provide a reference clock for a subsequent phase-locked loop circuit.

[0051] In some embodiments, the fractional phase-locked loop can be a fast-locking fractional phase-locked loop (Phase Locked Loop, PLL), which supports fractional mode and has a fractional accuracy that is 4 times or more of the subsequent calibrated phase-locked loop. The oscillator in the fractional phase-locked loop can be a ring oscillator or an LC oscillator. Different oscillators can be set according to specific application requirements, which is not limited in this disclosure.

[0052] For example, Figure 6A As shown in the schematic diagram, a ring oscillator is used in a fast-locking fractional phase-locked loop. The overall phase-locked loop area is very small and has a large locking bandwidth, which can make the locking time within 0.5us.

[0053] In some embodiments, the initial frequency is used as an input signal of a fractional phase-locked loop to determine the output signal. The initial frequency may be provided to the fractional phase-locked loop, and the fractional phase-locked loop is locked to a desired frequency or a target frequency to obtain the output signal. The target frequency may be a frequency value set according to a preset calibration interval.

[0054] For example, Figure 6AIn the schematic diagram shown, the reference clock source generates a reference clock with a typical value of 76.8 MHz, which is provided to the fast-lock fractional PLL. The fast-lock fractional PLL locks to the required frequency within a typical value of 0.5 μs. The frequency of the voltage-controlled oscillator to be calibrated is 7 to 9 GHz. The fast-lock fractional PLL locks to the target frequency of 2 GHz. The clock generated by the fast-lock fractional PLL reaches the frequency multiplier through arrow 1.

[0055] For example, Figure 6C As shown in the flowchart, the initialization configuration is first performed to lock the fast-lock fractional phase-locked loop to the target frequency.

[0056] In some embodiments, frequency doubling the output signal may be performing frequency doubling processing on the frequency of the output signal according to a frequency doubling mode to obtain a first signal, wherein the frequency doubling mode may be 1, 2, or 4 times the frequency, which is not limited in the present disclosure.

[0057] In some embodiments, the frequency multiplication process is used to multiply the frequency of the signal output by the fractional phase-locked loop to a frequency close to the frequency to be calibrated by the subsequent voltage-controlled oscillator.

[0058] For example, Figure 6A In the schematic diagram shown, the frequency multiplier is configured to multiply by 4, and the signal output by the fast locked fractional phase-locked loop is 2 GHz. The output of the frequency multiplier is an 8 GHz clock, which reaches the injection power modulator through arrow 2.

[0059] In some embodiments, based on a preset calibration interval, power regulation processing is performed on the first power of the first signal to obtain the input power of the voltage-controlled oscillator group. The first signal can be power regulated according to the preset calibration interval without processing the frequency to obtain the input power of the input signal of the voltage-controlled oscillator group.

[0060] In some embodiments, the power regulation processing of the first power can be performed by adjusting the first power through a filter. The filter can use an LC filter, a cavity filter, etc. to adjust the first power, or adjust the parameters of the filter to adjust the value of the first power according to a preset calibration interval to obtain the input power.

[0061] For example, Figure 6A As shown in the schematic diagram, the clock output by the frequency multiplier is multiplied to the subsequent injection-locked regulator to adjust the power of the clock input to the subsequent oscillator to be injected, thereby adjusting the frequency range that can be injection-locked.

[0062] In the above embodiment, by configuring the initial frequency, through a fractional phase-locked loop, frequency multiplication processing and power regulation processing, the input power input to the voltage-controlled oscillator group can be adjusted to a power range corresponding to a preset calibration interval, so as to perform frequency calibration on the subsequent voltage-controlled oscillator group.

[0063] In step 202, the capacitor array of the first voltage controlled oscillator in the voltage controlled oscillator group is traversed to determine the output power of the first voltage controlled oscillator under the input power until the input power and the output power meet the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage controlled oscillator.

[0064] In some embodiments, the target control value is used to determine a calibration frequency of the first voltage controlled oscillator.

[0065] In some embodiments, the control value may be a value for controlling the gear position of the capacitor array. Different control values may result in different capacitance values of the voltage-controlled oscillator, and different frequencies may be obtained when the input power is fixed.

[0066] In some embodiments, based on a preset calibration interval, determining the input power of the voltage-controlled oscillator group can be performed by using the input power as the input signal of any voltage-controlled oscillator in the voltage-controlled oscillator group, and traversing the gears of the capacitor array to perform frequency calibration on the voltage-controlled oscillator.

[0067] In some embodiments, the first voltage controlled oscillator may be any voltage controlled oscillator in a voltage controlled oscillator group.

[0068] In some embodiments, traversing the capacitor array of the first voltage controlled oscillator in the voltage controlled oscillator group may be for any voltage controlled oscillator currently undergoing frequency calibration, traversing the gears of its capacitor array to obtain different capacitance values.

[0069] In some embodiments, the capacitor array may be traversed using a binary traversal method or a step-by-step traversal method, which is not limited in the present disclosure.

[0070] In some embodiments, the capacitor array in the voltage controlled oscillator can be configured according to actual needs, for example Figure 6B The capacitor array in the architecture diagram shown can be set by combining coarse adjustment, medium adjustment, and fine adjustment, which is not limited in the present disclosure.

[0071] In some embodiments, the capacitor array of the first voltage-controlled oscillator is traversed to determine the output power under the input power, and the output power corresponding to different capacitance values under the same input power can be obtained.

[0072] In some embodiments, the injection locking condition can be that the input power is close to the output power, or that the difference between the output power and the input power meets a predetermined minimum value. In other words, injection locking occurs when the frequency of the input signal is very close to the frequency of the voltage-controlled oscillator or a harmonic of that frequency, causing the voltage-controlled oscillator to synchronize with the input signal. The predetermined minimum value can be customized based on different scenarios and is not limited in this disclosure.

[0073] In some embodiments, the input power and output power satisfy the injection locking condition by comparing the input power and the output power to determine whether the current control value is the target control value. If the input power and the output power satisfy the injection locking condition, it means that the current control value is the target control value, and the frequency calibration is completed. If the input power and the output power do not satisfy the injection locking condition, it means that the current control value is not the target control value, and it is necessary to continue to traverse the capacitor array downward to obtain the next control value, and compare and judge again until the target control value is obtained, and the frequency calibration of the currently calibrated voltage-controlled oscillator is completed.

[0074] For example, Figure 6A As shown in the schematic diagram, the injection locking detector is used to detect whether the injected oscillator is injection locked. The signal regulated by the injection power regulator is injected into the voltage controlled oscillator through the path of arrow 4 to achieve injection locking. At this time, the capacitor array control gear of the voltage controlled oscillator is traversed by binary division, and the clock of the voltage controlled oscillator is input to the injection locking detector through arrow 6. If the injection locking detector outputs 1 under a certain capacitor array control gear, it means that the current capacitor array control gear is the correct gear required for calibration. At this time, the injection locking detector outputs the detection result to the calibration logic through the path of arrow 3, and this calibration is completed.

[0075] In the above-described embodiment, the frequency of the voltage-controlled oscillator is calibrated by combining power regulation and injection-locked detection. Power regulation determines the input power of the voltage-controlled oscillator group according to a preset calibration interval, and injection-locked detection rapidly detects the input and output powers to quickly lock onto the target control value, achieving calibration. This method significantly reduces the time required for voltage-controlled oscillator frequency calibration while maintaining calibration accuracy, improving calibration efficiency and frequency switching speed, thereby significantly enhancing the frequency hopping capability of the entire signal chain system.

[0076] Figure 3 This is a flow chart of the power regulation process proposed in the embodiment of the present disclosure. Figure 2 The embodiment shown, Figure 3 Step 201 is further defined as follows: Figure 3 As shown, the method includes the following steps:

[0077] Step 301: Initialize and calibrate the theoretical power value to obtain the calibrated power.

[0078] In some embodiments, the initialization correction of the power theoretical value can be performed by adding fine-tuning verification to the power theoretical value so that it can meet the power requirement required for frequency calibration. The power requirement required for frequency calibration can be determined based on a preset calibration interval.

[0079] In some embodiments, the theoretical power value may be a theoretical parameter, which may be set according to specific scenarios or requirements. The initialization correction is to correct the theoretical power value so that it can meet a fixed power requirement.

[0080] For example, Figure 6C The flowchart shown is used to initialize and calibrate the injection-locked power modulator, and verify it through theoretical values and fine-tuning to ensure that it can meet the power requirements required for frequency correction.

[0081] Step 302 : When the correction power satisfies the preset correction power, the first power is subjected to power regulation processing by active filtering and / or passive filtering according to a preset calibration interval to obtain input power.

[0082] In some embodiments, when the correction power meets the preset correction power, power adjustment processing is performed; when the correction power does not meet the preset correction power, initialization correction is performed again until the final correction power meets the preset correction power.

[0083] For example, Figure 6A As shown in the schematic diagram, the injection power regulator calculates the required power level according to the range of the desired frequency discrimination. When the theoretical value of the power regulator cannot meet the current calibration requirements, the digital control logic fine-tunes the power level of the injection power regulator.

[0084] For example, Figure 6C The flowchart shown is used to determine whether the power determination boundary is normal. If it is normal, the subsequent steps are performed. If it is not normal, the process returns to continue power calibration.

[0085] In some embodiments, when the result of the initialization correction meets the preset correction power, the first power is power regulated by active filtering and / or passive filtering according to a preset calibration interval to obtain the input power of the voltage-controlled oscillator group.

[0086] For example, Figure 6A As shown in the schematic diagram, the output of the injection power regulator is injected into the voltage controlled oscillator group to achieve frequency calibration of each voltage controlled oscillator in the voltage controlled oscillator group.

[0087] In some embodiments, the power regulation process may employ active filtering to regulate the first power so that the input power falls within a preset calibration interval. The use of active filtering can achieve better regulation linearity and a smaller module area.

[0088] In some embodiments, the power regulation process may adopt passive filtering to perform power regulation on the first power so that the input power satisfies the range of a preset calibration interval.

[0089] In some embodiments, according to the preset calibration interval, the power adjustment process for the first power can be to calculate the required power level according to the range of the desired frequency discrimination to achieve the adjustment of the first power.

[0090] For example, Figure 6C As shown in the flowchart, when the power determination boundary is normal, the frequency calibration state machine is started to perform frequency correction on the voltage controlled oscillator.

[0091] In some embodiments, during the frequency calibration of the voltage-controlled oscillator, if the result obtained is abnormal, the above steps need to be performed again to initialize and correct the theoretical power value to obtain the corrected power. When the corrected power meets the preset corrected power, the first power is power regulated in the above manner to obtain the input power.

[0092] For example, Figure 6C As shown in the flowchart, the frequency calibration state machine is started. After the frequency of the voltage-controlled oscillator is calibrated, if an abnormal state is found in the result during the calibration process, the process returns to continue initializing and calibrating the injection power regulator. If the calibration is normal, the entire calibration process is completed and the relevant calibration circuit is turned off to save power consumption.

[0093] In the above embodiment, the theoretical power value is initialized and corrected to meet the requirement of power regulation processing on the first power, so that the obtained input power can meet the power required in the preset calibration interval.

[0094] Figure 4 This is a flow chart of determining the target control value proposed in the embodiment of the present disclosure. Figure 2-Figure 3 The embodiment shown, Figure 4 right Figure 2 Step 202 in the further definition is as follows: Figure 4 As shown, the following steps are also included.

[0095] Step 401: Determine a first voltage controlled oscillator based on a first control signal.

[0096] In some embodiments, the first control signal is used to control the switch of the voltage controlled oscillator in the voltage controlled oscillator group.

[0097] In some embodiments, the first control signal may be inputted by a related logic module to the voltage controlled oscillator group to determine the first voltage controlled oscillator currently undergoing frequency calibration, and the purpose of switching the voltage controlled oscillator is achieved by changing the control word in the first control signal.

[0098] For example, Figure 6A As shown in the schematic diagram, the digital calibration logic module is used to control all modules to perform frequency calibration. During each calibration, the digital calibration logic module inputs the control word to the voltage-controlled oscillator group through the path of arrow 7 to replace the switch of the voltage-controlled oscillator and determine the voltage-controlled oscillator currently being calibrated.

[0099] Step 402 : Determine a first control value of a capacitor array of a first voltage controlled oscillator based on a second control signal.

[0100] In some embodiments, the second control signal is used to determine an ergodic level of the capacitor array of the first voltage-controlled oscillator.

[0101] In some embodiments, the second control signal includes a control value, and the control value is used to determine the gear position of the capacitor array.

[0102] In some embodiments, the control value may be a control value obtained by performing a binary traversal on the capacitor array, or a control value obtained by performing a successive progressive traversal, which is not limited in the present disclosure.

[0103] For example, Figure 6A As shown in the schematic diagram, the digital calibration logic module inputs the control word and control value to the voltage controlled oscillator group through the path of arrow 7 to change the frequency of the currently calibrated voltage controlled oscillator, for example Figure 6B The capacitor array shown in traverses the gears through the binary search method to find the most suitable control value of the capacitor array.

[0104] Step 403: Determine a first output power of the first voltage controlled oscillator according to the first control value and the input power.

[0105] In some embodiments, the first control value is the current gear position of the capacitor array of the first voltage-controlled oscillator, and the current capacitance value of the first voltage-controlled oscillator can be obtained. The input power is the power of the input signal of the first voltage-controlled oscillator. The first output power of the first voltage-controlled oscillator can be obtained through the current capacitance value and the input power.

[0106] In some embodiments, by performing injection locking detection between the input power and the first output power, it is determined whether the injection locking condition is met to determine whether the current capacitance value is the target capacitance value of the first voltage-controlled oscillator at the calibration frequency, that is, to determine whether the current gear is the target gear, and then determine whether the first control value is the target control value.

[0107] In some embodiments, if the first control value is not the target control value, the capacitor array is traversed backward until the control value of the capacitor array reaches the target control value, thus completing the current frequency calibration of the first voltage-controlled oscillator.

[0108] For example, Figure 6A As shown in the schematic diagram, during a single calibration process, the injection power regulator injects the signal with adjusted injection power into the voltage-controlled oscillator through the path of arrow 4 to achieve injection locking. At this time, the capacitor array control gear of the voltage-controlled oscillator is binary traversed, and the clock of the voltage-controlled oscillator is input into the injection lock detector through arrow 6. If the injection lock detector outputs 1 under a certain capacitor array control gear, it means that the current capacitor array control gear is the correct gear required for calibration. At this time, the injection lock detector outputs the detection result to the calibration logic through the path of arrow 3, and this calibration is completed.

[0109] In some embodiments, when the first output power and the input power of the first voltage controlled oscillator satisfy an injection locking condition, the output frequency of the first voltage controlled oscillator at the first control value is determined as the calibration frequency of the first voltage controlled oscillator.

[0110] In some embodiments, when the first control value is the target control value, i.e., the output frequency of the first voltage-controlled oscillator under the first control value is the calibration frequency, the control word output by the first control signal is controlled to change the switch in the voltage-controlled oscillator group, switching to the second voltage-controlled oscillator, and performing frequency calibration on the second voltage-controlled oscillator. The method for frequency calibration of the second voltage-controlled oscillator is the same as the method for frequency calibration of the first voltage-controlled oscillator described above, and will not be repeated here.

[0111] In some embodiments, when the first output power and input power of the first voltage-controlled oscillator do not meet the injection locking condition, a second control value of the capacitor array of the first voltage-controlled oscillator is determined based on the second control signal; and the second output power of the first voltage-controlled oscillator is determined according to the second control value and the input power until the second output power and the input power meet the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage-controlled oscillator.

[0112] In some embodiments, if the output power of the first voltage-controlled oscillator at the first control value does not meet the injection locking condition, it means that the gear of the capacitor array at the first control value does not meet the calibration frequency, and the gear of the capacitor array needs to be further traversed downward.

[0113] For example, the control gear of the capacitor array of the voltage-controlled oscillator is traversed by binary division. During each calibration, the digital calibration logic module inputs the control value of the capacitor array to the corresponding voltage-controlled oscillator through the path of arrow 7 to achieve the change of the voltage-controlled oscillator frequency.

[0114] In the above embodiment, after all the voltage controlled oscillators in the voltage controlled oscillator group obtain corresponding target control values, the circuit corresponding to the frequency calibration method may be turned off to save power consumption.

[0115] In the above embodiment, the input power of the voltage-controlled oscillator group is power-regulated based on a preset calibration interval, and the capacitor array of the voltage-controlled oscillator is traversed to perform injection locking detection on the input power and the output power. When the injection locking condition is met, the target control value of the capacitor array of the voltage-controlled oscillator can be quickly locked to achieve the purpose of frequency calibration of the voltage-controlled oscillator. While ensuring that the calibration accuracy remains unchanged, the calibration efficiency and frequency switching speed can be improved, thereby greatly improving the frequency hopping capability of the entire signal chain system.

[0116] Figure 5 This is a diagram of the architecture of the frequency calibration circuit proposed in the embodiment of the present disclosure. Figure 5 As shown, the circuit includes: a power regulation module, a detection module, and a calibration module.

[0117] The power regulation module is used to determine the input power of the voltage-controlled oscillator group in the calibration module based on a preset calibration interval; the calibration module is connected to the power regulation module and the detection module respectively, and is used to traverse the capacitor array of the first voltage-controlled oscillator in the voltage-controlled oscillator group to determine the output power of the first voltage-controlled oscillator under the input power; the detection module is used to perform injection locking detection on the input power and output power, and when the input power and output power meet the injection locking conditions, obtain the target control value of the capacitor array of the first voltage-controlled oscillator, and the target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

[0118] In some embodiments, the preset calibration interval may be a current calibration interval or a range requiring frequency discrimination or a target calibration interval.

[0119] In some embodiments, the voltage-controlled oscillator group comprises a plurality of voltage-controlled oscillators. The voltage-controlled oscillator currently being calibrated is determined by controlling the switches of each voltage-controlled oscillator in the group. Each voltage-controlled oscillator has a capacitor array, and the capacitor array can be switched to obtain different capacitance values by traversing the capacitor array.

[0120] In some embodiments, the capacitor array may be traversed in a binary traversal or a step-by-step traversal, which is not limited in the present disclosure.

[0121] In some embodiments, the frequency calibration circuit also includes a clock module, a phase-locked loop module, and a frequency multiplication module: the clock module is used to configure the initial frequency, and the clock module is connected to the phase-locked loop module; the phase-locked loop module is used to use the initial power as the input signal to determine the output signal; the frequency multiplication module is respectively connected to the phase-locked loop module and the detection module, and is used to perform frequency multiplication processing on the output signal output by the phase-locked loop module to obtain a first signal, and send the first signal to the detection module.

[0122] In some embodiments, the initial frequency may be a starting frequency set for the clock module, such as 76.8 MHz or 72 MHz, and may be customized according to the scenario or specific application requirements, which is not limited by the present disclosure.

[0123] In some embodiments, the frequency multiplication module may perform frequency multiplication processing using different modes, such as 1x frequency multiplication, 2x frequency multiplication, or 4x frequency multiplication mode.

[0124] In some embodiments, the phase-locked loop module can be a fast-locking fractional phase-locked loop (PLL), which supports fractional mode and has a fractional accuracy that is 4 times or more of the subsequent calibrated phase-locked loop. The oscillator in the fractional phase-locked loop can be a ring oscillator or an LC oscillator. Different oscillators can be set according to specific application requirements, which is not limited in this disclosure.

[0125] In some embodiments, the frequency calibration circuit also includes a digital calibration logic module, which is connected to the detection module and the calibration module, and is used to receive the injection locking detection result output by the detection module, and determine the first control signal and the second control signal based on the injection locking detection result, the first control signal is used to control the switch of the voltage-controlled oscillator in the voltage-controlled oscillator group, and the second control signal is used to determine the traversal gear of the capacitor array of the first voltage-controlled oscillator; the power regulation module is also used to initialize and correct the theoretical power value to obtain the corrected power; when the corrected power meets the preset corrected power, the first power of the first signal is power regulated according to the preset calibration interval through active filtering and / or passive filtering to obtain the input power.

[0126] In some embodiments, the first control signal and the second control signal are input to the calibration module by the digital calibration logic module, the first control signal is used to determine the voltage-controlled oscillator currently undergoing frequency calibration, and the second control signal is used to determine the current gear position of the capacitor array of the voltage-controlled oscillator currently undergoing frequency calibration.

[0127] In some embodiments, the digital calibration logic module can change the information carried in the first control signal and / or the second control signal based on the injection locking detection result input by the detection module to achieve switching of the voltage-controlled oscillator and / or traversal of the gears of the capacitor array.

[0128] In some embodiments, the detection module can perform injection locking detection on the input power and output power. Injection locking detection can determine whether the input power and output power meet the injection locking condition. The injection locking condition can be that the input power and output power are close, or the difference between the output power and the input power meets a preset minimum value. In other words, the injection locking condition occurs when the frequency of the input signal is very close to the frequency of the voltage-controlled oscillator or a harmonic of this frequency, causing the voltage-controlled oscillator to synchronize with the input signal. The preset minimum value can be customized according to different scenarios and is not limited by this disclosure.

[0129] In some embodiments, when the detection module determines that the input power and output power meet the injection locking conditions, the injection locking detection result is sent to the digital calibration logic module, and the calibration process of the current voltage-controlled oscillator is completed. After the digital calibration logic module determines that all voltage-controlled oscillators have completed the frequency calibration process, the frequency calibration circuit can be turned off to save power consumption.

[0130] In the above embodiment, the frequency calibration circuit can achieve the above Figures 2 to 4 Frequency calibration method shown.

[0131] In the above embodiment, the frequency calibration circuit realizes frequency calibration of the voltage-controlled oscillator by combining the power regulation module and the detection module, thereby improving the calibration efficiency and frequency switching speed while ensuring the calibration accuracy, thereby greatly improving the frequency hopping capability of the entire signal chain system.

[0132] The following is a specific implementation of the frequency calibration scheme of the voltage controlled oscillator:

[0133] like Figure 6A The injection-locked voltage-controlled oscillator frequency calibration scheme shown in the figure includes the following components:

[0134] 1. Reference clock source, with a typical frequency of 76.8 MHz. This clock source provides the reference clock for the subsequent phase-locked loop.

[0135] 2. Fast-locking fractional phase-locked loop. This phase-locked loop has a typical locking frequency range of 1.5 to 3.6 GHz and supports fractional mode. The fractional accuracy is four times or more that of the subsequent calibrated phase-locked loop. The oscillator in this phase-locked loop uses a ring oscillator, resulting in a very small overall phase-locked loop area. It also features a wide locking bandwidth, ensuring a lock time of less than 0.5 μs.

[0136] 3. Frequency multiplier, supports three frequency multiplication modes: 1, 2, and 4. It is used to multiply the clock output by the fast-locked fractional phase-locked loop to a frequency close to the frequency to be calibrated by the subsequent phase-locked loop.

[0137] 4. Injection power regulator. This is primarily used to adjust the power of the clock input to the subsequent oscillator, thereby adjusting the frequency range that can be injection-locked. Using an active filter here can achieve better regulation linearity and a smaller module area.

[0138] 5. Injection Lock Detector: This is used to detect whether the injected oscillator is injection locked.

[0139] 6. Digital calibration logic: Used to control all modules to perform frequency calibration.

[0140] 7. Voltage Controlled Oscillator Group. The module to be calibrated has many different voltage controlled oscillators in the chip, and calibration of different voltage controlled oscillators is achieved through switch switching.

[0141] The single calibration process is as follows: First, a reference clock source generates a reference clock with a typical value of 76.8 MHz and provides it to the fast-locking fractional phase-locked loop (FPL). The FPL locks to the desired frequency, for example, 2 GHz, within a typical 0.5 μs. The voltage-controlled oscillator (VCO) to be calibrated has a frequency of 7 to 9 GHz. The clock generated by the FPL then passes through arrow 1 to the frequency multiplier. The frequency multiplier is configured for quadruple multiplication, resulting in an 8 GHz clock output from the frequency multiplier. This clock passes through arrow 2 to the injection power modulator, which adjusts the injection power based on the current calibration interval. The adjusted injection power signal is injected into the VCO via arrow 4 to achieve injection locking. A binary search is then performed on the VCO's capacitor array control settings. The VCO's clock is then fed into the injection lock detector via arrow 6. If the injection lock detector outputs a 1 at any capacitor array control setting, it indicates that the current capacitor array control setting is the correct one for calibration. The injection lock detector then outputs the detection result to the calibration logic via arrow 3. This completes the calibration. During each calibration, the digital calibration logic module inputs the control word of the voltage controlled oscillator to the voltage controlled oscillator group through the path of arrow 7, and inputs the control value of the capacitor array to the corresponding voltage controlled oscillator to achieve the change of the voltage controlled oscillator frequency.

[0142] Figure 6B This diagram shows the switched capacitor and injection-locked architecture of a voltage-controlled oscillator. Signals are injected through the injection points, and the frequency range of the voltage-controlled oscillator is controlled by the capacitor array control value. The capacitor array control has 6 coarse adjustment levels, 6 mid-range adjustment levels, and 6 fine adjustment levels. Using a traditional binary search method to iterate through the levels, the appropriate capacitor array control value is ultimately found.

[0143] Here, the power regulator will calculate the required power level according to the frequency range to be detected. When the theoretical value of the power regulator cannot meet the current calibration requirements, the digital control logic will fine-tune the power level of the power regulator. Figure 6C As shown, the following steps are included:

[0144] 1. First, perform initialization configuration.

[0145] 2. Lock the fast-lock phase-locked loop to the target frequency.

[0146] 3. Initialize and calibrate the injection-locked power regulator, verify it through theoretical values and fine-tuning, so that it can meet the power requirements required for frequency correction.

[0147] 4. Determine whether the power determination boundary is normal. If it is normal, proceed to the subsequent steps. If it is not normal, return to continue power calibration.

[0148] 5. Start the frequency calibration state machine, using the traditional binary method to calibrate the frequency. If the calibration results are abnormal, the system returns to the initialization state of the injection-locked power regulator. If the calibration is normal, the entire calibration process is completed and the relevant calibration circuits are turned off to save power.

[0149] In summary, the above calibration method shortens the time required for calibration and increases the frequency switching speed, thereby significantly improving the frequency hopping capability of the entire signal chain system.

[0150] Figure 7 FIG. 7 is a structural diagram of a frequency calibration device 700 according to an embodiment of the present disclosure. Figure 7 As shown, the device includes:

[0151] The determination module 710 is configured to determine the input power of the voltage controlled oscillator group based on a preset calibration region.

[0152] The calibration module 720 is used to traverse the capacitor array of the first voltage-controlled oscillator in the voltage-controlled oscillator group, determine the output power of the first voltage-controlled oscillator under the input power, until the input power and the output power meet the injection locking condition, and obtain a target control value of the capacitor array of the first voltage-controlled oscillator. The target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

[0153] In some embodiments, the determination module is also used to: configure the initial frequency, use the initial frequency as the input signal of the fractional phase-locked loop, and determine the output signal; perform frequency multiplication processing on the output signal to obtain a first signal; and perform power regulation processing on the first power of the first signal based on a preset calibration interval to obtain the input power of the voltage-controlled oscillator group.

[0154] In some embodiments, the determination module is also used to: initialize and correct the theoretical power value to obtain the corrected power; when the corrected power meets the preset corrected power, perform power regulation processing on the first power according to the preset calibration interval through active filtering and / or passive filtering to obtain the input power.

[0155] In some embodiments, the calibration module is further used to: determine a first voltage-controlled oscillator based on a first control signal, the first control signal being used to control the switch of the voltage-controlled oscillator in the voltage-controlled oscillator group; determine a first control value of the capacitor array of the first voltage-controlled oscillator based on a second control signal, the second control signal being used to determine the traversal gear of the capacitor array of the first voltage-controlled oscillator; and determine a first output power of the first voltage-controlled oscillator according to the first control value and the input power.

[0156] In some embodiments, the calibration module is further used to: determine a second control value of the capacitor array of the first voltage-controlled oscillator based on a second control signal when the first output power and input power of the first voltage-controlled oscillator do not meet the injection locking condition; determine the second output power of the first voltage-controlled oscillator based on the second control value and the input power until the second output power and the input power meet the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage-controlled oscillator.

[0157] In some embodiments, the calibration module is further configured to: determine the output frequency of the first voltage controlled oscillator at the first control value as the calibration frequency of the first voltage controlled oscillator when the first output power and the input power of the first voltage controlled oscillator satisfy an injection locking condition.

[0158] In summary, the frequency calibration device proposed in the present disclosure realizes frequency calibration of the voltage-controlled oscillator by combining power regulation and injection locked detection. While ensuring the calibration accuracy, it improves the calibration efficiency and frequency switching speed, thereby greatly improving the frequency hopping capability of the entire signal chain system.

[0159] Regarding the frequency calibration device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0160] Figure 8FIG. 8 is a structural diagram of an electronic device 800 for implementing the above-mentioned frequency calibration method according to an exemplary embodiment.

[0161] Reference Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , an input / output (I / O) interface 808 , a sensor component 810 , and a communication component 812 .

[0162] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, battery management, and logging operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a balancing module to facilitate interaction between the power supply component 806 and the processing component 802.

[0163] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0164] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0165] I / O interface 808 provides an interface between processing component 802 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0166] The sensor assembly 810 includes one or more sensors for providing various aspects of the status assessment of the electronic device 800. For example, the sensor assembly 810 can detect the open / closed state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 810 can also detect changes in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and changes in the temperature of the electronic device 800. The sensor assembly 810 can include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 810 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications.

[0167] In some embodiments, the sensor assembly 810 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0168] The communication component 812 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio) or a combination thereof. In an exemplary embodiment, the communication component 812 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 812 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0169] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0170] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by the processor 820 of the electronic device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0171] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon. When the program instructions are executed by a processor, the steps of the frequency calibration method provided by the present disclosure are implemented.

[0172] An embodiment of the present disclosure further provides a computer program product, including a computer program, which is used by a processor to execute the frequency calibration method described in the above embodiment of the present disclosure.

[0173] Figure 9 FIG. 1 is a schematic structural diagram of a chip 900 for implementing the above-mentioned frequency calibration method according to an exemplary embodiment. Figure 9 The chip 900 includes at least one communication interface 901 and a processor 902. The communication interface 901 is used to receive signals input into the chip 900 or signals output from the above chip 900. The processor 902 communicates with the communication interface 901 and implements the frequency calibration method described in the above embodiments of the present disclosure through logic circuits or executing code instructions.

[0174] Furthermore, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as advantageous over other aspects or designs. Rather, the use of the word exemplary is intended to present concepts in a concrete manner. As used herein, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X applies to A or B" is intended to mean any of the natural inclusive permutations. That is, if X applies to A; X applies to B; or X applies to both A and B, then "X applies to A or B" satisfies any of the aforementioned instances. Furthermore, the articles "a" and "an," as used in this application and the appended claims, are generally understood to mean "one or more," unless otherwise specified or clear from the context to refer to the singular form.

[0175] Likewise, although the present disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art after reading and understanding the specification and drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component (functionally equivalent) that performs the specific functions of the described components, even if structurally not equivalent to the disclosed structures. In addition, although specific features of the present disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations as may be desired and beneficial for any given or specific application. In addition, with respect to the terms "including," "having," "having," "having," or variations thereof used in the specific embodiments or claims, such terms are intended to be inclusive in a manner similar to the term "comprising."

[0176] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0177] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0178] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the numbers used in this manner are interchangeable where appropriate so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure as detailed in the appended claims.

[0179] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the illustrative use of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0180] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0181] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection having one or more wires (control method), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing it in a suitable manner if necessary, and then storing it in a computer memory.

[0182] It should be understood that the various parts of the embodiments of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0183] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0184] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disk, etc.

[0185] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and are not to be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A frequency calibration method, characterized in that: The method comprises: determining an input power of the voltage controlled oscillator group based on a preset calibration interval; The capacitor array of the first voltage-controlled oscillator in the voltage-controlled oscillator group is traversed to determine the output power of the first voltage-controlled oscillator under the input power until the input power and the output power meet the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage-controlled oscillator, and the target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

2. The method according to claim 1, characterized in that The step of determining the input power of the voltage controlled oscillator group based on the preset calibration interval includes: configuring an initial frequency, using the initial frequency as an input signal of a fractional phase-locked loop, and determining an output signal; Performing frequency multiplication processing on the output signal to obtain a first signal; Based on the preset calibration interval, power adjustment processing is performed on the first power of the first signal to obtain the input power of the voltage-controlled oscillator group.

3. The method according to claim 2, characterized in that The performing power adjustment processing on the first power of the first signal based on the preset calibration interval includes: Initialize and correct the theoretical power value to obtain the corrected power; When the correction power satisfies the preset correction power, the power adjustment process is performed on the first power according to the preset calibration interval through active filtering and / or passive filtering to obtain the input power.

4. The method according to claim 2, characterized in that The traversing the capacitor array of the first voltage controlled oscillator in the voltage controlled oscillator group to determine the output power of the first voltage controlled oscillator under the input power includes: determining the first voltage controlled oscillator based on a first control signal, wherein the first control signal is used to control switches of the voltage controlled oscillators in the voltage controlled oscillator group; determining a first control value of the capacitor array of the first voltage-controlled oscillator based on a second control signal, wherein the second control signal is used to determine an ergodic gear position of the capacitor array of the first voltage-controlled oscillator; A first output power of the first voltage-controlled oscillator is determined according to the first control value and the input power.

5. The method according to claim 4, characterized in that The method further comprises: determining, based on the second control signal, a second control value of the capacitor array of the first voltage-controlled oscillator when the first output power and the input power of the first voltage-controlled oscillator do not satisfy the injection locking condition; The second output power of the first voltage controlled oscillator is determined according to the second control value and the input power until the second output power and the input power meet the injection locking condition, thereby obtaining a target control value of the capacitor array of the first voltage controlled oscillator.

6. The method according to claim 4, characterized in that The method further comprises: When the first output power and the input power of the first voltage controlled oscillator satisfy the injection locking condition, the output frequency of the first voltage controlled oscillator under the first control value is determined as the calibration frequency of the first voltage controlled oscillator.

7. A frequency calibration circuit, characterized in that: Including power regulation module, detection module, calibration module, The power regulation module is used to determine the input power of the voltage controlled oscillator group in the calibration module based on a preset calibration interval; The calibration module is connected to the power regulation module and the detection module respectively, and is used to traverse the capacitor array of the first voltage controlled oscillator in the voltage controlled oscillator group to determine the output power of the first voltage controlled oscillator under the input power; The detection module is used to perform injection locking detection on the input power and the output power, and obtain a target control value of the capacitor array of the first voltage-controlled oscillator when the input power and the output power meet the injection locking condition. The target control value is used to determine the calibration frequency of the first voltage-controlled oscillator.

8. The circuit according to claim 7, characterized in that The frequency calibration circuit also includes a clock module, a phase-locked loop module, and a frequency multiplication module: The clock module is used to configure the initial frequency, and the clock module is connected to the phase-locked loop module; The phase-locked loop module is used to take the initial power as an input signal and determine an output signal; The frequency multiplication module is connected to the phase-locked loop module and the detection module respectively, and is used to perform frequency multiplication processing on the output signal output by the phase-locked loop module to obtain a first signal, and send the first signal to the detection module.

9. The circuit according to claim 8, characterized in that The frequency calibration circuit further includes a digital calibration logic module, the digital calibration logic module being connected to the detection module and the calibration module, and configured to receive an injection locking detection result output by the detection module, and determine a first control signal and a second control signal based on the injection locking detection result, wherein the first control signal is configured to control a switch of a voltage controlled oscillator in the voltage controlled oscillator group, and the second control signal is configured to determine an ergodic gear position of a capacitor array of the first voltage controlled oscillator; The power regulation module is also used to initialize and correct the theoretical power value to obtain the corrected power; when the corrected power meets the preset correction power, the power regulation processing is performed on the first power of the first signal according to the preset calibration interval through active filtering and / or passive filtering to obtain the input power.

10. A frequency calibration device, comprising: a determination module, configured to determine an input power of the voltage controlled oscillator group based on a preset calibration interval; A calibration module is configured to traverse the capacitor array of the first voltage-controlled oscillator in the voltage-controlled oscillator group, determine the output power of the first voltage-controlled oscillator under the input power, until the input power and the output power meet the injection locking condition, and obtain a target control value of the capacitor array of the first voltage-controlled oscillator, wherein the target control value is used to determine a calibration frequency of the first voltage-controlled oscillator.

11. An electronic device, characterized in that: include: A processor and a memory for storing a computer program that can be run on the processor, wherein when the processor is used to run the computer program, it executes the method according to any one of claims 1 to 6, or includes the circuit according to any one of claims 7 to 9.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 6.

13. A chip, characterized in that: The chip comprises at least one processor and a communication interface; the communication interface is used to receive a signal input to the chip or a signal output from the chip, the processor communicates with the communication interface and implements the method according to any one of claims 1 to 6 through a logic circuit or by executing code instructions, or the chip comprises a circuit according to any one of claims 7 to 9.

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