OPC (Optical Proximity Correction) method for regulating and controlling resistance of high-resistance sheet

Abstract

The invention provides an OPC (Optical Proximity Correction) method for regulating and controlling the resistance of a high-resistance sheet, which comprises the following steps of: 1, delimiting a layout area where a high-resistance layer and a silicide barrier layer are located in an original layout, and determining the resistance value of the high-resistance sheet according to the layout area; and 2, according to the resistance value of the sheet resistor of the high-resistance layer determined in the step 1, reducing the width of the overlapped part of the high-resistance layer and the silicide barrier layer. The resistance value of the high-resistance layer sheet resistor is regulated and controlled by changing the shape of the high-resistance layer in the layout, the position of a contact hole does not need to be adjusted, and more flexible layout design elasticity under different manufacturing processes is provided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an OPC correction method for regulating the resistance of a high-resistance layer. Background Art

[0002] For different semiconductor device manufacturing processes, the resistance value of the high resistance layer (HiR) sheet resistance is defined in different ways. Figure 1 As shown, the device structure in the left layout is fabricated using process one, where the resistance of the high-resistance sheet resistor is determined by the length of the silicide barrier layer (SAB). The device structure in the right layout is fabricated using process two, where the resistance of the high-resistance sheet resistor is determined by the spacing between the contact holes on either side of the SAB. If process two is used to fabricate the device structure in the left layout, to maintain the resistance of the high-resistance sheet resistor, the contact holes in the layout need to be moved to the sides of the SAB, thereby ensuring that the spacing between the contact holes on either side of the SAB is equal to the length of the SAB. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide an OPC correction method for regulating the resistance of the high-resistance layer, which is used to solve the problem in the prior art that changing the manufacturing process without changing the resistance value of the high-resistance layer requires changing the position of the contact hole in the layout.

[0004] To achieve the above-mentioned and other related purposes, the present application provides an OPC correction method for regulating the sheet resistance of a high-resistance layer, comprising:

[0005] Step 1: Delineating the layout area where the high-resistance layer and the silicide barrier layer are located in the original layout, and determining the resistance value of the high-resistance layer sheet resistor based on the layout area;

[0006] Step 2: According to the resistance value of the high-resistance layer sheet resistor determined in step 1, the width of the portion of the high-resistance layer overlapping the silicide barrier layer is reduced.

[0007] Preferably, the resistance of the high-resistance layer resistor is determined by the following formula: Wherein, Rs is the resistance value of the high resistance layer sheet resistor, ρ is the resistivity of the high resistance layer material, L is the length of the silicide barrier layer, W is the width of the high resistance layer, and Thick is the thickness of the high resistance layer.

[0008] Preferably, the width of the portion of the high-resistance layer overlapping with the silicide barrier layer is determined by the following formula: W1=L1 / (Rs×Thick / ρ-2L2 / W), wherein W1 is the width of the portion of the high-resistance layer overlapping with the silicide barrier layer, L1 is the length of the portion of the high-resistance layer overlapping with the silicide barrier layer (equal to the length of the silicide barrier layer), L2 is the spacing between the contact hole and the silicide barrier layer, W is the width of the high-resistance layer, Rs is the resistance value of the high-resistance layer sheet resistor, ρ is the resistivity of the high-resistance layer material, and Thick is the thickness of the high-resistance layer.

[0009] Preferably, the original layout and the layout obtained after implementing step 2 are respectively applied to different semiconductor manufacturing processes.

[0010] Preferably, the material of the high resistance layer is titanium nitride.

[0011] As described above, the OPC correction method for regulating the sheet resistance of the high-resistance layer provided in this application has the following beneficial effects: the resistance value of the high-resistance layer sheet resistance is regulated by changing the shape of the high-resistance layer in the layout without adjusting the position of the contact hole, providing more flexible layout design flexibility under different manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 Schematic diagram showing the limiting rules for the resistance value of the high-resistance layer in the layout under different manufacturing processes;

[0014] Figure 2 A flow chart showing an OPC correction method for regulating the sheet resistance of a high-resistance layer provided in an embodiment of the present application;

[0015] Figure 3 Shown is a schematic diagram of the shape of the high-resistance layer in the layout according to the OPC correction method for regulating the sheet resistance of the high-resistance layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The following describes the embodiments of the present application through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present application from the disclosure herein. The present application may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0017] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or location relationships, are used solely to facilitate the description of this application and simplify the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] See also Figure 2 , which shows a flow chart of an OPC correction method for regulating the resistance of a high-resistance layer provided in an embodiment of the present application.

[0022] like Figure 2 As shown, the OPC correction method for regulating the sheet resistance of the high-resistance layer includes the following steps:

[0023] Step 1: Delineating the layout area where the high-resistance layer and the silicide barrier layer are located in the original layout, and determining the resistance value of the high-resistance layer sheet resistor based on the layout area;

[0024] Step 2: According to the resistance value of the high-resistance layer sheet resistor determined in step 1, the width of the portion of the high-resistance layer overlapping the silicide barrier layer is reduced.

[0025] In step one, if Figure 1 As shown in the middle left figure, the resistance value of the high-resistance layer resistor is determined by the following formula:

[0026]

[0027] Wherein, Rs is the resistance value of the high resistance layer sheet resistor, ρ is the resistivity of the high resistance layer material, L is the length of the silicide barrier layer, W is the width of the high resistance layer, and Thick is the thickness of the high resistance layer.

[0028] In step 2, if Figure 3 As shown, after the overlapping portion of the high resistance layer and the silicide barrier layer is reduced, the width of the overlapping portion of the high resistance layer and the silicide barrier layer is determined by the following formula:

[0029]

[0030] Wherein, W1 is the width of the high resistance layer overlapping with the silicide barrier layer, L1 is the length of the high resistance layer overlapping with the silicide barrier layer (equal to the length of the silicide barrier layer), L2 is the distance between the contact hole and the silicide barrier layer, W is the width of the high resistance layer, Rs is the resistance value of the high resistance layer sheet resistor, ρ is the resistivity of the high resistance layer material, and Thick is the thickness of the high resistance layer.

[0031] Exemplarily, the material of the high resistance layer is titanium nitride (TiN).

[0032] By reducing the overlapping portion of the high-resistance layer with the silicide barrier layer, the high-resistance layer can be prepared using process 2 without changing the position of the contact hole.

[0033] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present application. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0034] In summary, the OPC correction method for controlling the sheet resistance of a high-resistance layer provided by this application modulates the sheet resistance of the high-resistance layer by changing the shape of the high-resistance layer in the layout (this resistance varies with the width of the overlap between the high-resistance layer and the silicide barrier layer). This eliminates the need to adjust the position of contact holes, providing greater flexibility in layout design under different manufacturing processes. Therefore, this application effectively overcomes the shortcomings of the existing technology and has high industrial application value.

[0035] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed herein shall be covered by the claims of this application.

Claims

1. An OPC correction method for regulating the sheet resistance of a high-resistance layer, characterized in that: The method comprises: Step 1: Delineating the layout area where the high-resistance layer and the silicide barrier layer are located in the original layout, and determining the resistance value of the high-resistance layer sheet resistor according to the layout area; Step 2: reducing the width of the portion of the high-resistance layer that overlaps the silicide barrier layer according to the resistance value of the high-resistance layer sheet determined in step 1.

2. The method according to claim 1, characterized in that The resistance value of the high-resistance layer resistor is determined by the following formula: Wherein, Rs is the resistance value of the high resistance layer sheet resistor, ρ is the resistivity of the high resistance layer material, L is the length of the silicide barrier layer, W is the width of the high resistance layer, and Thick is the thickness of the high resistance layer.

3. The method according to claim 1, characterized in that The width of the portion of the high-resistance layer overlapping with the silicide barrier layer is determined by the following formula: W1=L1 / (Rs×Thick / ρ-2L2 / W), wherein W1 is the width of the portion of the high-resistance layer overlapping with the silicide barrier layer, L1 is the length of the portion of the high-resistance layer overlapping with the silicide barrier layer (equal to the length of the silicide barrier layer), L2 is the spacing between the contact hole and the silicide barrier layer, W is the width of the high-resistance layer, Rs is the resistance value of the high-resistance layer sheet resistor, ρ is the resistivity of the high-resistance layer material, and Thick is the thickness of the high-resistance layer.

4. The method according to claim 1, wherein The original layout and the layout obtained after implementing step 2 are respectively applied to different semiconductor manufacturing processes.

5. The method according to claim 1, characterized in that The material of the high resistance layer is titanium nitride.

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