Loop branch prediction instruction fetching device, processor and electronic equipment

Abstract

The present invention proposes a loop branch prediction instruction fetching device, processor, and electronic device. A reference unit generates a reference address based on acquired address data; an instruction storage unit reads a historical reference address for prefetching. When an instruction storage unit hits, the target instruction corresponding to the historical reference address is transmitted to a first branch predictor after K clock cycles. The first branch predictor is configured to read the historical reference address, perform address prediction based on the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit. A second branch predictor is configured to read the historical reference address and, if the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, provide the stored loop start address to the reference unit. Reducing the number of instructions required to maintain loop variables and judgment conditions can reduce code complexity and maintenance difficulty, improve instruction fetching efficiency, and fully realize the performance potential of the processor.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to a loop branch prediction instruction fetching device, a processor and an electronic device. Background Art

[0002] With the continuous expansion of processor applications, especially in digital signal processing, image processing, neural networks, and other fields, loop structures are being used more and more frequently in programs. In the traditional RISC-V architecture, loop implementation mainly relies on conditional branch instructions (such as BEQ, BNE, BLT, etc.) and unconditional jump instructions (such as JAL and JALR).

[0003] When the number of loops is high, the hardware structure needs to be frequently accessed and updated, which not only increases power consumption but can also cause pipeline refreshes due to prediction failures, impacting processor performance. Even the most basic loop requires at least two instructions, and complex loops may require even more instructions to maintain loop variables and judgment conditions, increasing pressure on the instruction cache and reducing instruction fetch efficiency. In applications requiring precise control of loop counts (such as DSP algorithms), programmers are forced to use complex branch instruction combinations to achieve this, which increases programming complexity and makes code maintenance more difficult. Summary of the Invention

[0004] The object of the present invention is to provide a loop branch prediction instruction fetching device, a processor and an electronic device to improve the above-mentioned problem.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides a loop branch prediction instruction fetching device, the loop branch prediction instruction fetching device comprising: a reference unit, a first branch predictor, a second branch predictor, and an instruction storage unit;

[0007] The reference unit is configured to generate a reference address based on address data acquired in a current clock cycle, wherein a priority of the address data provided by the first branch predictor is lower than a priority of the address data provided by the second branch predictor;

[0008] The instruction storage unit is used to read a historical reference address for prefetching. When the historical reference address hits the instruction storage unit, the target instruction corresponding to the historical reference address is transmitted to the first branch predictor after K clock cycles. The historical reference address is a reference address generated by the reference unit in the previous clock cycle, and K ≥ 1.

[0009] The first branch predictor is used to read the historical reference address, perform address prediction based on the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit;

[0010] The second branch predictor is used to read the historical reference address, and when the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, provide the stored loop start address to the reference unit.

[0011] Optionally, the first branch predictor is further configured to, when the target instruction corresponding to the historical reference address is a loopi instruction, send the total number of loops and a loop start address corresponding to the loopi instruction to the second branch predictor; wherein the loop start address is a start address of the next instruction after the loopi instruction;

[0012] The first branch predictor is further configured to send a loop end address monitoring indication to the second branch predictor when the target instruction corresponding to the historical reference address is a loopend instruction, the loop end address monitoring indication including the loop end address corresponding to the loopend instruction;

[0013] The second branch predictor is used to store the total number of loops, the loop start address, and the loop end address when receiving them, and use the total number of loops as the number of pending loops.

[0014] Optionally, the second branch predictor is configured to provide the stored loop start address to the reference unit when obtaining the current loop end address for the first time.

[0015] Optionally, the first branch predictor is further configured to, when the target instruction corresponding to the historical reference address is a loopr instruction, cause the loop branch prediction instruction fetching device to enter a waiting state;

[0016] The second branch predictor is configured to store the total number of loops and the loop start address corresponding to the loopr instruction sent by the back-end branch execution unit when obtaining the total number of loops and the loop start address, and use the total number of loops as the number of pending loops;

[0017] When the reference unit obtains the loop start address corresponding to the loopr instruction sent by the back-end branch execution unit, it exits from the waiting state and uses the loop start address as the reference address of the current clock cycle;

[0018] The first branch predictor is further configured to send a loop end address monitoring indication to the second branch predictor when the target instruction corresponding to the historical reference address is a loopend instruction, the loop end address monitoring indication including the loop end address corresponding to the loopend instruction;

[0019] The second branch predictor is configured to store the loop end address upon receiving it.

[0020] Optionally, the second branch predictor is configured to control the number of pending loops stored therein to be reduced by one after providing a valid loop start address to the reference unit.

[0021] Optionally, the second branch predictor is configured to control the number of pending loops stored therein to be reduced by one upon receiving the loop end address monitoring indication sent by the first branch predictor.

[0022] Optionally, the instruction storage unit includes an instruction cache and an instruction queue;

[0023] The instruction cache is used to obtain the instruction corresponding to the historical reference address when the historical reference address does not hit the instruction queue but hits the instruction cache, and send the corresponding instruction to the first branch predictor and the instruction queue after K clock cycles;

[0024] The instruction queue is used to send the corresponding instruction to the first branch predictor after K clock cycles when the historical reference address hits the instruction queue.

[0025] Optionally, the reference unit includes a selector and a first register;

[0026] The first input of the selector is connected to the output of the first branch predictor for receiving a predicted address; the second input of the selector is connected to the output of the second branch predictor for receiving a loop start address; the third input of the selector is connected to the branch execution unit of the back end for receiving a result address, wherein the result address includes the loop start address corresponding to the loopr instruction fed back by the branch execution unit;

[0027] The output end of the selector is connected to the input end of the first register, and the first register is connected to the first branch predictor, the second branch predictor and the instruction storage unit respectively;

[0028] The selector is used to switch the internal conduction relationship according to the rule that the priority of the result address, the loop start address fed back by the second branch predictor and the predicted address decreases in sequence, and write the corresponding address data into the first register as the reference address of the current clock cycle.

[0029] In a second aspect, an embodiment of the present invention provides a processor, comprising the above-mentioned loop branch prediction and instruction fetching device.

[0030] In a third aspect, an embodiment of the present invention provides an electronic device comprising the above-mentioned processor.

[0031] Compared to the prior art, the embodiments of the present invention provide a loop branch prediction instruction fetching device, processor, and electronic device. A reference unit is used to generate a reference address based on address data acquired in the current clock cycle. An instruction storage unit is used to read a historical reference address for prefetching. When the historical reference address hits the instruction storage unit, the target instruction corresponding to the historical reference address is transmitted to a first branch predictor after K clock cycles. The first branch predictor is used to read the historical reference address, perform address prediction based on the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit. A second branch predictor is used to read the historical reference address and, if the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, provide the stored loop start address to the reference unit. Reducing the number of instructions required to maintain loop variables and judgment conditions can reduce code complexity and maintenance difficulty, improve instruction fetching efficiency, and fully realize the performance potential of the processor.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a structural diagram of a loop branch prediction and instruction fetching device provided by an embodiment of the present invention.

[0035] Figure 2 This is a second structural diagram of the loop branch prediction and instruction fetching device provided by an embodiment of the present invention.

[0036] Figure 3 The third structural diagram of the loop branch prediction and instruction fetching device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0039] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0040] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0041] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0042] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0043] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0044] The embodiment of the present invention provides a loop branch prediction instruction fetching device, which reduces the number of instructions to maintain loop variables and judgment conditions, can reduce the complexity and maintenance difficulty of the code, improve the efficiency of instruction acquisition, and give full play to the performance potential of the processor. Figure 1 , Figure 1 This is a structural diagram of a loop branch prediction and instruction fetching device provided by an embodiment of the present invention.

[0045] The loop branch prediction instruction fetching device includes: a reference unit, a first branch predictor, a second branch predictor and an instruction storage unit.

[0046] The first input of the reference unit is connected to the output of the first branch predictor, the second input of the reference unit is connected to the output of the second branch predictor, and the third input of the reference unit is used to connect to the branch execution unit of the back-end. The output of the reference unit is respectively connected to the first branch predictor, the second branch predictor, and the instruction storage unit. The first branch predictor is respectively connected to the second branch predictor and the instruction storage unit. The second branch predictor is also used to connect to the branch execution unit of the back-end.

[0047] The reference unit is used to generate a reference address according to address data acquired in a current clock cycle, wherein the priority of the address data provided by the first branch predictor is lower than the priority of the address data provided by the second branch predictor.

[0048] The address data obtained by the reference unit includes the predicted address provided by the first branch predictor, the loop start address provided by the second branch predictor, and the result address provided by the branch execution unit. The result address is the target address of the branch instruction parsed by the branch execution unit.

[0049] In an optional embodiment, the priority of the result address, the loop start address provided by the second branch predictor, and the predicted address are sequentially lowered. When the reference unit simultaneously obtains the above data, the reference address is determined according to the priority. Specifically, when the result address is obtained, the result address is used as the reference address for the current clock cycle; when only the predicted address and the loop start address provided by the second branch predictor are obtained, the loop start address provided by the second branch predictor is used as the reference address for the current clock cycle; when only the predicted address is obtained, the predicted address is used as the reference address for the current clock cycle.

[0050] The instruction storage unit is used to read the historical reference address for prefetching. When the historical reference address hits the instruction storage unit, the target instruction corresponding to the historical reference address is transmitted to the first branch predictor after K clock cycles. The historical reference address is the reference address generated by the reference unit in the previous clock cycle, and K≥1.

[0051] Prefetching refers to writing a historical reference address into an instruction queue in an instruction storage unit for calling by a back-end branch execution unit.

[0052] If the historical reference address misses the instruction storage unit, the instruction storage unit generates a miss signal to suspend the loop branch prediction device's prediction. After retrieving the instruction corresponding to the historical reference address from main memory, the instruction storage unit generates a resume signal to transmit the retrieved target instruction to the first branch predictor, resuming the update of registers in the loop branch prediction device and resuming predictive instruction fetching. The instructions in the instruction queue can be called by the back-end module.

[0053] The first branch predictor is used to read a historical reference address, perform address prediction according to the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit.

[0054] The second branch predictor is used to read the historical reference address. When the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, the stored loop start address is provided to the reference unit to restart the loop execution of the corresponding instruction.

[0055] When the number of waiting loops = 0, exit the loop.

[0056] The loop branch prediction instruction fetching device provided by the embodiment of the present invention reduces instructions to maintain loop variables and judgment conditions, can reduce code complexity and maintenance difficulty, improve instruction acquisition efficiency, and give full play to the performance potential of the processor.

[0057] It should be understood that the second branch predictor is provided with three registers, respectively for storing the loop start address, the loop end address, and the number of pending loops. Based on the foregoing, the present invention also provides an optional implementation method for updating the three registers in the second branch predictor, which is referenced below.

[0058] The first branch predictor is further configured to send the total number of loops and the loop start address corresponding to the loopi instruction to the second branch predictor when the target instruction corresponding to the historical reference address is the loopi instruction (loopimmediate instruction); wherein the loop start address is the start address of the next instruction after the loopi instruction.

[0059] It should be noted that the total number of loops in the loopi instruction is the immediate value (unsigned number form) in the loopi instruction, which can be directly obtained when the instruction is decoded.

[0060] The first branch predictor is also used to send a loop end address monitoring indication to the second branch predictor when the target instruction corresponding to the historical reference address is a loopend instruction (indicating the end of the loop body). The loop end address monitoring indication includes the loop end address corresponding to the loopend instruction. The loop end address monitoring indication indicates that the first branch predictor has obtained the loopend instruction, and at this time the first branch predictor will not output a valid predicted address.

[0061] The second branch predictor is used to store the total number of loops, the loop start address, and the loop end address when receiving them, and use the total number of loops as the number of pending loops.

[0062] In an optional implementation, the second branch predictor is configured to provide the stored loop start address to the reference unit when acquiring the current loop end address for the first time.

[0063] Optionally, the first branch predictor is further configured to cause the loop branch prediction instruction fetching device to enter a waiting state, suspend prediction, and cause the reference unit to stop outputting a valid reference address when the target instruction corresponding to the historical reference address is a loopr instruction (loop register instruction).

[0064] In an embodiment of the present invention, the loopr instruction is the start instruction of a first-type loop body. The total number of loops corresponding to the loopr instruction is stored in the corresponding integer register rs1. The integer register rs1 stores an unsigned value representing the total number of loops corresponding to the loopr instruction. The total number of loops corresponding to the loopr instruction needs to be obtained by the back-end execution unit.

[0065] The loopi instruction is the start instruction of the second type of loop body. The total number of loops in the loopi instruction is an immediate value (unsigned number) in the loopi instruction, which can be directly obtained during instruction decoding.

[0066] The loopend instruction is an instruction indicating the end of the loop body.

[0067] The second branch predictor is used to store the total number of loops and the loop start address corresponding to the loopr instruction sent by the back-end branch execution unit when obtaining them, and use the total number of loops as the number of pending loops.

[0068] When the reference unit obtains the loop start address corresponding to the loopr instruction sent by the branch execution unit of the back end, it exits from the waiting state and uses the loop start address as the reference address of the current clock cycle (provided to the back end).

[0069] The first branch predictor is also used to send a loop end address monitoring indication to the second branch predictor when the target instruction corresponding to the historical reference address is a loopend instruction. The loop end address monitoring indication includes the loop end address corresponding to the loopend instruction, and at this time the first branch predictor will not output a valid predicted address.

[0070] The second branch predictor is used to store the loop end address when it is received.

[0071] Optionally, the second branch predictor is configured to control the number of pending loops stored in the reference unit to be reduced by one after providing a valid loop start address to the reference unit.

[0072] Optionally, the second branch predictor is configured to control the number of pending loops stored therein to be reduced by one upon receiving the loop end address monitoring indication sent by the first branch predictor.

[0073] Please refer to Table 1, Table 2, and Table 3 below for the formats of the loopr, loopi, and loopend instructions, respectively.

[0074] Table 1

[0075]

[0076] Table 2

[0077]

[0078] Table 3

[0079]

[0080] The loop body of the loopr instruction is, for example:

[0081] loopr x5

[0082] / / other instructions

[0083] / / these instructions will be executed by (x5) times

[0084] Loopend

[0085] / / instructions after loop

[0086] The loop body of the loopi instruction is, for example:

[0087] loopi 10

[0088] / / other instructions

[0089] / / these instructions will be executed by10 times

[0090] Loopend

[0091] / / instructions after loop

[0092] exist Figure 1 On the basis of the structure of the instruction storage unit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 This is a second structural diagram of the loop branch prediction and instruction fetching device provided by an embodiment of the present invention.

[0093] The instruction storage unit includes an instruction cache and an instruction queue.

[0094] The instruction cache is used to obtain the instruction corresponding to the historical reference address when the historical reference address does not hit the instruction queue but hits the instruction cache, and send the corresponding instruction to the first branch predictor and the instruction queue after K clock cycles.

[0095] The instruction queue is used to send the corresponding instruction to the first branch predictor after K clock cycles when the historical reference address hits the instruction queue.

[0096] When the first historical reference address misses the instruction cache, the instruction cache generates a miss signal to stop updating the registers in the loop branch prediction instruction fetching device, and after obtaining the instruction corresponding to the historical reference address from the main memory, generates a resume signal to resume updating the loop branch prediction instruction fetching device.

[0097] exist Figure 1 On the basis of the structure of the instruction storage unit, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 3 , Figure 3 The third structural diagram of the loop branch prediction and instruction fetching device provided by an embodiment of the present invention.

[0098] The reference unit includes a selector and a first register (register 1).

[0099] The first input end of the selector is connected to the output end of the first branch predictor for accessing the predicted address; the second input end of the selector is connected to the output end of the second branch predictor for accessing the loop start address; the third input end of the selector is used to connect to the branch execution unit of the back end for accessing the result address, wherein the result address includes the loop start address corresponding to the loopr instruction fed back by the branch execution unit.

[0100] The output end of the selector is connected to the input end of the first register, and the first register is connected to the first branch predictor, the second branch predictor and the instruction storage unit respectively.

[0101] The selector is used to switch the internal conduction relationship according to the rule that the priority of the result address, the loop start address fed back by the second branch predictor and the predicted address decreases in sequence, and write the corresponding address data into the first register as the reference address of the current clock cycle.

[0102] An embodiment of the present invention further provides a processor, which includes the above-mentioned loop branch prediction and instruction fetching device.

[0103] An embodiment of the present invention further provides an electronic device, including the above-mentioned processor.

[0104] In summary, embodiments of the present invention provide a loop branch prediction instruction fetching device, processor, and electronic device. A reference unit is configured to generate a reference address based on address data acquired during the current clock cycle. An instruction storage unit is configured to read a historical reference address for prefetching. When the historical reference address hits the instruction storage unit, the target instruction corresponding to the historical reference address is transmitted to a first branch predictor after K clock cycles. The first branch predictor is configured to read the historical reference address, perform address prediction based on the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit. A second branch predictor is configured to read the historical reference address and, if the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, provide the stored loop start address to the reference unit. Reducing the number of instructions required to maintain loop variables and judgment conditions can reduce code complexity and maintenance difficulty, improve instruction fetching efficiency, and fully realize the processor's performance potential.

[0105] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0106] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A loop branch prediction instruction fetching device, characterized in that: The loop branch prediction instruction fetching device comprises: a reference unit, a first branch predictor, a second branch predictor and an instruction storage unit; The reference unit is configured to generate a reference address based on address data acquired in a current clock cycle, wherein a priority of the address data provided by the first branch predictor is lower than a priority of the address data provided by the second branch predictor; The instruction storage unit is used to read a historical reference address for prefetching. When the historical reference address hits the instruction storage unit, the target instruction corresponding to the historical reference address is transmitted to the first branch predictor after K clock cycles. The historical reference address is a reference address generated by the reference unit in the previous clock cycle, and K ≥ 1. The first branch predictor is used to read the historical reference address, perform address prediction based on the historical reference address and its corresponding target instruction, and provide the predicted address to the reference unit; The second branch predictor is used to read the historical reference address, and when the historical reference address is the same as the loop end address stored therein and the number of pending loops is greater than 0, provide the stored loop start address to the reference unit.

2. The loop branch prediction instruction fetching device according to claim 1, wherein: The first branch predictor is further configured to, when the target instruction corresponding to the historical reference address is a loopi instruction, send the total number of loops and the loop start address corresponding to the loopi instruction to the second branch predictor; wherein the loop start address is the start address of the next instruction after the loopi instruction; The first branch predictor is further configured to send a loop end address monitoring indication to the second branch predictor when the target instruction corresponding to the historical reference address is a loopend instruction, the loop end address monitoring indication including the loop end address corresponding to the loopend instruction; The second branch predictor is used to store the total number of loops, the loop start address, and the loop end address when receiving them, and use the total number of loops as the number of pending loops.

3. The loop branch prediction instruction fetching device according to claim 2, wherein: The second branch predictor is configured to provide the stored loop start address to the reference unit when acquiring the current loop end address for the first time.

4. The loop branch prediction instruction fetching device according to claim 1, wherein: The first branch predictor is further configured to cause the loop branch prediction instruction fetching device to enter a waiting state when the target instruction corresponding to the historical reference address is a loopr instruction; The second branch predictor is configured to store the total number of loops and the loop start address corresponding to the loopr instruction sent by the back-end branch execution unit when obtaining the total number of loops and the loop start address, and use the total number of loops as the number of pending loops; When the reference unit obtains the loop start address corresponding to the loopr instruction sent by the back-end branch execution unit, it exits from the waiting state and uses the loop start address as the reference address of the current clock cycle; The first branch predictor is further configured to send a loop end address monitoring indication to the second branch predictor when the target instruction corresponding to the historical reference address is a loopend instruction, the loop end address monitoring indication including the loop end address corresponding to the loopend instruction; The second branch predictor is configured to store the loop end address upon receiving it.

5. The loop branch prediction and instruction fetching device according to any one of claims 2 to 4, characterized in that: The second branch predictor is used to control the number of pending loops stored in the reference unit to be reduced by one after providing a valid loop start address to the reference unit.

6. The loop branch prediction and instruction fetching device according to any one of claims 2 to 4, characterized in that: The second branch predictor is configured to control the number of pending loops stored therein to be reduced by one upon receiving the loop end address monitoring indication sent by the first branch predictor.

7. The loop branch prediction instruction fetching device according to claim 1, wherein: The instruction storage unit includes an instruction cache and an instruction queue; The instruction cache is used to obtain the instruction corresponding to the historical reference address when the historical reference address does not hit the instruction queue but hits the instruction cache, and send the corresponding instruction to the first branch predictor and the instruction queue after K clock cycles; The instruction queue is used to send the corresponding instruction to the first branch predictor after K clock cycles when the historical reference address hits the instruction queue.

8. The loop branch prediction instruction fetching device according to claim 1, wherein: The reference unit includes a selector and a first register; The first input of the selector is connected to the output of the first branch predictor for receiving a predicted address; the second input of the selector is connected to the output of the second branch predictor for receiving a loop start address; the third input of the selector is connected to the branch execution unit of the back end for receiving a result address, wherein the result address includes the loop start address corresponding to the loopr instruction fed back by the branch execution unit; The output end of the selector is connected to the input end of the first register, and the first register is connected to the first branch predictor, the second branch predictor and the instruction storage unit respectively; The selector is used to switch the internal conduction relationship according to the rule that the priority of the result address, the loop start address fed back by the second branch predictor and the predicted address decreases in sequence, and write the corresponding address data into the first register as the reference address of the current clock cycle.

9. A processor, characterized in that: The processor includes the loop branch prediction and instruction fetching device according to any one of claims 1 to 8.

10. An electronic device, characterized in that: comprising the processor of claim 9.

Images