Digital gain adjustment control circuit

Abstract

The invention discloses a digital gain adjustment control circuit which comprises a power detector, a digital peak detector, a gain control module and a digital gain adjustment module. The power detector calculates the power of an input signal by adopting a smooth root-mean-square algorithm, and rapidly adjusts a gain coefficient according to different step lengths adapted to regions; the digital peak value detector adopts a sliding window maximum value method to detect the peak value of an input signal, carries out statistical counting on the overload and underload states of the peak value based on a two-stage method, and judges and adjusts the gain according to a comparison result with a threshold value, so that the influence of frequent gain refreshing on the AGC loop state is avoided, and the loop stabilization time is shortened. Flexible algorithm upgrading and parameter configuration are supported by adopting a full-digital framework, different communication standards are adapted through firmware updating, the limitation of single index control is solved through a dual-detection cooperative working mode, peak overshoot is effectively restrained while the average power of the system is kept stable, the system is conveniently integrated to an SoC chip through modular design, and the reliability of the system is improved. And the power consumption and the size are greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a digital gain adjustment control circuit. Background Art

[0002] Because analog AGC has slow convergence and is susceptible to environmental influences, adjusting the receive channel gain cannot meet the requirements of applications requiring high accuracy and stability. Currently, much research is turning to digital implementations of the AGC loop. The AGC loop primarily consists of three modules: a gain module, a detection and comparison module, and a gain control module. In a digital AGC, the receive channel's high-speed ADC is integrated into the loop to sample the VGA output signal. This signal is then fed into a digital processing module, which detects the signal strength and calculates the ADC input power. This is then compared with a reference power to generate a control signal, achieving gain control.

[0003] The gain control module is a key component of the AGC loop. Digital and analog circuits implement gain control using the same principles: comparing the output signal with a reference voltage and transmitting the comparison result as loop response feedback to the gain module. However, the control signal directly obtained by the digital processing module after processing the information sent by the detector is a discrete binary quantity. Depending on the gain module used in the AGC, the digital AGC loop will differ slightly. If a programmable gain amplifier is used, the gain can be adjusted directly using a binary control word. However, if a continuously gain-adjustable VGA is used, an analog signal is required for control, and a DAC must be added to the loop to convert the digital signal into an analog signal.

[0004] Current research on implementing AGC loops in the digital domain focuses on structural and algorithmic design improvements, optimizing performance such as dynamic range, regulation accuracy, and settling time. Because analog circuits enable real-time signal adjustment and rapid response, while digital circuits offer greater flexibility, many studies combine analog front-ends with digital control logic, using digital feedback to adjust analog gain, achieving a balance between rapid response and flexible control. Summary of the Invention

[0005] The object of the present invention is to provide a digital gain adjustment control circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a digital gain adjustment control circuit, comprising: a power detector, a digital peak detector, a gain control module and a digital gain adjustment module;

[0007] The external input I and Q baseband data are connected to the input ports of the power detector and the digital peak detector respectively, the output end of the power detector is connected to the input end of the gain control module, the output end of the digital peak detector is connected to the input end of the gain control module, and the output end of the gain control module is connected to the input end of the digital gain adjustment module;

[0008] The power detector detects the average power of the input signal and sends the detection result to the gain control module; the digital peak detector detects the peak value of the input signal and sends the detection result to the gain control module; the gain control module processes the received detection value according to the preset threshold, obtains the gain adjustment value and sends it to the digital gain adjustment module to achieve gain adjustment of the input signal.

[0009] In one embodiment, the power detector detects the average power of the input signal, including: first calculating the square sum of the I and Q signals to obtain the signal power; during the measurement process, measuring the power of all signals in the tuning window, where the window value is set according to actual application requirements and does not exceed the full-scale value of the gain update counter; resetting the power detector when the gain update counter is full-scale, performing multiple power measurements in a window and accumulating them, and calculating the average value after the window counter is full and outputting it to the gain control module.

[0010] In one embodiment, the gain control module first compares the detected signal with the threshold and sets four thresholds: an out-of-range high power threshold ORPT H , Out of range low power threshold ORPT L and underrange high power threshold URPT H , Underrange Low Power Threshold URPT L ;

[0011] When the detected power P is within [ORPT L , ORPT H ], the AGC does not change the gain;

[0012] When the power P is lower than ORPT L or greater than ORPT H When , the AGC waits for the next gain update counter to be full, and then increases or decreases the gain with a larger gain step size;

[0013] When the measured value of power P is [URPT H , URPT L ] or [ORPT H , ORPT L ] interval, the AGC increases or decreases the gain with a smaller gain step; larger and smaller are relative and can be set by the user as needed.

[0014] In one embodiment, the digital peak detector detects the peak value of I or Q within a tuning window, the tuning window is configured according to actual application, and the absolute value of the sampled value is calculated and filtered.

[0015] In one embodiment, the digital peak detector is implemented using a two-stage method. The gain update counter is a cycle, and this cycle is further divided into smaller time subsets. Each subset is a cycle of the overload duration counter. The tuning window is also a subset of the overload duration counter. Each cycle is considered separately. The individual samples exceeding the threshold are greater than the set value, indicating that the cycle exceeds the overload threshold; within the gain update counter cycle, if the number of samples exceeding the overload threshold exceeds the expected value, the overrange condition is triggered; if the number of underloads exceeds the low threshold, the underrange condition is triggered.

[0016] In one embodiment, the value detected by the digital peak detector is sent to the corresponding gain control module to calculate the gain, the gain update counter is reset, the overload duration counter is reset at the same time, and the overload counter and underload counter are reset to start peak detection;

[0017] The detected value is compared with the preset high and low thresholds. If it is greater than the high preset value, the overload counter is incremented by 1, and if it is less than the low preset value, the underload counter is incremented by 1. When the overload counter reaches the maximum value, the overload counter and underload counter are compared with the preset overload threshold and underload threshold respectively:

[0018] When the overload counter is greater than the overload threshold, the gain is reduced;

[0019] When the underload counter is greater than the underload threshold, the gain increases;

[0020] When the overload counter is less than the overload threshold and the underload counter is less than the underload threshold, the gain remains unchanged; then, the overload counter is reset, and the underload counter is reset at the same time, and it is determined whether the gain update counter is full. If not, a new round of peak detection is started to determine the direction of gain change until the gain update counter is full, the gain value is output, and all counters are reset again.

[0021] This invention provides a digital gain adjustment control circuit that uses a two-stage cascade to achieve gain modulation, improving the speed and accuracy of channel gain compensation to meet the requirements of high-bandwidth receivers in 5G communication systems. This circuit can quickly adjust the input signal to the target range, with a minimum achievable step of 0.05dB and a gain range of 0-50dB. Compared with analog gain modulation circuits, this circuit offers greater flexibility, higher adjustment accuracy, and more stable output signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a system structure diagram of the digital gain adjustment control circuit provided by the present invention.

[0023] Figure 2 This is a functional diagram of the digital gain adjustment control circuit provided by the present invention.

[0024] Figure 3 This is a working flow chart of the digital gain adjustment control circuit provided by the present invention.

[0025] Figure 4 This is a flow chart of power detection gain control of the present invention.

[0026] Figure 5 This is a flow chart of the digital peak detection gain control of the present invention. DETAILED DESCRIPTION

[0027] The following is a further detailed description of a digital gain adjustment control circuit proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0028] The present invention provides a digital gain adjustment control circuit, which is mainly embedded in 5G communication network chips to achieve gain modulation of radio frequency signals.

[0029] Figure 1 This is a system structure diagram of the present invention, and its core modules include: a power detector, a digital peak detector, a gain control module, and a digital gain adjustment module. A pair of I and Q baseband orthogonal data input from the outside is simultaneously connected to the input ports of the power detector and the digital peak detector. The output of the power detector is connected to the input of the gain control module, the output of the digital peak detector is connected to the input of the gain control module, and the output of the gain control module is connected to the input of the digital gain adjustment module. The power detector detects the average power of the input signal and sends it to the gain control module; the digital peak detector detects the peak value of the input signal and sends it to the gain control module; the gain control module processes the received detection value according to a preset threshold, obtains a gain adjustment value, and sends it to the digital gain adjustment module to adjust the gain of the input signal.

[0030] Figure 2 This is the functional diagram of the digital gain adjustment control circuit of the present invention. The I and Q channel ADCs output digital baseband signals. After digital filtering, I in / Q inEntering the digital baseband AGC loop power or amplitude peak detection circuit, the multiplexer (MUX) switches between amplitude calculation and power calculation to select the measured value for gain control. The measured value is filtered by mean, and the signal is smoothed before entering the gain control module. In the gain control module, the gain adjustment amount of the large dynamic range signal is first calculated using exponential operation, and then the filtered signal strength is compared with the preset threshold based on the threshold comparison to determine whether gain adjustment is required; the gain coefficient calculation module calculates the gain adjustment coefficient based on the comparison result and provides the control parameter for the gain adjustment module. The gain adjustment module adjusts the gain output signal I according to the calculated gain coefficient. out / Q out .

[0031] Figure 3 This is a flowchart of the digital gain adjustment control circuit of the present invention. Initially, parameters such as the threshold, step size, and smoothing window length are set. A signal detection module is selected based on the mode setting. For example, if power detection is selected, the signal detection module calculates the power of the input signal using a smoothed RMS algorithm and compares the resulting signal power value with the threshold.

[0032] Figure 4 This is the power detection gain control flow chart of the present invention. In this control system, four thresholds are set: out-of-range high power threshold (ORPT H ), Out of Range Low Power Threshold (ORPT L ) and Underrange High Power Threshold (URPT H ), Under Range Low Power Threshold (URPT L ). When I in / Q in The value of power P in [ORPT L , URPT H ], AGC does not change the gain. When the power P is lower than URPT L or greater than ORPT H When the AGC waits for the next gain update counter to be full, it increases or decreases the gain with a larger gain step; when the measured value of the power P is within [URPT H , URPT L ] or [ORPT H , ORPT L ] interval, the AGC increases or decreases the gain with a smaller gain step; larger and smaller are relative terms and can be set by the user as needed, with a minimum value of 0.05dB.

[0033] To prevent jitter in the output signal caused by frequent short-term gain fluctuations due to immediate signal fluctuations, the power of all signals within the tuning window is measured during the measurement process. The window value is set according to the actual application requirements and does not exceed the full-scale value of the gain update counter. When the gain update counter reaches full scale, the power detector is reset. Multiple power measurements are performed within a window and accumulated. When the window counter is full, the average value is calculated and output to the gain control module.

[0034] If peak detection mode is selected, the I or Q peak is detected and the detected sample value is absolute valued and filtered. The digital peak detector is implemented using a two-stage method. The gain update counter is a period, which is further divided into smaller time subsets. Each time subset is a period of the overload duration counter. The tuning window is a subset of the overload duration counter. Each period is considered separately and compared with the threshold. Figure 5 This is a flow chart of the gain control for digital peak detection. The gain update counter (GainUpCnt) is reset, the overload hold counter (OverHoldCnt) is reset at the same time, and the overload counter (OverCnt) and underload counter (UnderCnt) are reset to start detecting the digital peak. The detected value is compared with the preset high and low thresholds. If it is greater than the high threshold, the overload counter is incremented by 1, and if it is less than the low threshold, the underload counter is incremented by 1. When the overload counter counts to the maximum value, the overload counter and underload counter are compared with the preset overload threshold and underload threshold respectively. When the overload counter is greater than the overload threshold, the gain decreases; when the underload counter is greater than the underload threshold, the gain increases; when the overload counter is less than the overload threshold, and the underload counter is less than the underload threshold, the gain remains unchanged. Then, reset the overload counter and the underload counter at the same time, and determine whether the gain update counter is full. If it is not full, start a new round of peak detection, determine the direction of gain change, until the gain update counter is full, output the gain value, and reset all counters. See the detailed algorithm flow. Figure 5 Compared with the traditional binary method, the advantage of this two-stage algorithm is that it can reduce the frequent output of gain and shorten the loop stabilization time.

[0035] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A digital gain adjustment control circuit, characterized in that: include: Power detector, digital peak detector, gain control module and digital gain adjustment module; The external input I and Q baseband data are connected to the input ports of the power detector and the digital peak detector respectively, the output end of the power detector is connected to the input end of the gain control module, the output end of the digital peak detector is connected to the input end of the gain control module, and the output end of the gain control module is connected to the input end of the digital gain adjustment module; The power detector detects the average power of the input signal and sends the detection result to the gain control module; The digital peak detector detects the peak value of the input signal and sends the detection result to the gain control module; the gain control module processes the received detection value according to the preset threshold, obtains the gain adjustment value and sends it to the digital gain adjustment module to achieve gain adjustment of the input signal.

2. The digital gain adjustment control circuit according to claim 1, wherein: The power detector detects the average power of the input signal, including: first, calculating the square sum of the I and Q signals to obtain the signal power; during the measurement process, measuring the power of all signals in the tuning window, where the window value is set according to actual application requirements and does not exceed the full-scale value of the gain update counter; resetting the power detector when the gain update counter is full, performing multiple power measurements in a window and accumulating them, and calculating the average value after the window counter is full and outputting it to the gain control module.

3. The digital gain adjustment control circuit according to claim 2, wherein: The gain control module first compares the detected signal with the threshold and sets four thresholds: out-of-range high power threshold ORPT H , Out of range low power threshold ORPT L and underrange high power threshold URPT H , Underrange Low Power Threshold URPT L ; When the detected power P is within [ORPT L , ORPT H ], the AGC does not change the gain; When the power P is lower than ORPT L or greater than ORPT H When , the AGC waits for the next gain update counter to be full, and then increases or decreases the gain with a larger gain step size; When the measured value of power P is [URPT H , URPT L ] or [ORPT H , ORPT L ] interval, the AGC increases or decreases the gain with a smaller gain step; larger and smaller are relative and can be set by the user as needed.

4. The digital gain adjustment control circuit according to claim 3, wherein: The digital peak detector detects the peak value of I or Q within a tuning window. The tuning window is configured according to actual application. The absolute value of the sampled value is calculated and filtered.

5. The digital gain adjustment control circuit according to claim 4, wherein: The digital peak detector is implemented using a two-stage method. The gain update counter is a cycle, which is further divided into smaller time subsets. Each subset is a cycle of the overload duration counter. The tuning window is a subset of the overload duration counter. Each cycle is considered separately. If the individual samples exceeding the threshold are greater than the set value, it means that the cycle exceeds the overload threshold. Within the gain update counter cycle, if the number of samples exceeding the overload threshold exceeds the expected value, the overrange condition is triggered; if the number of underloads exceeds the low threshold, the underrange condition is triggered.

6. The digital gain adjustment control circuit according to claim 5, wherein: The value detected by the digital peak detector is sent to the corresponding gain control module to calculate the gain, the gain update counter is reset, the overload duration counter is reset at the same time, and the overload counter and underload counter are reset to start peak detection; The detected value is compared with the preset high and low thresholds. If it is greater than the high preset value, the overload counter is incremented by 1, and if it is less than the low preset value, the underload counter is incremented by 1. When the overload counter reaches the maximum value, the overload counter and underload counter are compared with the preset overload threshold and underload threshold respectively: When the overload counter is greater than the overload threshold, the gain is reduced; When the underload counter is greater than the underload threshold, the gain increases; When the overload counter is less than the overload threshold and the underload counter is less than the underload threshold, the gain remains unchanged; then, the overload counter is reset, and the underload counter is reset at the same time, and it is determined whether the gain update counter is full. If not, a new round of peak detection is started to determine the direction of gain change until the gain update counter is full, the gain value is output, and all counters are reset again.

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