Enhanced gallium nitride device based on lamination passivation and manufacturing method thereof

Abstract

The invention relates to an enhanced gallium nitride device based on lamination passivation and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top, a P-GaN cap layer is arranged on the upper side of the AlGaN barrier layer, passivation layers are arranged on the portions, on the two sides of the P-GaN cap layer, of the AlGaN barrier layer, source electrode metal and drain electrode metal are arranged on the two sides of each passivation layer respectively, the source electrode metal and the drain electrode metal extend to the GaN buffer layer, and grid electrode metal is arranged on the upper side of the P-GaN cap layer. According to the invention, the interface quality of the device is obviously improved, the surface trap effect and hot carrier injection are inhibited, the thermal stress mismatch is relieved, and the overall electrical performance and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to an enhanced gallium nitride device based on stacked passivation and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Wide-bandgap GaN materials possess excellent electrical properties, such as high electron mobility, high saturation electron velocity, and high critical breakdown field. These properties make GaN HEMTs (High-Energy Transistor) (HEMTs) promising for applications in high-frequency, high-power, and high-temperature environments. Precisely because of their high output power density and high breakdown voltage, GaN HEMTs have attracted widespread attention in power electronics, RF microwaves, and 5G communications. However, practical applications of GaN HEMTs still face several key technical challenges. Current enhancement-mode (intrinsic-off) GaN HEMTs commonly suffer from low and unstable threshold voltages, insufficient breakdown voltages, weak gate withstand voltages, and high leakage currents. The instability of low threshold voltages can lead to false triggering, place higher demands on the drive circuit, and even accelerate device aging. Low breakdown voltages limit device reliability in high-power environments. Furthermore, excessive gate leakage and low withstand voltages significantly impact device performance and lifetime.

[0003] To meet the application requirements of traditional enhancement-mode GaN HEMTs, various improvement methods have been proposed, such as thickening the P-GaN layer, surface nitridation, extending the drift region length, introducing field plates, or adjusting the AlGaN layer composition, in order to improve threshold voltage and breakdown performance. However, these methods are often accompanied by negative effects such as significantly increased process complexity, increased on-resistance, or decreased carrier mobility, and are also prone to causing new gate leakage and parasitic effects.

[0004] In the traditional P-GaN gate GaN HEMT device structure, the interface between the gate region P-GaN and the passivation layer has the following major problems: (1) High interface state density (Dit): A large number of trap states at the interface will lead to charge capture effect, causing threshold voltage drift and dynamic on-resistance degradation; (2) Hot carrier injection (HCI): Under high electric field, electrons may tunnel into the passivation layer, causing the passivation layer and interface quality to deteriorate, thereby reducing the long-term reliability of the device; (3) Stress mismatch: Due to the large difference in thermal expansion coefficients between the passivation layer and the P-GaN layer, microcracks are easily generated at the interface during the device thermal cycle, reducing mechanical stability and reliability. The above problems jointly limit the performance improvement and reliability of P-GaN HEMT. Summary of the Invention

[0005] In response to the shortcomings of the existing technology, the present invention provides an enhanced gallium nitride device based on stacked passivation. By sequentially introducing multiple layers of functional passivation materials on the device surface, the lattice matching, dielectric properties and thermodynamic properties of each layer of material are synergistically optimized to significantly improve the device interface quality, inhibit surface trap effects and hot carrier injection, alleviate thermal stress mismatch, and enhance the overall electrical performance and reliability of the device.

[0006] The present invention also provides a method for manufacturing the enhanced gallium nitride device based on stacked passivation. The technical solutions of the present invention are as follows: An enhancement-mode gallium nitride device based on stacked passivation comprises, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, and an AlGaN barrier layer. A P-GaN cap layer is provided on the upper side of the AlGaN barrier layer. Passivation layers are provided on the AlGaN barrier layers on both sides of the P-GaN cap layer. Source metal and drain metal are provided on both sides of the passivation layer, respectively. The source metal and drain metal extend to the GaN buffer layer. A gate metal is provided on the upper side of the P-GaN cap layer. The passivation layer includes an AlN passivation layer, a HfO2 passivation layer, a SiO2 passivation layer and a SiN passivation layer in sequence from bottom to top.

[0007] Preferably, according to the present invention, the cross-sections of the AlN passivation layer, the HfO2 passivation layer and the SiO2 passivation layer are all L-shaped, the cross-section of the SiN passivation layer is rectangular, and the AlN passivation layer, the HfO2 passivation layer, the SiO2 passivation layer and the SiN passivation layer are stacked in sequence from bottom to top.

[0008] According to the present invention, preferably, the material of the substrate is silicon carbide, silicon, or sapphire; The thickness of the GaN buffer layer is 0.1-50 μm; The thickness of the GaN channel layer is 5-1000nm; The thickness of the AlN intercalation layer is 0.2-2 nm; The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%; The thickness of the P-GaN cap layer is 1-1000nm, the doping source is magnesium or boron, and the doping concentration is 1×10 17 -1×10 20 cm -3 ; The source metal and the drain metal are made of the same material, which is a Ti / Al / Ni / Au metal stack, a Ti / Al / Ti / Au metal stack, or a Ti / Al / Mo / Au metal stack; The gate metal material is Ni / Au metal stack.

[0009] According to the present invention, the substrate is preferably made of silicon carbide. The thickness of the GaN buffer layer is 2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the P-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ; The source metal and the drain metal are made of Ti / Al / Ni / Au metal stacks.

[0010] According to the present invention, preferably, the thickness of the AlN passivation layer is 5-1000 nm; The thickness of the HfO2 passivation layer is 1-1000nm; The thickness of the SiO2 passivation layer is 10-5000nm; The thickness of the SiN passivation layer is 20-5000 nm.

[0011] According to the present invention, the thickness of the AlN passivation layer is further preferably 15 nm; The thickness of the HfO2 passivation layer is 5 nm; The thickness of the SiO2 passivation layer is 100 nm; The thickness of the SiN passivation layer is 150 nm.

[0012] Preferably, according to the present invention, the device has a gate-source spacing of 4 μm, a gate length of 4 μm, a gate-drain spacing of 12 μm, and a gate width of 100 μm. The gate-source spacing is the distance from the left side of the p-GaN cap layer to the source metal, the gate length is the length between the two ends of the p-GaN cap layer (left to right), the gate-drain spacing is the distance from the right side of the p-GaN cap layer to the drain metal, and the gate width is the extension width of the gate metal into the paper.

[0013] The manufacturing method of the enhancement-mode gallium nitride device based on stacked passivation comprises the following steps: S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a P-GaN cap layer on a substrate; S2, dry etching the P-GaN cap layer except under the gate; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal on the table; S5, annealing the source metal and drain metal regions to form ohmic contacts; S6, depositing an AlN passivation layer on the upper side of the AlGaN barrier layer; S7, performing dry etching on the AlN passivation layer in the region close to the source metal and the drain metal; S8, depositing a HfO2 passivation layer on the AlN passivation layer; S9, performing dry etching on the HfO2 passivation layer in the region close to the source metal and the drain metal; S10, depositing a SiO2 passivation layer on the HfO2 passivation layer; S11, performing dry etching on the SiO2 passivation layer in the region close to the source metal and the drain metal; S12, depositing a SiN passivation layer on the SiO2 passivation layer; S13, evaporating a gate metal on the P-GaN cap layer.

[0014] According to the present invention, preferably, the growth method of the GaN buffer layer, GaN channel layer, AlN intercalation layer, AlGaN barrier layer, and P-GaN cap layer in step S1 is a high-quality film formation method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE); The etching method in steps S2, S3, S7, S9 and S11 is inductively coupled plasma etching (ICP) or reactive ion etching (RIE); The annealing method of the source metal and the drain metal in step S5 is laser selective annealing; The method of depositing the AlN passivation layer in step S6 is metal organic chemical vapor deposition (MOCVD); The method of depositing the HfO2 passivation layer in step S8 is low temperature atomic layer deposition (ALD); The method of depositing the SiO2 passivation layer in step S10 is a high-quality film-forming method such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD); The method for depositing the SiN passivation layer in step S12 is a high-quality film forming method such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0015] According to the present invention, further preferably, the growth method of the GaN buffer layer, GaN channel layer, AlN intercalation layer, AlGaN barrier layer and P-GaN cap layer in step S1 is metal organic chemical vapor deposition; The etching method of steps S2, S3, S7, S9 and S11 is inductively coupled plasma etching; The method of depositing the SiO2 passivation layer in step S10 is low pressure chemical vapor deposition; The method of depositing the SiN passivation layer in step S12 is plasma enhanced chemical vapor deposition.

[0016] The beneficial effects of the present invention are: 1. Significantly improved interface quality: The first AlN passivation layer of the present invention is in direct contact with the P-GaN cap layer. Utilizing its good lattice matching and strong chemical bonding with GaN, it can effectively reduce the interface state density at the gate interface. In-situ MOCVD growth avoids interface oxidation, further improving the crystal quality of the passivation layer and P-GaN interface, optimizing the device surface trap distribution, reducing carrier capture, and contributing to the stabilization of the device threshold voltage.

[0017] 2. Significantly suppresses leakage current: The second passivation layer of the present invention uses a high-dielectric-constant HfO2 passivation layer. Its high-k property enhances the electric field shielding effect of the gate region, effectively preventing the gate region electric field from penetrating into the passivation layer, thereby suppressing gate leakage current. The use of a low-temperature ALD growth process avoids damage to the underlying AlN layer. This design effectively controls leakage current when the device is in the off state.

[0018] 3. Reduced threshold voltage drift and improved dynamic on-resistance: The multilayer passivation structure of this invention optimizes the surface charge distribution and gradient dielectric constant distribution, reducing the charge-discharge effect of interface traps, thereby stabilizing the threshold voltage. Simulation results show that with this stacked passivation structure, the off-state leakage current and threshold voltage of the device remain essentially stable, while the on-state current increases, demonstrating that the surface trap effect is effectively mitigated. The reduced trapping effect also improves the on-resistance (Ron) degradation of the device during dynamic switching.

[0019] 4. Improved breakdown voltage and gate withstand voltage: This invention utilizes a third low-dielectric-constant SiO2 passivation layer as a stress buffer, effectively alleviating the thermal stress mismatch between AlN / HfO2 and the upper SiN layer. Simultaneously, the SiO2 thickness is adjusted to optimize the dielectric constant gradient distribution, reducing the risk of electric field concentration. The outermost, dense SiN passivation layer not only blocks the intrusion of water and oxygen from the environment, but also utilizes its lower dielectric constant to further smooth the electric field distribution in the gate region. This multilayer structure design collectively reduces the local electric field strength, significantly improving the device's breakdown voltage and gate withstand voltage.

[0020] 5. Enhanced device reliability: The multi-layer passivation solution of this invention effectively blocks the corrosion of environmental moisture and oxygen on the device, reducing the accumulation of thermomechanical stress between the passivation layer and the substrate. At the same time, the high-quality interface and stable electric field distribution reduce the accumulation of hot carrier damage caused by high electric fields, thereby significantly improving the long-term stability and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1It is a structural schematic diagram of the present invention; Figure 2 Schematic diagram of conventional device structure; Figure 3 A transfer curve comparison diagram of the stacked passivation device of the present invention and a conventional device; Figure 4 A comparison diagram of the breakdown curves of the stacked passivation device of the present invention and a conventional device; Figure 5 A comparison diagram of gate withstand voltage and leakage current of the stacked passivation device of the present invention and conventional devices; Among them: 1. substrate; 2. GaN buffer layer; 3. GaN channel layer; 4. AlN intercalation layer; 5. AlGaN barrier layer; 6. P-GaN cap layer; 7. AlN passivation layer; 8. HfO2 passivation layer; 9. SiO2 passivation layer; 10. SiN passivation layer; 11. source metal; 12. drain metal; 13. gate metal. DETAILED DESCRIPTION

[0022] The present invention will be further described below with reference to embodiments and accompanying drawings, but is not limited thereto.

[0023] Example 1: like Figure 1 As shown, this embodiment provides an enhancement-mode gallium nitride device based on stacked passivation, which comprises, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4, and an AlGaN barrier layer 5. A P-GaN cap layer 6 is provided on the upper side of the AlGaN barrier layer 5. Passivation layers are provided on the AlGaN barrier layers 5 on both sides of the P-GaN cap layer 6. Source metal 11 and drain metal 12 are provided on both sides of the passivation layer, respectively. The source metal 11 and the drain metal 12 extend to the GaN buffer layer 2. A gate metal 13 is provided on the upper side of the P-GaN cap layer 6. The passivation layer includes, from bottom to top, an AlN passivation layer 7, a HfO2 passivation layer 8, a SiO2 passivation layer 9 and a SiN passivation layer 10.

[0024] The cross sections of the AlN passivation layer 7, the HfO2 passivation layer 8 and the SiO2 passivation layer 9 are all L-shaped, the cross section of the SiN passivation layer 10 is rectangular, and the AlN passivation layer 7, the HfO2 passivation layer 8, the SiO2 passivation layer 9 and the SiN passivation layer 10 are stacked in sequence from bottom to top.

[0025] The gate metal 13 is made of a Ni / Au metal stack; The material of substrate 1 is silicon carbide; The thickness of the GaN buffer layer 2 is 2 μm; The thickness of the GaN channel layer 3 is 200 nm; The thickness of the AlN intercalation layer 4 is 0.5 nm; The thickness of the AlGaN barrier layer 5 is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the P-GaN cap layer 6 is 100 nm, the doping source is magnesium or boron, and the doping concentration is 3×10 19 cm -3 ; The source metal 11 and the drain metal 12 are made of a Ti / Al / Ni / Au metal stack.

[0026] The thickness of the AlN passivation layer 7 is 15 nm; The thickness of the HfO2 passivation layer 8 is 5 nm; The thickness of the SiO2 passivation layer 9 is 100 nm; The thickness of the SiN passivation layer 10 is 150 nm.

[0027] The device has a gate-source spacing of 4μm, a gate length of 4μm, a gate-drain spacing of 12μm, and a gate width of 100μm. The gate-source spacing is the distance from the left side of the p-GaN cap layer to the source metal, the gate length is the length between the two ends of the p-GaN cap layer (left to right), the gate-drain spacing is the distance from the right side of the p-GaN cap layer 6 to the drain metal, and the gate width is the extension width of the gate metal 13 into the paper.

[0028] The manufacturing method of the enhancement-mode gallium nitride device based on stacked passivation comprises the following steps: S1, using metal organic chemical vapor deposition method to grow GaN buffer layer 2, GaN channel layer 3, AlN intercalation layer 4, AlGaN barrier layer 5, and P-GaN cap layer 6 on substrate 1 in sequence; S2, dry etching the P-GaN cap layer 6 except below the gate; S3, removing the GaN channel layer 3, AlN intercalation layer 4, and AlGaN barrier layer 5 outside the device by dry etching to form a mesa; S4, evaporating source metal 11 and drain metal 12 on the mesa; S5, annealing the source metal 11 and the drain metal 12 regions by laser selective annealing to form ohmic contacts; S6, depositing an AlN passivation layer 7 on the upper side of the AlGaN barrier layer by metal organic chemical vapor deposition; S7, performing dry etching on the AlN passivation layer 7 in the region close to the source metal 11 and the drain metal 12; S8, depositing a HfO2 passivation layer 8 on the AlN passivation layer 7 by low temperature atomic layer deposition; S9, performing dry etching on the HfO2 passivation layer 8 in the region close to the source metal 11 and the drain metal 12; S10, depositing a SiO2 passivation layer 9 on the HfO2 passivation layer 8 by using a low pressure chemical vapor deposition method; S11, performing dry etching on the SiO2 passivation layer 9 in the region close to the source metal 11 and the drain metal 12; S12, depositing a SiN passivation layer 10 on the SiO2 passivation layer 9 by plasma enhanced chemical vapor deposition; S13 , evaporating a gate metal 13 on the P-GaN cap layer 6 .

[0029] The etching method of steps S2, S3, S7, S9 and S11 is inductively coupled plasma etching.

[0030] Conventional devices such as Figure 2 As shown, the difference is that the passivation layer only uses a SiO2 passivation layer. The performance of the stacked passivation device of this embodiment and the conventional device are compared and verified in Sentaurus TCAD simulation; (1) Simulation model construction: Two-dimensional structural models of this embodiment and conventional devices were constructed in Sentaurus TCAD software.

[0031] (2) Simulation parameter setting: Set appropriate boundary conditions and initial conditions, including voltage and current. For the transfer curve, first apply a drain voltage of 10V, and then apply a variable gate voltage. For breakdown, first apply a gate voltage of -6V to ensure depletion, and then apply the drain voltage until breakdown. For gate withstand voltage and leakage, first leave the drain floating, and then apply the gate voltage until breakdown.

[0032] (3) Simulation process: Simulation is performed to observe the changes in electrical properties of this embodiment compared with conventional devices.

[0033] (4) Result analysis: Figure 3 It can be seen that the stacked passivation device increases the saturation current while keeping the threshold voltage basically unchanged. Figure 4 In the breakdown curve, the breakdown voltage of the stacked passivation device reached 1044V, which is better than the 955V of the conventional device, with the critical breakdown field strength of GaN material 3.3MV / cm as the judgment standard. Figure 5 In the gate withstand voltage curve, with the gate current reaching 1mA / mm as the standard, the gate withstand voltage of the stacked passivation device reached 20.25V, which is better than the 13.65V of the conventional device; and the gate leakage of the stacked passivation device was reduced by more than three orders of magnitude, which shows that the overall performance and reliability of the device can be significantly improved under the coordinated optimization of the lattice matching, dielectric properties and thermodynamic properties of each layer of the stacked passivation material.

Claims

1. An enhancement-mode gallium nitride device based on stacked passivation, characterized in that: From bottom to top, there are substrate, GaN buffer layer, GaN channel layer, AlN intercalation layer and AlGaN barrier layer. A P-GaN cap layer is provided on the upper side of the AlGaN barrier layer. Passivation layers are provided on the AlGaN barrier layers on both sides of the P-GaN cap layer. Source metal and drain metal are provided on both sides of the passivation layer respectively. The source metal and drain metal extend to the GaN buffer layer. A gate metal is provided on the upper side of the P-GaN cap layer. The passivation layer includes an AlN passivation layer, a HfO2 passivation layer, a SiO2 passivation layer and a SiN passivation layer in sequence from bottom to top.

2. The enhancement-mode gallium nitride device based on stacked passivation according to claim 1, characterized in that: The cross sections of the AlN passivation layer, the HfO2 passivation layer and the SiO2 passivation layer are all L-shaped, the cross section of the SiN passivation layer is rectangular, and the AlN passivation layer, the HfO2 passivation layer, the SiO2 passivation layer and the SiN passivation layer are stacked in sequence from bottom to top.

3. The enhancement-mode gallium nitride device based on stacked passivation according to claim 2, wherein: The substrate material is silicon carbide, silicon, and sapphire; The thickness of the GaN buffer layer is 0.1-50 μm; The thickness of the GaN channel layer is 5-1000nm; The thickness of the AlN intercalation layer is 0.2-2 nm; The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%; The thickness of the P-GaN cap layer is 1-1000nm, the doping source is magnesium or boron, and the doping concentration is 1×10 17 -1×10 20 cm -3 ; The source metal and the drain metal are made of the same material, which is a Ti / Al / Ni / Au metal stack, a Ti / Al / Ti / Au metal stack, or a Ti / Al / Mo / Au metal stack; The gate metal material is Ni / Au metal stack.

4. The enhancement-mode gallium nitride device based on stacked passivation according to claim 3, characterized in that: The material of the substrate is silicon carbide; The thickness of the GaN buffer layer is 2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the P-GaN cap layer is 100 nm and the doping concentration is 3×10 19 cm -3 ; The source metal and the drain metal are made of Ti / Al / Ni / Au metal stacks.

5. The enhancement-mode gallium nitride device based on stacked passivation according to claim 3, characterized in that: The thickness of the AlN passivation layer is 5-1000nm; The thickness of the HfO2 passivation layer is 1-1000nm; The thickness of the SiO2 passivation layer is 10-5000nm; The thickness of the SiN passivation layer is 20-5000 nm.

6. The enhancement-mode gallium nitride device based on stacked passivation according to claim 5, characterized in that: The thickness of the AlN passivation layer is 15 nm; The thickness of the HfO2 passivation layer is 5 nm; The thickness of the SiO2 passivation layer is 100 nm; The thickness of the SiN passivation layer is 150 nm.

7. The enhancement-mode gallium nitride device based on stacked passivation according to claim 5, characterized in that: The device has a gate-source spacing of 4μm, a gate length of 4μm, a gate-drain spacing of 12μm, and a gate width of 100μm. The gate-source spacing is the distance from the p-GaN cap layer to the source metal, the gate length is the length between the two ends of the p-GaN cap layer, the gate-drain spacing is the distance from the p-GaN cap layer to the drain metal, and the gate width is the extension width of the gate metal into the paper.

8. The method for manufacturing an enhancement-mode gallium nitride device based on stacked passivation according to claim 7, wherein: Here are the steps: S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a P-GaN cap layer on a substrate; S2, dry etching the P-GaN cap layer except under the gate; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal on the table; S5, annealing the source metal and drain metal regions to form ohmic contacts; S6, depositing an AlN passivation layer on the upper side of the AlGaN barrier layer; S7, performing dry etching on the AlN passivation layer in the region close to the source metal and the drain metal; S8, depositing a HfO2 passivation layer on the AlN passivation layer; S9, performing dry etching on the HfO2 passivation layer in the region close to the source metal and the drain metal; S10, depositing a SiO2 passivation layer on the HfO2 passivation layer; S11, performing dry etching on the SiO2 passivation layer in the region close to the source metal and the drain metal; S12, depositing a SiN passivation layer on the SiO2 passivation layer; S13, evaporating a gate metal on the P-GaN cap layer.

9. The method for manufacturing an enhancement-mode gallium nitride device based on stacked passivation according to claim 8, wherein: The growth method of the GaN buffer layer, GaN channel layer, AlN intercalation layer, AlGaN barrier layer, and P-GaN cap layer in step S1 is metal organic chemical vapor deposition or molecular beam epitaxy; The etching method in steps S2, S3, S7, S9 and S11 is inductively coupled plasma etching or reactive ion etching; The annealing method of the source metal and the drain metal in step S5 is laser selective annealing; The method of depositing the AlN passivation layer in step S6 is metal organic chemical vapor deposition (MOCVD); The method of depositing the HfO2 passivation layer in step S8 is low temperature atomic layer deposition; The method of depositing the SiO2 passivation layer in step S10 is plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition; The method of depositing the SiN passivation layer in step S12 is plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

10. The method for manufacturing an enhancement-mode gallium nitride device based on stacked passivation according to claim 9, wherein: The growth method of the GaN buffer layer, GaN channel layer, AlN intercalation layer, AlGaN barrier layer and P-GaN cap layer in step S1 is metal organic chemical vapor deposition; The etching method of steps S2, S3, S7, S9 and S11 is inductively coupled plasma etching; The method of depositing the SiO2 passivation layer in step S10 is low pressure chemical vapor deposition; The method of depositing the SiN passivation layer in step S12 is plasma enhanced chemical vapor deposition.

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