Multi-channel ultra-wide frequency domain signal acquisition method and device

Abstract

The invention discloses a multi-channel ultra-wide-frequency-domain signal acquisition method and device. The method comprises the steps that signal sources of multiple channels are sent to the IN + end of an amplifier; the FPGA transmits the bias analog signal to the IN-end of the amplifier; a signal source and a bias analog signal are converted into differential signals, the differential signals are sent to an analog switch, and an FPGA configures a channel switching strategy and a measurement scheme of an ADC chip; the ADC performs analog-to-digital conversion on the differential signal and sends an obtained digital signal to the FPGA; the clock signal source provides a system clock and an equipment clock for the FPGA and the ADC; a multipurpose digital timing and triggering signal is connected with the analog front-end board card, and a generated synchronous sampling signal is sent to the FPGA; the FPGA synchronously acquires the voltage, current and power of alternating current and direct current in real time through the three-phase voltage and current acquisition unit; and sending the digital signal, the time node of the current sampling data and the temperature drift data to a data receiving end to complete multichannel ultra-wide frequency domain signal acquisition. The problem of measurement deviation caused by inconsistent gain of two channels of the module is solved, and the measurement precision is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic measurement, and in particular to a multi-channel ultra-wide frequency domain signal acquisition method and device. Background Art

[0002] According to the metrology law and various management standards, current transformers, a type of mandatory measuring instrument, must undergo periodic verification or calibration. A transformer calibrator is a specialized device used for verifying or calibrating current transformers. Traditional transformer calibrators operate by manually turning a knob and observing the AC null indicator pointer. When the pointer approaches zero, the current angle error and ratio error are recorded. Alternatively, software can be used to control the voltage divider to achieve automatic zeroing and calibration. However, both methods currently suffer from errors introduced by different channel circuits (these two errors are the difference in the fixed gain error of the channels and the phase difference between the channels, which are additionally calculated into the transformer error measurement results). In this context, dual-channel switching measurement technology is being used to address measurement deviations caused by inconsistent dual-channel gain and improve measurement accuracy. To complement this dual-channel switching measurement technology, a multi-channel, ultra-wideband, high-speed, and high-precision acquisition method and device is urgently needed. This method can collect data from dual-channel switching measurements or other voltage and current analog front-end boards, and transmit it to software for analysis (including the precise time point of the current data point, temperature drift, and frequency error). Summary of the Invention

[0003] In order to solve the above technical problems, the present invention provides a multi-channel ultra-wideband signal acquisition method and device, comprising:

[0004] The signal sources of multiple channels are respectively sent to the IN+ terminal of the corresponding high-speed fully differential amplifier; the bias digital signal is transmitted to the high-precision DAC through the FPGA, and the bias digital signal is converted into a bias analog signal by the high-precision DAC, and the bias analog signal is transmitted to the IN- terminal of the high-speed fully differential amplifier;

[0005] The signal source and bias analog signal are converted into differential signals, and the differential signals are sent to a fully differential digital gain amplifier, where the FPGA adjusts the gain ratio. The differential signals are then sent to a high-speed analog switch, where the FPGA configures the channel switching strategy and the measurement scheme of the ADC chip. The ADC chip performs analog-to-digital conversion on the input differential signals and sends the obtained digital signals to the FPGA.

[0006] The clock signal source provides system clock and device clock for FPGA and ADC chip;

[0007] Multi-purpose digital timing and trigger signals are connected to the analog front-end card for channel switching. The synchronous sampling signals generated by the analog front-end card are sent to the FPGA.

[0008] The FPGA obtains the current sampling environment temperature from the temperature sensor through I2C / SPI communication for temperature drift compensation. The FPGA obtains the time node of the current sampling data from the RTC clock chip through I2C communication. The FPGA is connected to the Beidou chip through UART communication, and the Beidou chip corrects the error of the RTC clock chip. The FPGA is connected to the three-phase voltage and current acquisition unit through SPI communication, and the three-phase voltage and current acquisition unit collects the AC and DC voltage, current and power in real time synchronously. The FPGA sends the digital signal, the time node of the current sampling data and the temperature drift data to the data receiving end through the GPIB / PCI data transmission module, completing multi-channel ultra-wide frequency domain signal acquisition.

[0009] Furthermore, it also includes: the data receiving end configures the acquisition board through RS485 communication mode, and the IO is used for online detection of the acquisition board.

[0010] Furthermore, the signal sources of multiple channels are respectively sent to the IN+ terminals of the corresponding high-speed fully differential amplifiers, including:

[0011] The signal sources of multiple channels are sent to the IN+ end of the high-speed fully differential amplifier through transient voltage suppression diodes TVS and surge protection.

[0012] Furthermore, the bias analog signal is transmitted to the IN- terminal of the high-speed fully differential amplifier, including:

[0013] The biased analog signal is amplified by a high-precision amplifier, sent to a precision buffer, and then transmitted to the IN- terminal of a high-speed fully differential amplifier.

[0014] Furthermore, after the step of adjusting the gain ratio by the FPGA, the method further includes:

[0015] The differential signal is filtered by an anti-aliasing filter, and the filtered differential signal is sent to a high-speed analog switch.

[0016] Furthermore, the clock signal source provides system clock and device clock for the FPGA and ADC chip, including:

[0017] The clock signal source is frequency modulated once through the PLL clock regulator and divided into three outputs, namely;

[0018] Output clock signal to external through high-speed analog switch;

[0019] Provide system clock and device clock to FPGA;

[0020] The PLLL clock regulator performs secondary frequency modulation to increase the clock signal frequency, which is used to provide the system clock and device clock for the ADC chip.

[0021] Furthermore, the multi-purpose digital timing and trigger signals are connected to the analog front-end card for channel switching, and the synchronous sampling signals generated by the analog front-end card are sent to the FPGA, including:

[0022] The DIN connector is connected to the FPGA through an isolator for multi-purpose digital timing and trigger signals. When the 4-channel input interface is fully loaded, it can achieve a maximum input measurement channel of 1:1*(4:1*4)=16 channels when combined with the analog front-end card with 4:1*4 channel switching.

[0023] When using a dual-channel switching acquisition board, the synchronous sampling signal generated by the dual-channel switching acquisition board is obtained by the Trig port and sent to the FPGA for corresponding data acquisition processing.

[0024] Furthermore, the FPGA is connected to the BeiDou chip via UART communication, and the BeiDou chip corrects the error of the RTC clock chip, including:

[0025] The FPGA communicates with the Beidou chip via the UART serial port. The Beidou chip obtains timing information from the Beidou satellite constellation and the ground satellite station, and corrects errors in the RTC clock chip and frequency synthesizer.

[0026] Furthermore, the FPGA is connected to the three-phase voltage and current acquisition unit via SPI communication, and the three-phase voltage and current acquisition unit performs real-time synchronous acquisition of AC and DC voltage, current, and power, including:

[0027] The isolated AC / DC sensors in the three-phase voltage and current acquisition unit convert the analog signals of AC / DC voltage, current and power into digital signals. The SPI bus sends the digital signals converted by the isolated AC / DC sensors to the FPGA, completing the real-time synchronous acquisition of AC / DC voltage, current and power.

[0028] Furthermore, the channel switching strategy includes:

[0029] When the analog switch is in use, when the control terminal is high, the switch is turned on;

[0030] When the control terminal is low, the switch is turned off and the errors caused by the gain and bias of the front end are offset by switching through the first-level channel.

[0031] Secondary channel switching selects the optimal ADC chip for measurement based on the current measured signal source. Sampling stops after the set acquisition time and a square wave pulse signal is used as the switching control signal of the analog switch. The rising positive signal of the square wave serves as the switch home signal and the acquisition start signal of the digitizer, and the falling negative signal of the square wave serves as the switching signal of the switch. By setting the acquisition time, the acquisition is completed before the switch switches.

[0032] The present invention provides a multi-channel, ultra-wideband signal acquisition method and device. This method addresses the errors introduced by different channel circuits in current transformer calibration measurements (these two errors are the difference in fixed gain errors of the channels and the phase difference between the channels, which are additionally calculated into the transformer error measurement results). This method solves the measurement deviation caused by inconsistent dual-channel gain in the module, improving measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a block diagram of a multi-channel, ultra-wide frequency domain, high-speed, and high-precision acquisition system according to an embodiment of the present invention;

[0034] Figure 2 This is a block diagram of the principle of multi-channel ultra-wide frequency domain high-speed and high-precision acquisition involved in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the configuration and detection of the acquisition board involved in the embodiment of the present invention;

[0036] Figure 4 Schematic diagram of A / B / C / D signal source processing according to an embodiment of the present invention;

[0037] Figure 5 Schematic diagram of the channel switching strategy and different ADC chip measurement solutions involved in the embodiment of the present invention;

[0038] Figure 6 Schematic diagram of a clock source according to an embodiment of the present invention;

[0039] Figure 7 is a partial schematic diagram of a multi-purpose digital timing and trigger signal involved in an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the temperature, time-frequency calibration, external triggering, and three-phase voltage and current acquisition interfaces involved in an embodiment of the present invention;

[0041] Figure 9 This is a schematic diagram of the principle of a three-phase voltage and current acquisition unit involved in an embodiment of the present invention;

[0042] Figure 10 The figure is a schematic diagram showing the principle of an analog front-end card with 4:1*4 channel switching according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following description sets forth numerous specific details to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific implementations disclosed below.

[0044] Example 1

[0045] To achieve the above objectives, the present invention provides a multi-channel ultra-wideband signal acquisition method and device, the system block diagram of which is as follows: Figure 1 As shown, the following steps are included:

[0046] In step S101, the signal sources of multiple channels are respectively sent to the IN+ terminal of the corresponding high-speed fully differential amplifier; the bias digital signal is sent to the high-precision DAC through the FPGA, and the bias digital signal is converted into a bias analog signal through the high-precision DAC, and the bias analog signal is transmitted to the IN- terminal of the high-speed fully differential amplifier.

[0047] The present invention proposes a multi-channel ultra-wideband signal acquisition method. It can be used to acquire dual-channel switching boards or Figure 1 The data of the 4:1*4 channel switching analog front-end board shown is sent to a data receiving end, which is generally a PC installed with software for analyzing the final collected signal. Beidou timing can calibrate clock frequency errors generated during long-term operation. The addition of a temperature sensor further monitors and optimizes the impact of temperature drift. It also supports converting wide-band single-ended / differential signal inputs to fully differential high-speed, high-resolution, and high-precision time-sharing / synchronous measurements. Adjustable offset and gain extend the dynamic range and flexibility of supported input signals. It also features a frequency generator to provide the clock signal source required for dual-channel switching measurements. It allows custom frequency adjustment and supports multiple clock source outputs, with a maximum output frequency of 15 GHz. When the maximum input channel interface is fully loaded with four channels, the 4:1*4 channel switching analog front-end board and multi-purpose digital timing and trigger signals can achieve a maximum input measurement channel ratio of 1:1*(4:1*4)=16. It also supports real-time, synchronous acquisition of integrated three-phase AC and DC voltage, current, and power with isolation technology. Each channel interface can be connected for AC or DC measurement, eliminating the need for separate AC and DC measurements, further reducing PCB area and cost.

[0048] Basic principles such as Figure 2As shown in the figure, the input signals of the A / B / C / D channels are converted through full differential conversion and gain and offset adjustment to ensure that the differential signal meets the measurement range of the back-end ADC chip. The FPGA then selects the ADC chip with the best signal to be measured according to the requirements for analog-to-digital conversion and converts it into a digital signal. When measuring with a single ADC chip at a 1MSPS sampling rate and a 5V reference voltage, the resolution can reach 32 bits, the 1LSB effective value can reach 2.3nV, the linearity error is 0.1ppm, and the temperature drift is 0.05ppm, when the dual-channel ADC chip switching measurement function is turned on, the accuracy and stability of the measurement signal can be further improved. The ADC sampling rate supports up to 10GSPS and supports internal and external clock sources. When the external clock source is inserted, the external clock source works and the internal clock source stops working. Conversely, the internal clock source works and the external clock source stops working. The clock source provides clock signals for the high-speed ADC chip and FPGA. At the same time, the FPGA controls the clock source frequency and the switch of the external output clock source, such as providing a clock source signal to the external dual-channel switching analog front end for channel switching; when the input clock source passes through the PLL The clock regulator adjusts the signal once through the FPGA and then sends it to the PLL frequency synthesizer for secondary adjustment. The clock source provides clock signals for the high-speed ADC chip and FPGA. Its PLL frequency synthesizer can output a clock source signal with a maximum frequency of 15GHz. Trig is an external trigger synchronous sampling signal used to sense the real-time channel switching status of the external dual-channel switching analog front end. At the same time, the temperature sensor monitors the current sampling environment temperature in real time, and the RTC chip records the time node of the current sampling data. Due to long-term continuous operation, time errors are inevitable in the RTC clock chip and frequency synthesizer. In order to reduce the error coefficient, at this time, the Beidou chip can obtain timing through the Beidou satellite group and the ground satellite station, and correct the errors in the RTC clock chip and frequency synthesizer. The timing accuracy is 20pps; the measured signal is converted into a digital signal through the ADC analog-to-digital conversion, and then sent to the FPGA through SPI, JESD204B / JESD204C, and SYNC communication methods. Finally, the FPGA provides the converted digital signal, the time node of the current sampling data, and the temperature drift data to the PC through the GPIB / PCI data transmission module, and the PC software completes the data processing such as the ratio and angle difference calculation of the input signal. The RS485 interface is used for PC software configuration of the acquisition board, and the IO interface is used for online board testing. When the 4-channel input interface is fully loaded, the analog front-end board with 4:1*4 channel switching and multi-purpose digital timing and trigger signals can achieve a maximum input measurement channel ratio of 1:1*(4:1*4) = 16 channels. It also supports integrated three-phase AC and DC voltage, current, and power real-time synchronous acquisition with isolation technology. Each channel interface has AC or DC access measurement, eliminating the need for separate AC and DC measurements, further reducing PCB area and cost. Voltage management provides reliable power supply for the entire system.

[0049] First, the signal sources of multiple channels are sent to the IN+ end of the high-speed fully differential amplifier through transient voltage suppression diodes (TVS) and surge protection.

[0050] The FPGA adjusts the appropriate bias digital signal and sends it to the high-precision DAC. The high-precision DAC converts the bias digital signal into a bias analog signal, amplifies the bias analog signal through a high-precision amplifier, and sends it to a precision buffer, which then transmits it to the IN-terminal of the high-speed fully differential amplifier.

[0051] In step S102, the signal source and bias analog signal are converted into differential signals, and the differential signals are sent to a fully differential digital gain amplifier, where the FPGA adjusts the gain ratio. The differential signals are then sent to a high-speed analog switch, where the FPGA configures the channel switching strategy and the measurement scheme of the ADC chip. The ADC chip performs analog-to-digital conversion on the input differential signals and sends the obtained digital signals to the FPGA.

[0052] The FPGA adjusts the gain ratio to make the differential signal conform to the measurement range of the high-precision ADC chip. The differential signal is then filtered by an anti-aliasing filter and sent to a high-speed analog switch.

[0053] In step S103 , the clock signal source provides the system clock and the device clock to the FPGA and the ADC chip.

[0054] The clock signal source undergoes a primary frequency modulation through the PLL clock regulator and is divided into three output paths: outputting the clock signal externally through a high-speed analog switch; providing the system clock and device clock to the FPGA; and undergoing a secondary frequency modulation through the PLLL clock regulator to increase the clock signal frequency, which is used to provide the system clock and device clock to the ADC chip.

[0055] Step S104: The multi-purpose digital timing and trigger signal is connected to the analog front-end card of the channel switch, and the synchronous sampling signal generated by the analog front-end card is sent to the FPGA.

[0056] The DIN connector is connected to the FPGA through an isolator for multi-purpose digital timing and trigger signals. When the 4-channel input interface is fully loaded, it can achieve a maximum input measurement channel of 1:1*(4:1*4)=16 channels in conjunction with the analog front-end card with 4:1*4 channel switching. When using a dual-channel switching acquisition board, the synchronous sampling signal generated by the dual-channel switching acquisition board is obtained by the Trig port and sent to the FPGA for corresponding data acquisition and processing.

[0057] In step S105, the FPGA obtains the current sampling environment temperature from the temperature sensor through the I2C / SPI communication mode for temperature drift compensation; the FPGA obtains the time node of the current sampling data from the RTC clock chip through the I2C communication mode; the FPGA is connected to the Beidou chip through the UART communication mode, and the error of the RTC clock chip is corrected by the Beidou chip; the FPGA is connected to the three-phase voltage and current acquisition unit through the SPI communication mode, and the AC and DC voltage, current and power are synchronously acquired in real time through the three-phase voltage and current acquisition unit; the FPGA sends the digital signal, the time node of the current sampling data and the temperature drift data to the data receiving end through the GPIB / PCI data transmission module, completing the multi-channel ultra-wide frequency domain signal acquisition.

[0058] The FPGA communicates with the Beidou chip via the UART serial port. The Beidou chip obtains timing information from the Beidou satellite constellation and the ground satellite station, and corrects errors in the RTC clock chip and frequency synthesizer.

[0059] The isolated AC / DC sensors in the three-phase voltage and current acquisition unit convert the analog signals of AC / DC voltage, current and power into digital signals. The SPI bus sends the digital signals converted by the isolated AC / DC sensors to the FPGA, completing the real-time synchronous acquisition of AC / DC voltage, current and power.

[0060] The channel switching strategy includes: when the analog switch is in use, when the control end is at a high level, the switch is turned on; when the control end is at a low level, the switch is turned off. Through the first-level channel switching, the errors caused by the gain and bias of the front end are offset. The second-level channel switching selects the optimal ADC chip for measurement based on the current measured signal source, stops sampling after a set acquisition time, uses a square wave pulse signal as the switching control signal of the analog switch, and the rising positive signal of the square wave serves as the switch home signal and the acquisition start signal of the digitizer. The falling negative signal of the square wave serves as the switch switching signal. By setting the acquisition time, the acquisition is completed before the switch switches.

[0061] Example 2

[0062] The present invention provides a multi-channel ultra-wideband signal acquisition method and device, and the specific working steps are as follows:

[0063] Step 1: PC software configures the acquisition board through RS485 communication mode. IO is used for online detection of the board. Figure 3 As shown;

[0064] Step 2: Input the A / B / C / D channel signal source, first pass through the TVS and surge protection, and then send it to the IN+ of the high-precision fully differential amplifier. The TVS and surge protection are mainly used to prevent the abnormal input signal from causing damage to the subsequent circuit. Figure 4 As shown;

[0065] Step 3: At this point, the input A / B / C / D channel signal source is sent to the IN+ terminal of the high-speed fully differential amplifier. Figure 4 As shown;

[0066] Step 4: At the same time, the FPGA adjusts the appropriate bias digital signal to the high-precision DAC (digital-to-analog converter), and converts the bias digital signal into a bias analog signal through analog-to-digital conversion. Figure 4 As shown;

[0067] Step 5: The biased analog signal is amplified by a high-precision amplifier and sent to a precision buffer, which then transmits it to the IN-terminal of a high-speed fully differential amplifier. Figure 4 As shown;

[0068] Step 6: Then, the input A / B / C / D channel signal source and the bias signal source are converted into differential signals and sent to the fully differential digital gain amplifier. The FPGA adjusts the gain ratio so that the differential signal meets the measurement range of the back-end ADC chip. Figure 4 As shown;

[0069] Step 7: The anti-aliasing filter filters the differential signal. Figure 4 As shown;

[0070] Step 8: The filtered differential signal is then fed into a high-speed analog switch. The FPGA configures the channel switching strategy and the measurement solution for which ADC chip to use. Figure 5 As shown;

[0071] Step 9: After the ADC chip performs analog-to-digital conversion on the input differential signal, it is sent to the FPGA via SPI, JESD204B / JESD204C, or SYNC communication. Figure 5 As shown;

[0072] Step 10: The 10MHz crystal oscillator is the internal clock source signal, and the 10MHz input is the external clock source signal. The internal / external clock source signal is selected through a high-speed precision analog switch. When the external clock source is inserted, the external clock source works and the internal clock source stops working. Conversely, the internal clock source works and the external clock source stops working. At the same time, the clock source signal selection status is notified to the FPGA, see Figure 6 As shown;

[0073] Step 11: The 10MHz clock source signal currently in use is frequency modulated once through the PLL clock regulator, see Figure 6 As shown, it is divided into three outputs, namely:

[0074] ① Output the clock source signal to the outside through a high-speed analog switch (clock output switch);

[0075] ② Provide system clock and device clock to FPGA;

[0076] ③ Perform secondary frequency modulation through the PLL frequency synthesizer to increase the clock signal frequency, which is used to provide system clock and device clock for the high-speed ADC chip.

[0077] Step 12: The 9-pin miniature circular DIN connector is connected to the FPGA through an isolator for multi-purpose digital timing and trigger signals. When the 4-channel input interface is fully loaded, the analog front-end card with 4:1*4 channel switching can achieve a maximum input measurement channel of 1:1*(4:1*4)=16 channels. Figure 7 As shown;

[0078] Step 13: When using a dual-channel switching acquisition board, the synchronous sampling signal generated by the board is obtained by the Trig port and sent to the FPGA for corresponding data acquisition processing. Figure 8 As shown;

[0079] Step 14: FPGA obtains the current sampled ambient temperature from the temperature sensor through I2C / SPI communication for temperature drift compensation. Figure 8 As shown;

[0080] Step 15: FPGA obtains the time node of the current sampling data from the RTC clock chip through I2C communication for algorithm optimization. Figure 8 As shown;

[0081] Step 16: FPGA communicates with BeiDou chip via UART communication. BeiDou chip can obtain timing from BeiDou satellite constellation and ground satellite station, and correct the errors in RTC clock chip and frequency synthesizer. The timing accuracy is 20pps. Figure 8 As shown;

[0082] Step 17: FPGA communicates with the three-phase voltage and current acquisition unit via SPI communication. Figure 8 As shown in the figure, in the three-phase voltage and current acquisition unit, the isolated AC / DC sensor converts the analog signals of AC / DC voltage, current and power into digital signals, and then the SPI bus transmits the digital signals converted by the isolated AC / DC sensor to the FPGA, completing the real-time synchronous acquisition of AC / DC voltage, current and power. Figure 9 As shown;

[0083] Step 18: Finally, the FPGA transmits the converted digital signal, the time node of the current sampling data, and the temperature drift data of the entire system to the PC through the GPIB / PCI data transmission module. The PC software completes data processing tasks such as the ratio and angular difference calculation of the input signal.

[0084] The specific channel switching strategy is as follows:

[0085] When the analog switch is in use, when the control end is high, the switch is turned on; when the control end is low, the switch is turned off. Through the first-level channel switching, the errors caused by the front-end gain and bias can be offset each other. The second-level channel switching can select the optimal ADC chip solution for measurement based on the current measured signal source. The sampling is stopped after the set acquisition time. The square wave pulse signal can be used as the switching control signal of the analog switch. The rising positive signal of the square wave is used as the switch home signal and the acquisition start signal of the digitizer. The falling negative signal of the square wave is used as the switching signal of the switch. The acquisition time is set by the application software to complete the acquisition before the switch is switched.

[0086] The present invention provides a multi-channel ultra-wide frequency domain signal acquisition method and device, which solves the errors caused by different channel circuits in the current mutual inductor calibration measurement (these two errors are the difference in the fixed gain error of the channel and the phase difference between the channels, which will be additionally calculated into the error measurement result of the mutual inductor). It solves the measurement deviation caused by the inconsistent gain of the dual channels of the module and improves the measurement accuracy. It can be used to collect data of dual-channel switching measurement and send it to PC software for analysis (including the precise time node of the current data point acquisition, temperature drift and frequency error). Through Beidou time service, the clock frequency error generated during long-term operation can be calibrated. The addition of temperature sensor can further monitor and optimize the impact of temperature drift, and supports wide-frequency domain single-ended / differential signal input to fully differential high-speed, high-resolution, high-precision time-sharing / synchronous measurement. The adjustable bias and gain make the dynamic range of the input signal it supports wider and more flexible. It also has a frequency generator function to meet the clock requirements of dual-channel switching measurement. The signal source can customize the frequency and support more clock source outputs, with a maximum output frequency of up to 15GHz. When the 4-channel input interface is fully loaded, the analog front-end board with 4:1*4 channel switching and multi-purpose digital timing and trigger signals can achieve a maximum input measurement channel of 1:1*(4:1*4)=16 channels of acquisition. At the same time, it supports integrated three-phase AC and DC voltage, current and power real-time synchronous acquisition with isolation technology. Each channel interface has AC or DC access measurement, eliminating the need for separate AC and DC measurements, further reducing PCB area and cost. It can also be used for research and analysis of switching measurements of different ADC chip solutions for the same signal source.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modifications or equivalents that do not depart from the spirit and scope of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A multi-channel ultra-wideband signal acquisition method and device, characterized in that: include: Send the signal sources of multiple channels to the IN+ terminals of the corresponding high-speed fully differential amplifiers respectively; The bias digital signal is transmitted to a high-precision DAC through the FPGA, converted into a bias analog signal through the high-precision DAC, and then transmitted to the IN- terminal of the high-speed fully differential amplifier; Converting the signal source and the bias analog signal into a differential signal, sending the differential signal to a fully differential digital gain amplifier, and adjusting the gain ratio by the FPGA; The differential signal is then fed into a high-speed analog switch, where the FPGA configures the channel switching strategy and the ADC chip's measurement scheme. The ADC chip performs analog-to-digital conversion on the input differential signal and feeds the resulting digital signal into the FPGA. The clock signal source provides system clock and device clock for FPGA and ADC chip; Multi-purpose digital timing and trigger signals are connected to the analog front-end card for channel switching. The synchronous sampling signals generated by the analog front-end card are sent to the FPGA. The FPGA obtains the current sampling environment temperature from the temperature sensor through I2C / SPI communication for temperature drift compensation. The FPGA obtains the time node of the current sampling data from the RTC clock chip through I2C communication. The FPGA is connected to the Beidou chip through UART communication, and the Beidou chip corrects the error of the RTC clock chip. The FPGA is connected to the three-phase voltage and current acquisition unit through SPI communication, and the three-phase voltage and current acquisition unit collects the AC and DC voltage, current and power in real time synchronously. The FPGA sends the digital signal, the time node of the current sampling data and the temperature drift data to the data receiving end through the GPIB / PCI data transmission module, completing multi-channel ultra-wide frequency domain signal acquisition.

2. The method according to claim 1, characterized in that Also includes: The data receiving end configures the acquisition board through RS485 communication, and IO is used for online detection of the acquisition board.

3. The method according to claim 1, characterized in that Send the signal sources of multiple channels to the IN+ terminals of the corresponding high-speed fully differential amplifiers, including: The signal sources of multiple channels are sent to the IN+ end of the high-speed fully differential amplifier through transient voltage suppression diodes TVS and surge protection.

4. The method according to claim 1, wherein Delivers biased analog signals to the IN- terminal of a high-speed fully differential amplifier, including: The biased analog signal is amplified by a high-precision amplifier, sent to a precision buffer, and then transmitted to the IN- terminal of a high-speed fully differential amplifier.

5. The method according to claim 1, wherein After the step of adjusting the gain ratio by the FPGA, the following steps are also included: The differential signal is filtered by an anti-aliasing filter, and the filtered differential signal is sent to a high-speed analog switch.

6. The method according to claim 1, wherein The clock signal source provides the system clock and device clock for the FPGA and ADC chip, including: The clock signal source is frequency modulated once through the PLL clock regulator and divided into three outputs, namely; Output clock signal to external through high-speed analog switch; Provide system clock and device clock to FPGA; The PLLL clock regulator performs secondary frequency modulation to increase the clock signal frequency, which is used to provide the system clock and device clock for the ADC chip.

7. The method according to claim 1, characterized in that Multipurpose digital timing and trigger signals are connected to the analog front-end card for channel switching. The synchronous sampling signals generated by the analog front-end card are sent to the FPGA, including: The DIN connector is connected to the FPGA through an isolator for multi-purpose digital timing and trigger signals. When the 4-channel input interface is fully loaded, it can achieve a maximum input measurement channel of 1:1*(4:1*4)=16 channels when combined with the analog front-end card with 4:1*4 channel switching. When using a dual-channel switching acquisition board, the synchronous sampling signal generated by the dual-channel switching acquisition board is obtained by the Trig port and sent to the FPGA for corresponding data acquisition processing.

8. The method according to claim 1, characterized in that The FPGA is connected to the BeiDou chip through UART communication, and the BeiDou chip corrects the error of the RTC clock chip, including: The FPGA communicates with the Beidou chip via the UART serial port. The Beidou chip obtains timing information from the Beidou satellite constellation and the ground satellite station, and corrects errors in the RTC clock chip and frequency synthesizer.

9. The method according to claim 1, characterized in that The FPGA is connected to the three-phase voltage and current acquisition unit via SPI communication. The three-phase voltage and current acquisition unit collects the AC and DC voltage, current, and power in real time and synchronously, including: The isolated AC / DC sensors in the three-phase voltage and current acquisition unit convert the analog signals of AC / DC voltage, current and power into digital signals. The SPI bus sends the digital signals converted by the isolated AC / DC sensors to the FPGA, completing the real-time synchronous acquisition of AC / DC voltage, current and power.

10. The method according to claim 1, characterized in that Channel switching strategy, including: When the analog switch is in use, when the control terminal is high, the switch is turned on; When the control terminal is low, the switch is turned off and the errors caused by the gain and bias of the front end are offset by switching through the first-level channel. Secondary channel switching selects the optimal ADC chip for measurement based on the current measured signal source. Sampling stops after the set acquisition time and a square wave pulse signal is used as the switching control signal of the analog switch. The rising positive signal of the square wave serves as the switch home signal and the acquisition start signal of the digitizer, and the falling negative signal of the square wave serves as the switching signal of the switch. By setting the acquisition time, the acquisition is completed before the switch switches.

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