Single event resistant high electron mobility transistor

Abstract

The invention discloses a single-particle-resistant high-electron-mobility transistor which comprises a substrate layer, a buffer layer, a channel layer, a barrier layer and a gate structure layer which are arranged in a stacked mode in the second direction, and the surface, away from the buffer layer, of the channel layer is further provided with a first electrode structure and a second electrode structure. The first electrode structure and the second electrode structure are connected to the two sides of the barrier layer in the first direction respectively, and at least one buried layer is inserted into the buffer layer; wherein a polarization effect and two-dimensional electron gas can be generated between the buffer layer and the channel layer, and each buried layer is made of a p-type GaN material. According to the anti-single-particle high-electron-mobility transistor, the anti-single-particle capability of a device is improved under the condition that the original characteristics of the device are not changed.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a single-particle resistant high electron mobility transistor. Background Art

[0002] Among semiconductor power devices, GaN HEMTs (GaN High Electron Mobility Transistors) feature a wide bandgap, high 2DEG (Two Dimension Electron Gas) concentration, a high breakdown electric field, low power consumption, high reliability, and high electron mobility. However, in the radiation-rich environment of space, single particles in the radiation can introduce defects into GaN HEMT devices, causing performance degradation or even burnout. Consequently, GaN HEMTs have limited single-event immunity.

[0003] Currently, the common approach is to dope the GaN channel with Al to convert it into an AlGaN channel. However, the AlGaN channel can affect the conduction characteristics of the GaN HEMT device. Alternatively, a mismatch in lattice constants between the substrate and epitaxial layer can be used, but this mismatch is uncontrollable and can reduce device reliability. Therefore, how to improve the device's single event resistance without changing its original characteristics has become a problem that needs to be solved. Summary of the Invention

[0004] The embodiments of the present application provide a single-event-resistant high electron mobility transistor, which improves the single-event-resistant capability of the device without changing the original characteristics of the device.

[0005] An embodiment of the present application provides a single-particle resistant high electron mobility transistor, which includes a substrate layer, a buffer layer, a channel layer, a barrier layer and a gate structure layer stacked along a second direction, and a first electrode structure and a second electrode structure are further provided on the surface of the channel layer away from the buffer layer, the first electrode structure and the second electrode structure are respectively connected to the two sides of the barrier layer in the first direction, and at least one buried layer is inserted into the buffer layer; wherein a polarization effect can occur between the buffer layer and the channel layer and generate a two-dimensional electron gas, and each buried layer is made of p-type GaN material.

[0006] In the above single event resistant high electron mobility transistor, the number of layers of the at least one buried layer is 1 to 3.

[0007] In the above single-event resistant high electron mobility transistor, the extending width of the buried layer along the first direction is a first width L1, the extending width of the buffer layer along the first direction is a second width L2, and 1 / 3L2≤L1≤L2.

[0008] As described above, the single-particle resistant high electron mobility transistor has at least one buried layer having multiple layers, and the multiple buried layers are arranged in the buffer layer at intervals along the second direction; wherein the second direction is perpendicular to the first direction, and the second direction is the stacking direction of the high electron mobility transistor.

[0009] As shown in the above single-particle resistant high electron mobility transistor, the width of each buried layer in the first direction shows a decreasing trend from the channel layer to the substrate layer; the extension width of the buried layer close to the channel layer along the first direction is a third width L3, L3=L2; the extension width of the buried layer close to the substrate layer along the first direction is a fourth width L4, 1 / 3L2≤L4<L2.

[0010] In the above single event resistant high electron mobility transistor, the widths of the buried layers in the first direction are all set to be equal.

[0011] As described above, the single-particle resistant high electron mobility transistor includes a top buffer layer and a bottom buffer layer, and the top buffer layer and the bottom buffer layer are respectively arranged on both sides of at least one buried layer in the second direction, and the at least one buried layer has a total thickness D1 in the second direction, and the top buffer layer has a buffer thickness D2 in the second direction, D2≤D1≤6D2.

[0012] As shown above, the single-particle resistant high electron mobility transistor has multiple buried layers, and the multiple buried layers are spaced apart along the second direction. The buffer layer also includes at least one isolation buffer layer, and each isolation buffer layer is arranged between two adjacent buried layers. The thickness of each isolation buffer layer in the second direction is less than the buffer thickness D2 of the top buffer layer.

[0013] As described above, the single-particle resistant high electron mobility transistor further includes a passivation layer, which is arranged in the same layer as the gate structure layer and is arranged on both sides of the gate structure layer in the first direction, so that the gate structure layer is isolated from the first electrode structure and the second electrode structure.

[0014] As described above, the single-particle high electron mobility transistor comprises a gate structure and a cap layer structure stacked along the second direction, the cap layer structure is arranged on the surface of the barrier layer away from the channel layer, and the cap layer structure is made of p-type GaN material.

[0015] The embodiment of the present application includes a stacked substrate layer, a buffer layer, a channel layer, a barrier layer, and a gate structure layer. The surface of the channel layer away from the buffer layer is further provided with a first electrode structure and a second electrode structure. The first electrode structure and the second electrode structure are respectively connected to the two sides of the barrier layer in a first direction. A polarization effect can occur between the buffer layer and the channel layer and generate a two-dimensional electron gas. The channel layer can provide a conductive channel along the first direction for the two-dimensional electron gas, allowing electrons to flow in the conductive channel, thereby generating a current between the first electrode structure and the second electrode structure. The gate structure layer can control the on and off of the conductive channel, thereby controlling the on and off state of the transistor device as a whole. Inside the buffer layer, at least one buried layer is inserted, each buried layer is made of p-type GaN material. The at least one p-type GaN buried layer can concentrate some holes in the buffer layer below the buried layer, thereby increasing the extension depth of the hole barrier in the buffer layer, reducing the accumulation of holes at the bottom of the channel layer, and thereby increasing the single-particle burnout voltage. Therefore, the high electron mobility transistor of the present application improves the single event resistance of the device without changing the original characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is a schematic diagram of the overall structure of a single-particle resistant high electron mobility transistor according to an embodiment of the present application;

[0018] Figure 2 This is a schematic structural diagram of another single-event resistant high electron mobility transistor according to an embodiment of the present application;

[0019] Figure 3 This is a transient current diagram of a conventional high electron mobility transistor after irradiation;

[0020] Figure 4 This is a transient current diagram of the single-event resistant high electron mobility transistor after irradiation according to an embodiment of the present application;

[0021] Figures 5 to 10 Schematic diagram of each step in the method for manufacturing a single event resistant high electron mobility transistor according to an embodiment of the present application.

[0022] Description of Figure Numbers:

[0023] 1. Substrate layer; 2. Buffer layer; 21. Top buffer layer; 22. Bottom buffer layer; 23. Isolation buffer layer; 3. Channel layer; 4. Barrier layer; 5. Gate structure layer; 51. Gate structure; 52. Cap layer structure; 6. First electrode structure; 7. Second electrode structure; 8. Buried layer; 9. Passivation layer; 10. Field plate structure;

[0024] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0025] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0026] Space is a harsh radiation environment, primarily composed of single particles such as protons, electrons, and a small amount of heavy ions. Radiation can introduce defects into semiconductor devices, leading to performance degradation and even burnout. Extensive research has been conducted domestically and internationally on the single-event effects (SEBs) of P-GaN HEMT devices, with most results demonstrating that GaN power devices have a relatively weak SEE resistance and are susceptible to SEBs.

[0027] When a single-event effect occurs in a P-GaN HEMT device, heavy ions pass through the active region of the device, generating a large number of hole-electron pairs along the ion orbit. Since the mobility of electrons is greater than that of holes, the electrons are instantly absorbed by the drain, leaving excess holes in the GaN buffer layer of the P-GaN HEMT device. The holes will accumulate below the gate channel, which can reduce the potential barrier between the source and the channel, thereby allowing electrons to be injected into the drain through the channel, forming a large current and causing the device to burn out.

[0028] like Figure 1 and Figure 2 As shown, an embodiment of the present application provides a single-particle resistant high electron mobility transistor, which includes a stacked substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a gate structure layer 5. A first electrode structure 6 and a second electrode structure 7 are further provided on a surface of the channel layer 3 away from the buffer layer 2. The first electrode structure 6 and the second electrode structure 7 are respectively connected to two sides of the barrier layer 4 in a first direction X. At least one buried layer 8 is inserted into the buffer layer 2.

[0029] A polarization effect can occur between the buffer layer 2 and the channel layer 3 and generate a two-dimensional electron gas, and each buried layer 8 is made of p-type GaN material.

[0030] In specific implementation, the single-particle high electron mobility transistor of the embodiment of the present application includes a stacked substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4 and a gate structure layer 5. The surface of the channel layer 3 away from the buffer layer 2 is also provided with a first electrode structure 6 and a second electrode structure 7. The first electrode structure 6 and the second electrode structure 7 are respectively connected to the two sides of the barrier layer 4 in the first direction X. A polarization effect can occur between the buffer layer 2 and the channel layer 3 and generate a two-dimensional electron gas. The channel layer 3 can provide a conductive channel along the first direction X for the two-dimensional electron gas, so that electrons can flow in the conductive channel, thereby generating current between the first electrode structure 6 and the second electrode structure 7. The gate structure layer 5 can control the on and off of the conductive channel, thereby controlling the overall on and off state of the transistor device.

[0031] At least one buried layer 8 is inserted inside the buffer layer 2, and each buried layer 8 is made of p-type GaN material. When a single-particle effect occurs in the device, some holes can be concentrated in the buffer layer 2 below each buried layer 8, avoiding the concentration of all holes in the buffer layer 2 near the channel layer 3, thereby increasing the extension depth of the hole barrier in the buffer layer 2, that is, increasing the distribution height of the holes in the second direction Y, reducing the accumulation of holes at the bottom of the channel layer 3, and thus increasing the single-particle burnout voltage. Therefore, the high electron mobility transistor of the present application improves the device's ability to resist single-particle effects without changing the original characteristics of the device.

[0032] Please refer to Figure 3 and Figure 4 ,like Figure 3 As shown in the figure, in a conventional high electron mobility transistor device, when the drain voltage is at 330V, the gate current, source current and drain current (I G , I S with I D ) will increase sharply, and after a period of time, each current will return to its initial state. Therefore, the device will not suffer from single-event burnout at a voltage level of 330V; However, when the drain voltage is at 340V, the gate current, source current and drain current (I G , I S with I D ) will increase sharply, but after a period of time, each current does not return to its initial state. Therefore, at a voltage level of 340V, traditional high electron mobility transistor devices will experience single-particle burnout, and the device cannot return to normal working state.

[0033] like Figure 4As shown, in the single-particle resistant high electron mobility transistor of the embodiment of the present application, when the drain voltage is at 480V, the gate current, source current and drain current (I G , I S with I D ) will increase dramatically, and after a period of time, each current will return to its initial state. Therefore, at a voltage level of 480V, the single-event-resistant high electron mobility transistor device of the present application embodiment still does not experience single-event burnout. It is not until the drain voltage reaches 490V that the currents fail to return to their initial state after a period of single-event incidence, and single-event burnout can occur. Therefore, the single-event burnout voltage of the single-event-resistant high electron mobility transistor of the present application embodiment is 490V, and the single-event-resistant capability of the device is significantly improved.

[0034] Specifically, the buffer layer 2 and the barrier layer 4 are both made of AlGaN material, and the channel layer 3 is made of GaN material. A polarization effect can occur between the buffer layer 2 and the channel layer 3 and generate a two-dimensional electron gas.

[0035] Optionally, the channel layer 3 may also be made of AlGaN material, but the Al content therein is different from the Al content in the buffer layer 2 , so that a polarization effect can occur between the two and a two-dimensional electron gas can be generated.

[0036] like Figure 1 and Figure 2 As shown, in the single-particle resistant high electron mobility transistor of the embodiment of the present application, the number of layers of the at least one buried layer 8 is 1 to 3.

[0037] During specific implementation, the number of buried layers 8 is in the range of 1 to 3 layers, so that the saturation current of the device is within a reasonable range, thereby avoiding the situation where the saturation current is too low, and further avoiding the situation where the device current exceeds the threshold of the saturation current, resulting in device failure or performance degradation; and within this range of the number of layers, the breakdown voltage of the device is also improved, thereby achieving a balance between the breakdown voltage and the saturation current of the device, further improving the overall performance of the device.

[0038] In the single-particle resistant high electron mobility transistor of the embodiment of the present application, the extending width of the buried layer 8 along the first direction X is a first width L1, the extending width of the buffer layer 2 along the first direction X is a second width L2, and 1 / 3L2≤L1≤L2.

[0039] It should be noted that the first direction X is perpendicular to the second direction Y. Figure 1 The horizontal direction in the second direction Y is Figure 1 The vertical direction in the diagram is the stacking direction of the device layers.

[0040] During specific implementation, the first width L1 of the buried layer 8 and the second width L2 of the buffer layer 2 have a range relationship of 1 / 3L2≤L1≤L2, that is, the extension width of the buried layer 8 is at least one-third of the extension width of the buffer layer 2, so that the buried layer 8 has sufficient width to enable a sufficient number of holes to accumulate in the lower part of the buffer layer 2, thereby avoiding excessive holes from concentrating at the bottom of the channel layer 3, thereby ensuring that the device has a higher single-particle burnout voltage and the device's ability to resist single particles.

[0041] In the embodiment of the present application, the single-particle resistant high electron mobility transistor, wherein at least one buried layer 8 has multiple layers, and the multiple buried layers 8 are arranged in the buffer layer 2 at intervals along the second direction Y; wherein the second direction Y is perpendicular to the first direction X, and the second direction Y is the stacking direction of the high electron mobility transistor.

[0042] During specific implementation, multiple layers of buried layers 8 are arranged in the buffer layer 2 at intervals along the second direction Y, and partial buffer layers 2 are provided between each layer of buried layers 8. Therefore, when a single particle effect occurs in the device, the buffer layers 2 corresponding to the lower side of each layer of buried layer 8 can accommodate holes, thereby increasing the distribution height of the holes in the second direction Y, reducing the accumulation of holes at the bottom of the channel layer 3, increasing the single particle burnout voltage, and thereby improving the device's ability to resist single particles.

[0043] like Figure 1 As shown, the single-particle resistant high electron mobility transistor of the embodiment of the present application is shown, wherein the width of each buried layer 8 in the first direction X shows a decreasing trend from the channel layer 3 to the substrate layer 1; wherein the extension width of the buried layer 8 close to the channel layer 3 along the first direction X is a third width L3, L3=L2; the extension width of the buried layer 8 close to the substrate layer 1 along the first direction X is a fourth width L4, 1 / 3L2≤L4<L2.

[0044] In specific implementation, the width of each buried layer 8 in the first direction X tends to decrease from the channel layer 3 to the substrate layer 1, thereby forming a stepped multi-layer buried layer 8 structure, and the width of the buried layer 8 close to the side of the substrate layer 1 is the smallest. Such a shape setting can not only ensure that the holes have a sufficient distribution height in the second direction Y, but also reduce the impact of reducing the device saturation current due to the excessive overall volume of the buried layer 8.

[0045] Moreover, the buried layer 8 close to the channel layer 3 has the longest extension width along the first direction X, and its third width L3 is equal to the second width L2 of the buffer layer 2 along the first direction X. Such a setting ensures that the holes generated below this buried layer 8 can be completely located in the part of the buffer layer 2 on the lower side of the buried layer 8, thereby ensuring the stability of the extension depth of the holes in the buffer layer 2; and the extension width of the buried layer 8 close to the substrate layer 1 along the first direction X is the fourth width L4, and 1 / 3L2≤L4<L2. Such a setting makes this buried layer 8, that is, the extension width of the buried layer 8 at least one-third of the extension width of the buffer layer 2, so that the buried layer 8 closest to the substrate layer 1 also has sufficient width to gather a sufficient amount of holes in the lower part of the buffer layer 2, thereby avoiding too many holes from concentrating at the bottom of the channel layer 3, thereby ensuring that the device has a higher single-particle burnout voltage and the device's single-particle resistance.

[0046] Specifically, the first electrode structure 6 is the source, the second electrode structure 7 is the drain, and each buried layer 8 is arranged near the first electrode structure 6, and the projection of the bottommost buried layer 8 perpendicular to the second direction Y covers at least part of the first electrode structure 6 and at least part of the gate structure layer 5, thereby improving the electric field distribution between the source and the gate and enhancing the overall performance of the device.

[0047] like Figure 2 As shown, in another embodiment of the present application, the single event resistant high electron mobility transistor, wherein the widths of the buried layers 8 in the first direction X are all set to be equal.

[0048] In specific implementation, the widths of the buried layers 8 in the first direction X are equal, so that the number of holes in the buffer layer 2 under each buried layer 8 is close, thereby ensuring the uniformity of the hole distribution in the buffer layer 2 and avoiding excessive holes close to the channel layer 3, thereby ensuring that the device has a higher single-particle burnout voltage and further ensuring the device's ability to resist single-particle damage.

[0049] Specifically, the width of each buried layer 8 in the first direction X is equal to the second width L2 of the buffer layer 2, so that the holes on the lower side of each buried layer 8 are stably located inside the buffer layer 2 between the two buried layers 8, ensuring that the device has stable single-particle resistance.

[0050] Optionally, the width of each buried layer 8 in the first direction X is smaller than the second width L2 of the buffer layer 2, and the projections of each buried layer 8 on the channel layer 3 can be arranged to partially overlap. This arrangement can also prevent holes from transferring to the lower side of the channel layer 3, ensuring the device's single-event resistance. In addition, the relatively small width of each buried layer 8 can prevent the saturation current from being too low, thereby preventing device failure or performance degradation when the device current exceeds the saturation current threshold. Therefore, this structural arrangement ensures the overall performance of the device.

[0051] like Figure 1 and Figure 2 As shown, the single-particle resistant high electron mobility transistor of an embodiment of the present application, wherein the buffer layer 2 includes a top buffer layer 21 and a bottom buffer layer 22, the top buffer layer 21 and the bottom buffer layer 22 are respectively arranged on both sides of at least one buried layer 8 in the second direction Y, the at least one buried layer 8 has a total thickness D1 in the second direction Y, and the top buffer layer 21 has a buffer thickness D2 in the second direction Y, D2≤D1≤6D2.

[0052] In a specific implementation, the top buffer layer 21 is disposed within the buffer layer 2 in a region near the top, and the bottom buffer layer 22 is disposed within the buffer layer 2 in a region near the bottom. The total thickness D1 of the at least one buried layer 8 and the buffer thickness D2 of the top buffer layer 21 have a range relationship of D2≤D1≤6D2. Within this range, the total thickness of the buried layer 8 does not exceed six times the thickness of the top buffer layer 21. This thickness setting ensures that the total thickness of the buried layer 8 is not excessively large, thereby reducing the impact of the thickness of the buried layer 8 on the device saturation current, keeping the device saturation current within a reasonable range. Furthermore, the total thickness of the buried layer 8 is not less than the thickness of the top buffer layer 21, thereby ensuring that the buried layer 8 controls the position of holes, allowing holes to accumulate in the buffer layer 2 below each buried layer 8, thereby ensuring a high distribution height of holes in the second direction Y and ensuring the device's single-event resistance. Therefore, the relationship between D1 and D2 improves the overall performance of the device.

[0053] like Figure 1 and Figure 2 As shown, the single-particle resistant high electron mobility transistor of the embodiment of the present application is provided, wherein the number of buried layers 8 is multiple layers, the multiple layers of buried layers 8 are arranged at intervals along the second direction Y, and the buffer layer 2 also includes at least one isolation buffer layer 23, each isolation buffer layer 23 is arranged between two adjacent buried layers 8, and the thickness of each isolation buffer layer 23 in the second direction Y is less than the buffer thickness D2 of the top buffer layer 21.

[0054] In specific implementation, each isolation buffer layer 23 is arranged between two adjacent buried layers 8. When a single particle effect occurs in the device, the holes will gather in the isolation buffer layer 23 on the lower side of the buried layer 8 and in the bottom buffer layer 22 at the bottom, thereby increasing the extension depth of the holes in the buffer layer 2; the thickness of each isolation buffer layer 23 in the second direction Y is less than the buffer thickness D2 of the top buffer layer 21, which avoids the overall thickness of the device being too large, thereby ensuring the overall miniaturization design of the device while ensuring the device's ability to resist single particles.

[0055] The single-particle resistant high electron mobility transistor of the embodiment of the present application, wherein the high electron mobility transistor further includes a passivation layer 9, which is arranged in the same layer as the gate structure layer 5 and is arranged on both sides of the gate structure layer 5 in the first direction X, so that the gate structure layer 5 is isolated from the first electrode structure 6 and the second electrode structure 7.

[0056] In a specific implementation, the provision of the passivation layer 9 ensures that the gate structure layer 5 can be isolated from the first electrode structure 6 and the second electrode structure 7, thereby preventing the electrodes from being connected to each other and ensuring the conduction characteristics of the device.

[0057] like Figure 1 and Figure 2 As shown, the single-particle high electron mobility transistor of the embodiment of the present application, wherein the gate structure layer 5 includes a gate structure 51 and a cap layer structure 52 stacked along the second direction Y, the cap layer structure 52 is arranged on the surface of the barrier layer 4 away from the channel layer 3, and the cap layer structure 52 is made of p-type GaN material.

[0058] In a specific implementation, a cap layer structure 52 is provided between the gate structure 51 of the gate structure layer 5 and the barrier layer 4, so that the high electron mobility transistor can form a normally closed device. When a voltage is applied to the gate structure 51, the first electrode structure 6 and the second electrode structure 7 of the device are turned on, thereby realizing the switching effect of the device.

[0059] like Figure 1 and Figure 2 As shown, in an embodiment of the present application, the high electron mobility transistor further includes a field plate structure 10. The field plate structure 10 covers the surface of the gate structure layer 5 away from the barrier layer 4, and the field plate structure 10 extends from the gate structure layer 5 toward the second electrode structure 7 to cover a portion of the passivation layer 9. The first electrode structure 6 is the source electrode, and the second electrode structure 7 is the drain electrode. By providing the field plate structure 10 between the gate and the drain electrode, the electric field strength of the gate near the drain electrode can be effectively reduced, thereby increasing the breakdown voltage of the device. At the same time, the probability of electrons in the channel layer 3 being excited by the strong electric field into the surface state is reduced, thereby suppressing the current collapse of the device.

[0060] like Figures 5 to 10 As shown, the method for manufacturing the high electron mobility transistor of the embodiment of the present application is as follows:

[0061] like Figure 5 As shown, a buffer layer 2 and at least one buried layer 8, a channel layer 3, a barrier layer 4 and a cap layer structure 52 of a gate structure layer 5 are epitaxially grown on a Si substrate using metal organic chemical vapor deposition (MOCVD) technology;

[0062] like Figure 6As shown, the cap layer structure 52 is selectively etched in the first direction X by using inductively coupled plasma technology, and finally a cap layer structure 52 is formed near the middle in the first direction X;

[0063] like Figure 7 As shown, the inductively coupled plasma technology is used to selectively etch both sides of the barrier layer 4 until the channel layer 3 is exposed;

[0064] like Figure 8 As shown, electron beam evaporation technology is used on the surface of the channel layer 3 on both sides of the barrier layer 4 and the surface of the cap layer structure 52 to form the first electrode structure 6, the second electrode structure 7 and the gate structure 51;

[0065] like Figure 9 As shown, a passivation layer 9 is formed on the surface of the barrier layer 4 by using a low-pressure chemical deposition technique;

[0066] like Figure 10 As shown, the field plate structure 10 is formed on the surface of the gate structure 51 by using electron beam evaporation technology.

[0067] During the formation of the buffer layer 2 and at least one buried layer 8 within the buffer layer 2, it is necessary to sequentially form a bottom buffer layer 22, a buried layer 8, an isolation buffer layer 23, a buried layer 8, and a top buffer layer 21, wherein the buried layer 8 and the isolation buffer layer 23 are sequentially arranged in an overlapping manner. Furthermore, when the width of the buried layer 8 is smaller than the width of the buffer layer 2, it is necessary to etch the buried layer 8 in the first direction X. After etching, the buffer layer 2 is then grown on the surface of the buried layer 8 and on the surface of the bottom buffer layer 22 or the isolation buffer layer 23 corresponding to the etched position, thereby forming a stepped isolation buffer layer 23.

[0068] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0069] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A single-particle high electron mobility transistor, characterized in that: The invention comprises a stacked substrate layer (1), a buffer layer (2), a channel layer (3), a barrier layer (4), and a gate structure layer (5); a surface of the channel layer (3) away from the buffer layer (2) is further provided with a first electrode structure (6) and a second electrode structure (7); the first electrode structure (6) and the second electrode structure (7) are respectively connected to two sides of the barrier layer (4) in a first direction (X); and at least one buried layer (8) is inserted into the buffer layer (2); A polarization effect can occur between the buffer layer (2) and the channel layer (3) to generate a two-dimensional electron gas, and each buried layer (8) is made of p-type GaN material.

2. The single-event high electron mobility transistor according to claim 1, wherein: The number of layers of the at least one buried layer (8) is 1 to 3.

3. The single-event high electron mobility transistor according to claim 2, wherein: The extending width of the buried layer (8) along the first direction (X) is a first width L1, the extending width of the buffer layer (2) along the first direction (X) is a second width L2, and 1 / 3L2≤L1≤L2.

4. The single-event high electron mobility transistor according to claim 3, wherein: The at least one buried layer (8) has multiple layers, and the multiple buried layers (8) are arranged in the buffer layer (2) at intervals along the second direction (Y); The second direction (Y) is perpendicular to the first direction (X), and the second direction (Y) is the stacking direction of the high electron mobility transistor.

5. The single-event high electron mobility transistor according to claim 4, characterized in that: From the channel layer (3) to the substrate layer (1), the width of each buried layer (8) in the first direction (X) shows a decreasing trend; The buried layer (8) close to the channel layer (3) has an extension width along the first direction (X) of a third width L3, where L3=L2; and the buried layer (8) close to the substrate layer (1) has an extension width along the first direction (X) of a fourth width L4, where 1 / 3L2≤L4<L2.

6. The single-event high electron mobility transistor according to claim 4, wherein: The widths of the buried layers (8) in the first direction (X) are all set to be equal.

7. The single-event high electron mobility transistor according to claim 1, wherein: The buffer layer (2) comprises a top buffer layer (21) and a bottom buffer layer (22), wherein the top buffer layer (21) and the bottom buffer layer (22) are respectively arranged on both sides of the at least one buried layer (8) in the second direction (Y), the at least one buried layer (8) has a total thickness D1 in the second direction (Y), and the top buffer layer (21) has a buffer thickness D2 in the second direction (Y), where D2≤D1≤6D2.

8. The single-event high electron mobility transistor according to claim 7, wherein: The number of the buried layers (8) is multiple, and the multiple buried layers (8) are arranged at intervals along the second direction (Y). The buffer layer (2) further includes at least one isolation buffer layer (23), and each isolation buffer layer (23) is arranged between two adjacent layers of the buried layers (8), and the thickness of each isolation buffer layer (23) in the second direction (Y) is less than the buffer thickness D2 of the top buffer layer (21).

9. The single-event high electron mobility transistor according to claim 1, wherein: The high electron mobility transistor further comprises a passivation layer (9), the passivation layer (9) being arranged in the same layer as the gate structure layer (5) and being arranged on both sides of the gate structure layer (5) in the first direction (X), so that the gate structure layer (5) is isolated from the first electrode structure (6) and the second electrode structure (7).

10. The single-event high electron mobility transistor according to claim 9, wherein: The gate structure layer (5) comprises a gate structure (51) and a cap layer structure (52) stacked along a second direction (Y); the cap layer structure (52) is provided on a surface of the barrier layer (4) away from the channel layer (3); and the cap layer structure (52) is made of p-type GaN material.

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