Performance optimization method for high-density 3D NAND flash memory

Abstract

The invention discloses a performance optimization method for a high-density 3D NAND flash memory. The method comprises the following steps of: obtaining a writing request of a plurality of to-be-written data in a cache block and an old placement flash memory block; classifying the to-be-written data according to the writing request and the old placement position of each to-be-written data to obtain the type of each to-be-written data; and writing the to-be-written data into a new flash memory block according to the type of each to-be-written data. The performance optimization method has the advantages of being short in response time, long in service life and high in performance.

Description

Technical Field

[0001] The present invention relates to the field of solid-state hard disk storage technology, and more specifically, to a high-density 3D NAND flash memory performance optimization method. Background Art

[0002] With the rapid growth in data storage demand, NAND flash-based solid-state drives (SSDs) have become a mainstream storage device. To increase storage capacity, SSDs employ high-density memory cells such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), storing 2, 3, and 4 bits of data per cell, respectively. Simultaneously, NAND flash architecture has evolved from 2D to 3D, further improving storage density through stacking technologies (e.g., 176-layer). With increasing storage density, the voltage window of flash memory cells is split into more voltage states, resulting in a smaller read margin between adjacent voltage states. This makes flash memory cells more susceptible to read disturb, leading to voltage state drift and, in turn, increased bit error rates. To combat accumulated read disturb, read refresh operations (RROs) are triggered when a block reaches its read endurance threshold. However, RROs involve multiple read and write operations, increasing the SSD's response time and write amplification factor (WAF), thereby reducing SSD performance and lifespan.

[0003] Existing technologies use firmware-level mitigation, data management, and reprogramming to avoid read disturb. Firmware-level mitigation reduces voltage offsets caused by read disturb by modifying programming or reading modules, primarily by lowering the Vpass voltage and increasing the channel voltage. However, lowering the Vpass voltage (reducing the impact of read disturb by lowering the Vpass voltage) requires more precise programming techniques and may result in reduced write performance. Increasing the channel voltage (applying a high voltage to unselected strings to increase the channel voltage) results in higher power consumption and increased chip area. Data management extends the life of SSDs by balancing the read interference of blocks. It mainly includes three methods: read balancing, block density definition, and mixing user data and read refresh operation data. However, read balancing (increasing the read count of a block by using a small amount of hot read data to occupy a large number of free pages in the block) wastes a lot of storage space. Block density definition (increasing the read endurance threshold of 2D SSD blocks by defining block density through software) requires a large amount of cache space to identify hot read data and is not suitable for 3D SSDs. Mixing user data and read refresh operation data (mixing user write data with read refresh operation data to balance the read count of the block and reduce the triggering of read refresh operations) does not consider the read latency asymmetry of pages within a word line, and user cold write data may cause additional write amplification factors. Reprogramming aims to enable more programming operations before a block is erased. It primarily includes three methods: narrow programming range, write-once memory encoding, and voltage-level-constrained write-once memory encoding. However, narrow programming range (each programming operation uses only the highest narrow range to represent newly written data) is only suitable for 2DSLC SSDs. Write-once memory (WOM) encoding (which allows multiple reprogramming operations on the same storage cell, reducing the number of erase operations and extending SSD life) is not suitable for high-density flash memory. The reliability of reprogramming operations with voltage-level-constrained write-once memory (WOM-v) encoding is limited by background pattern dependency (BPD). In summary, existing approaches to addressing read disturb suffer from insufficient voltage window utilization, waste storage space, and are unsuitable for 3D flash memory.

[0004] Prior art discloses a method and device for improving solid-state hardware storage performance, relating to the field of solid-state drive (SSD) storage. The method includes recording the write time of each SSD (Solid State Drive) block when data to be read is written; upon receiving a read command from any SSD block, the data to be read is read using a corresponding offset voltage according to a correspondence between the storage time and the offset voltage. The correspondence between the storage time and the offset voltage is obtained by recording the offset voltage used to successfully read test data after the data has been stored in different SSD blocks for different periods of time. This method does not specifically address the problem of SSD read disturb. Summary of the Invention

[0005] The present invention addresses the shortcomings of existing SSDs, such as long response time, short lifespan, and poor performance, and provides a high-density 3D NAND flash memory performance optimization method. This performance optimization method has the characteristics of short response time, long lifespan, and strong performance.

[0006] The primary purpose of the present invention is to solve the above technical problems, and the technical solutions of the present invention are as follows:

[0007] A high-density 3D NAND flash memory performance optimization method, comprising:

[0008] S1: Obtain write requests for several data to be written in the cache block and the old placement flash memory block;

[0009] S2: classifying the data to be written according to the write request and the old placement location of each data to be written, and obtaining the type of each data to be written;

[0010] S3: Writing the data to be written into a new flash memory block according to the type of each data to be written.

[0011] Furthermore, in step S2, classifying the data to be written includes:

[0012] S201: Determine whether the write request for the data to be written is a read-refresh-write operation or a reclaim block migration operation; if so, the data type is cold-write-hot-read data or cold-write-cold-read data; if not, execute step S202;

[0013] S202: Determine whether the write request for the data to be written is an update operation; if so, execute step S203; if not, the data type is warm write data;

[0014] S203: Determine the old placement flash memory block of the data to be written; if the old placement flash memory block of the data to be written is a pre-filled balancing block or a non-pre-filled balancing block, the data type is warm write data; if the old placement flash memory block of the data to be written is a warm block, a hot block or a reprogramming block, the data type is hot write data.

[0015] Furthermore, the flash memory blocks in the 3D NAND are divided into hot blocks, warm blocks, pre-filled balancing blocks, non-pre-filled balancing blocks, and reprogramming blocks.

[0016] Furthermore, in step S3, the data to be written is written into a new flash memory block according to the type of the data to be written, including:

[0017] S301: Determine whether there is warm-written data in the cache; if so, store the warm-written data in the warm block and execute step S302; if not, directly execute step S302;

[0018] S302: Determine whether there is hot-write data in the cache; if so, execute step S303; if not, execute step S304;

[0019] S303: Determine whether there is cold write and hot read data in the cache; if so, store the hot write data and the cold write and hot read data in the reprogramming block and execute step S304; if not, store the hot write data in the hot block and execute step S304;

[0020] S304: Determine whether there is cold write hot read data or cold write cold read data in the cache; if so, execute step S305; if not, terminate the storage;

[0021] S305: Determine whether the pre-filled balancing block meets the preset data placement conditions; if so, store the cold write hot read data or the cold write cold read data in the pre-filled balancing block; if not, store the cold write hot read data or the cold write cold read data in a non-pre-filled balancing block.

[0022] Furthermore, each word line in the reprogramming block includes a preset high-latency page and a low-latency page; the hot write data is stored in the high-latency page, and the cold write and hot read data is stored in the low-latency page.

[0023] Furthermore, the method further includes: S4: performing a reprogramming operation on the data written into the reprogramming block; specifically including:

[0024] S30301: Selecting a first layer of a reprogramming block as a first reprogramming block layer; performing a conventional programming operation on the word lines of the first reprogramming block layer in ascending order;

[0025] S30302: Select the first word line of the first reprogramming block layer as the first word line;

[0026] S30303: Determine the validity of the data of the high-latency page; if the data is valid, execute step S30304; if the data is invalid, execute step S30305;

[0027] S30304: Store the data of the high-latency page as cold write and cold read data in the cache; and execute step S30305;

[0028] S30305: reprogramming the first word line;

[0029] S30306: using a word line at a position corresponding to the first word line in a next layer of the first reprogramming block layer as a second word line, and performing a normal programming operation on the second word line;

[0030] S30307: Select the next word line of the first reprogramming block layer as the new first word line; execute step S30303; until all word lines of the first reprogramming block layer are selected;

[0031] S30308: Select the next layer of the first reprogramming block layer as a new first reprogramming block layer, and execute step S30302 until the first reprogramming block layer becomes the last layer of the reprogramming block;

[0032] S30309: reprogramming the word lines of the first reprogramming block layer in ascending order.

[0033] Furthermore, the reprogramming operation of step S30305 includes:

[0034] S3030101: Encode the data in the first word line into five voltage states using the ISPP algorithm;

[0035] S3030102: Store the states of the five voltages in the first word line.

[0036] Furthermore, the conventional programming operation of step S30306 includes:

[0037] S3030201: Encode the data in the second word line into eight voltage states using the ISPP algorithm;

[0038] S3030202: Store the states of the eight voltages in the second word line.

[0039] Furthermore, the preset data placement condition includes: if the space occupied by the data type of cold write and hot read data in the pre-filled balancing block is less than half of the total space occupied by the pre-filled balancing block, and the space occupied by the data type of cold write and cold read data in the pre-filled balancing block is less than half of the total space occupied by the pre-filled balancing block, then allowing the cold write and hot read data or the cold write and cold read data to be stored; otherwise, not allowing the cold write and cold read data or the cold write and hot read data to be stored.

[0040] A high-density 3D NAND flash memory performance optimization system, comprising:

[0041] Cache read module: obtains write requests and old placement locations of several data to be written;

[0042] Data type classification module: classifies the data to be written according to the write request and the old placement location of each data to be written, and obtains each data type to be written;

[0043] Storage module: writes the data to be written into the hot block, warm block, pre-filled balancing block, non-pre-filled balancing block, and reprogramming block according to the type of the data to be written.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The present invention classifies the data to be written based on the write request and the old location of each data to be written, obtaining the type of each data to be written. The data to be written is then written to a hot block, a warm block, a pre-filled balancing block, a non-pre-filled balancing block, or a reprogramming block, depending on the data type. This reduces mixed data storage, lowers the triggering frequency of garbage collection and RROs, reduces write amplification factors, shortens response time, and improves SSD performance and lifespan, resulting in high-density 3D NAND flash memory with short response time, long life, and strong performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a flow chart of a high-density 3D NAND flash memory performance optimization method provided in Example 1.

[0047] Figure 2 A schematic diagram illustrating the principle of a high-density 3D NAND flash memory performance optimization method provided in Example 1.

[0048] Figure 3 This is a flowchart of data type classification provided in Example 1.

[0049] Figure 4 A schematic diagram of the principle of data type classification provided in Example 1.

[0050] Figure 5 This is a flowchart of storing multiple input data in the cache into corresponding storage blocks provided in Example 1.

[0051] Figure 6 This is a schematic diagram of the principle of storing multiple input data in the cache into corresponding storage blocks provided in Example 1.

[0052] Figure 7 This is a flow chart of the programming optimization method for the reprogramming block provided in Example 1.

[0053] Figure 8 This is a schematic diagram of the principle of the programming optimization method for the reprogramming block provided in Example 1.

[0054] Figure 9 A schematic diagram of the conventional programming and reprogramming sequence provided in Example 1.

[0055] Figure 10 Schematic diagram of conventional programming principles of the TLC flash memory architecture provided in Example 1.

[0056] Figure 11 Schematic diagram of the reprogramming principle of the TLC flash memory architecture provided in Example 1.

[0057] Figure 12 Schematic diagram of the reprogramming principle of the QLC flash memory architecture provided in Example 1.

[0058] Figure 13 This is a schematic diagram of the principle of repeated occupation of voltage states provided in Example 1.

[0059] Figure 14 This is a flowchart of the reprogramming operation provided in Example 1.

[0060] Figure 15 This is a schematic diagram of the principle of the read refresh operation provided in Example 1.

[0061] Figure 16 Flowchart of a conventional programming operation provided in Example 1.

[0062] Figure 17 A schematic diagram of the principle of a high-density 3D NAND flash memory performance optimization system provided in Example 1.

[0063] Figure 18 This is a graph of average read times under various loads provided in Example 1. DETAILED DESCRIPTION

[0064] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0065] In order to better illustrate this embodiment, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product size;

[0066] It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0067] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0068] Example 1

[0069] like Figure 1 、 Figure 2 As shown, a high-density 3D NAND flash memory performance optimization method includes:

[0070] S1: Obtain write requests for several data to be written in the cache block and the old placement flash memory block;

[0071] S2: classifying the data to be written according to the write request and the old placement location of each data to be written, and obtaining the type of each data to be written;

[0072] S3: Writing the data to be written into a new flash memory block according to the type of each data to be written.

[0073] It should be noted that write requests for data to be written are divided into UW, RRW, and GCW.

[0074] It should be noted that the data to be written is stored in the cache in steps S1 and S2, and the data type is determined and stored according to the data in the cache in step S3.

[0075] It should be noted that the types of data to be written include: warm write data, hot write data, cold write hot read data, cold write cold read data

[0076] Furthermore, if Figure 3 、 Figure 4 As shown, in step S2, the classification of the data to be written includes:

[0077] S201: Determine whether the write request for the data to be written is a read-refresh-write operation or a reclaim block migration operation; if so, the data type is cold-write-hot-read data or cold-write-cold-read data; if not, execute step S202;

[0078] S202: Determine whether the write request for the data to be written is an update operation; if so, execute step S203; if not, the data type is warm write data;

[0079] S203: Determine the old placement flash memory block of the data to be written; if the old placement flash memory block of the data to be written is a pre-filled balancing block or a non-pre-filled balancing block, the data type is warm write data; if the old placement flash memory block of the data to be written is a warm block, a hot block or a reprogramming block, the data type is hot write data.

[0080] Furthermore, the flash memory blocks in the 3D NAND are divided into hot blocks, warm blocks, pre-filled balancing blocks, non-pre-filled balancing blocks, and reprogramming blocks.

[0081] Furthermore, if Figure 5 、 Figure 6 As shown, in step S3, the data to be written is written into a new flash memory block according to the type of the data to be written, including:

[0082] S301: Determine whether there is warm-written data in the cache; if so, store the warm-written data in the warm block and execute step S302; if not, directly execute step S302;

[0083] S302: Determine whether there is hot-write data in the cache; if so, execute step S303; if not, execute step S304;

[0084] S303: Determine whether there is cold write and hot read data in the cache; if so, store the hot write data and the cold write and hot read data in the reprogramming block and execute step S304; if not, store the hot write data in the hot block and execute step S304;

[0085] S304: Determine whether there is cold write hot read data or cold write cold read data in the cache; if so, execute step S305; if not, terminate the storage;

[0086] S305: Determine whether the pre-filled balancing block meets the preset data placement conditions; if so, store the cold write hot read data or the cold write cold read data in the pre-filled balancing block; if not, store the cold write hot read data or the cold write cold read data in a non-pre-filled balancing block.

[0087] Furthermore, the word lines of each layer in the reprogramming block in step S303 include preset high-latency pages and low-latency pages; the hot write data is stored in the high-latency page, and the cold write and hot read data is stored in the low-latency page.

[0088] It should be noted that storing cold-write and hot-read data in low-latency pages can balance the read latency symmetry of pages within a word line and reduce read latency.

[0089] Further, if Figure 7 、 Figure 8 As shown, the method further includes: S4: performing a reprogramming operation on the data written into the reprogramming block; specifically including:

[0090] S30301: Selecting a first layer of a reprogramming block as a first reprogramming block layer; performing a conventional programming operation on the word lines of the first reprogramming block layer in ascending order;

[0091] S30302: Select the first word line of the first reprogramming block layer as the first word line;

[0092] S30303: Determine the validity of the data of the high-latency page; if the data is valid, execute step S30304; if the data is invalid, execute step S30305;

[0093] S30304: Store the data of the high-latency page as cold write and cold read data in the cache; and execute step S30305;

[0094] S30305: reprogramming the first word line;

[0095] S30306: using a word line at a position corresponding to the first word line in a next layer of the first reprogramming block layer as a second word line, and performing a normal programming operation on the second word line;

[0096] S30307: Select the next word line of the first reprogramming block layer as the new first word line; execute step S30303; until all word lines of the first reprogramming block layer are selected;

[0097] S30308: Select the next layer of the first reprogramming block layer as a new first reprogramming block layer, and execute step S30302 until the first reprogramming block layer becomes the last layer of the reprogramming block;

[0098] S30309: reprogramming the word lines of the first reprogramming block layer in ascending order.

[0099] In a three-layer, four-word-line TLC flash memory architecture, the sequence of normal programming and reprogramming is as follows: Figure 9 As shown in FIG. WL(i,j) represents the jth word line in the i-th layer of the memory block.

[0100] In the TLC flash memory architecture, the principle of conventional programming is as follows Figure 10 The principle of reprogramming is shown in Figure 11 shown.

[0101] In the QLC flash memory architecture, the reprogramming principle is as follows Figure 12 As shown, the two upper bits are invalid. The present invention creates a wider read margin for the lower pages.

[0102] It should be noted that if Figure 13 As shown, the existence of invalid pages in the prior art also leads to repeated occupation of voltage states, resulting in insufficient voltage window utilization. Therefore, the present invention releases the voltage space of the invalid pages, which is conducive to improving the utilization of the voltage window.

[0103] Furthermore, if Figure 14 As shown, the reprogramming operation of step S30305 includes:

[0104] S3030101: Encode the data in the first word line into five voltage states using the ISPP algorithm;

[0105] S3030102: Store the states of the five voltages in the first word line.

[0106] It should be noted that the reprogramming operation in step S30309 is similar, that is, encoding the data in the word line into five voltage states and storing the five voltage states in corresponding locations.

[0107] It should be noted that the reprogramming operation increases the read margin between adjacent voltage states, thereby reducing the read disturb effect. The delay block reaches its read endurance threshold, thereby reducing the triggering time of the Flash Translation Layer (FTL). Figure 15The read refresh operations (RROs) shown in the figure reduce the response time and write amplification factor (WAF) of the SSD, thereby increasing the performance and lifespan of the SSD.

[0108] Further, if Figure 16 As shown, the conventional programming operation of step S30306 includes:

[0109] S3030201: Encode the data in the second word line into eight voltage states using the ISPP algorithm;

[0110] S3030202: Store the states of the eight voltages in the second word line.

[0111] It should be noted that the conventional programming operation in step S30301 is similar, and both encode the data in the word line into eight voltage states and store the eight voltage states in corresponding locations.

[0112] Furthermore, the preset data placement condition includes: if the space occupied by the data type of cold write and hot read data in the pre-filled balancing block is less than half of the total space occupied by the pre-filled balancing block, and the space occupied by the data type of cold write and cold read data in the pre-filled balancing block is less than half of the total space occupied by the pre-filled balancing block, then allowing the cold write and hot read data or the cold write and cold read data to be stored; otherwise, not allowing the cold write and cold read data or the cold write and hot read data to be stored.

[0113] like Figure 17 As shown, a high-density 3D NAND flash memory performance optimization system includes:

[0114] Cache read module: obtains write requests and old placement locations of several data to be written;

[0115] Data type classification module: classifies the data to be written according to the write request and the old placement location of each data to be written, and obtains each data type to be written;

[0116] Storage module: writes the data to be written into the hot block, warm block, pre-filled balancing block, non-pre-filled balancing block, and reprogramming block according to the type of the data to be written.

[0117] A computer-readable storage medium includes a high-density 3D NAND flash memory performance optimization method program. When the high-density 3D NAND flash memory performance optimization method program is executed by a processor, the steps of a high-density 3D NAND flash memory performance optimization method are implemented.

[0118] User write data is defined as UW, valid data that needs to be migrated in the reclaimed block is defined as GCW, and write data from RRO is defined as RRW. In order to analyze the difference between RRW and GCW, as shown in Figure 18 As shown, 10 real-world loads are tracked through experiments.

[0119] The average number of reads for GCW is significantly lower than that for RRW. For example, in the web1 workload, the average number of reads for RRW is 13.069, while the average number of reads for GCW is only 0.3194, a difference of approximately 40 times. Similarly, in the ali504 workload, the average number of reads for RRW and GCW differs by more than 6 times. These results indicate that GCW has a significantly lower read frequency compared to RRW. In other words, GCW not only inherently has cold write characteristics, but also cold read characteristics. Therefore, the two types of migrated data can be considered cold write hot read data and cold write cold read data, respectively. Hot write data is identified based on its temporal locality. The process for identifying user-written data is as follows: First, when the request is not an update operation, the data is identified as warm data and written directly to the warm block. If the request is an update operation, further judgment is required based on the data's old location. Specifically, if the data's old location is in a cold block, it is identified as warm data; if the data's old location is in a warm block, it is considered hot-written data; if the data's old location is in a hot block or a reprogrammed block, it continues to be identified as hot-written data. In summary, user-written data is divided into two temperature levels through this process: warm and hot. Because hot writes are frequently updated with short update intervals, the read disturbance caused to the block is almost negligible, so the temperature of the hot-written data can be ignored in terms of reads. Therefore, distinguishing data types and processing them step by step can improve the performance of flash memory.

[0120] The cold blocks include pre-filled balancing blocks and non-pre-filled balancing blocks.

[0121] The same or similar reference numerals correspond to the same or similar components;

[0122] The terms used in the drawings to describe positional relationships are for illustrative purposes only and should not be construed as limiting this patent;

[0123] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A high-density 3D NAND flash memory performance optimization method, characterized in that: include: S1: Obtain write requests for several data to be written in the cache block and the old placement flash memory block; S2: classifying the data to be written according to the write request and the old placement location of each data to be written, and obtaining the type of each data to be written; S3: Writing the data to be written into a new flash memory block according to the type of each data to be written.

2. A high-density 3D NAND flash memory performance optimization method according to claim 1, characterized in that: The flash memory in 3D NAND is divided into hot blocks, warm blocks, pre-filled balancing blocks, non-pre-filled balancing blocks, and reprogramming blocks.

3. A high-density 3D NAND flash memory performance optimization method according to claim 2, characterized in that: In step S2, classifying the data to be written includes: S201: Determine whether the write request for the data to be written is a read-refresh-write operation or a reclaim block migration operation; if so, the data type is cold-write-hot-read data or cold-write-cold-read data; if not, execute step S202; S202: Determine whether the write request for the data to be written is an update operation; if so, execute step S203; if not, the data type is warm write data; S203: Determine the old placement flash memory block of the data to be written; if the old placement flash memory block of the data to be written is a pre-filled balancing block or a non-pre-filled balancing block, the data type is warm write data; if the old placement flash memory block of the data to be written is a warm block, a hot block or a reprogramming block, the data type is hot write data.

4. A high-density 3D NAND flash memory performance optimization method according to claim 3, characterized in that: In step S3, the data to be written is written into a new flash memory block according to the type of the data to be written, including: S301: Determine whether there is warm-written data in the cache; if so, store the warm-written data in the warm block and execute step S302; if not, directly execute step S302; S302: Determine whether there is hot-write data in the cache; if so, execute step S303; if not, execute step S304; S303: Determine whether there is cold write and hot read data in the cache; if so, store the hot write data and the cold write and hot read data in the reprogramming block and execute step S304; if not, store the hot write data in the hot block and execute step S304; S304: Determine whether there is cold write hot read data or cold write cold read data in the cache; if so, execute step S305; if not, terminate the storage; S305: Determine whether the pre-filled balancing block meets the preset data placement conditions; if so, store the cold write hot read data or the cold write cold read data in the pre-filled balancing block; if not, store the cold write hot read data or the cold write cold read data in a non-pre-filled balancing block.

5. A high-density 3D NAND flash memory performance optimization method according to claim 2 or 4, characterized in that: The word lines of each layer in the reprogramming block include a preset high-latency page and a low-latency page; the hot-write data is stored in the high-latency page, and the cold-write hot-read data is stored in the low-latency page.

6. A high-density 3D NAND flash memory performance optimization method according to claim 5, characterized in that: Also includes: S4: performing a reprogramming operation on the data written into the reprogramming block; Specifically include: S30301: Select the first layer of the reprogramming block as the first reprogramming block layer; performing conventional programming operations on the word lines of the first reprogramming block layer in ascending order of word lines; S30302: Select the first word line of the first reprogramming block layer as the first word line; S30303: Determine the validity of the data of the high-latency page; if the data is valid, execute step S30304; if the data is invalid, execute step S30305; S30304: Store the data of the high-latency page as cold write and cold read data in the cache; and execute step S30305; S30305: reprogramming the first word line; S30306: using a word line at a position corresponding to the first word line in a next layer of the first reprogramming block layer as a second word line, and performing a normal programming operation on the second word line; S30307: Select the next word line of the first reprogramming block layer as the new first word line; execute step S30303; until all word lines of the first reprogramming block layer are selected; S30308: Select the next layer of the first reprogramming block layer as a new first reprogramming block layer, and execute step S30302 until the first reprogramming block layer becomes the last layer of the reprogramming block; S30309: reprogramming the word lines of the first reprogramming block layer in ascending order.

7. A high-density 3D NAND flash memory performance optimization method according to claim 6, characterized in that: The reprogramming operation of step S30305 includes: S3030101: Encode the data in the first word line into five voltage states using the ISPP algorithm; S3030102: Store the states of the five voltages in the first word line.

8. The high-density 3D NAND flash memory performance optimization method according to claim 6, characterized in that: The conventional programming operation of step S30306 includes: S3030201: Encode the data in the second word line into eight voltage states using the ISPP algorithm; S3030202: Store the states of the eight voltages in the second word line.

9. The method for optimizing the performance of a high-density 3D NAND flash memory according to claim 4, wherein: The preset data placement condition includes: if the space occupied by data of the cold write and hot read data type in the pre-filled balancing block is less than half of the total space occupied by the pre-filled balancing block, and the space occupied by data of the cold write and cold read data type in the pre-filled balancing block is less than half of the total space occupied by the pre-filled balancing block, then allowing the cold write and hot read data or the cold write and cold read data to be stored; otherwise, not allowing the cold write and cold read data or the cold write and hot read data to be stored.

10. A high-density 3D NAND flash memory performance optimization system, applied to the optimization method according to any one of claims 1 to 9, characterized in that: include: Cache read module: obtains write requests and old placement locations of several data to be written; Data type classification module: classifies the data to be written according to the write request and the old placement location of each data to be written, and obtains each data type to be written; Storage module: writes the data to be written into the hot block, warm block, pre-filled balancing block, non-pre-filled balancing block, and reprogramming block according to the type of the data to be written.

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