Scale-configurable GNSS (Global Navigation Satellite System) baseband
Through time-sharing multiplexing technology and modular architecture design, the hardware resource limitation problem of multi-system, multi-frequency, multi-channel design is solved, and a miniaturized, low-power satellite navigation receiver is realized, with flexible configuration capabilities and efficient signal processing capabilities.
Patent Information
- Application Number
- CN202510513088.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-08-15
AI Technical Summary
How to implement multi-system, multi-frequency, multi-channel GNSS baseband design under limited hardware resources to meet the needs of miniaturized and low-power satellite navigation receivers, and have flexible configuration capabilities.
The combined architecture of IF interface module, preprocessing module, tracking engine FIFO module, tracking engine group and arbitration module is adopted. The multi-system multi-frequency signal is processed through time-sharing multiplexing technology, and the flexible configuration of the channel is achieved using M physical correlators.
Effectively save chip area, improve hardware utilization, support the fusion processing of multiple satellite navigation system signals, strong compatibility, future expansion capabilities, and reduce resource requirements.
Smart Images
Figure CN120498504A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of satellite navigation signal processing and relates to a configurable GNSS baseband. Background Art
[0002] With the continuous development of global satellite navigation systems, the demand for navigation and positioning in daily life, aerospace, national defense, scientific research, and other fields continues to increase. Miniaturized, low-power, and highly integrated satellite navigation receivers have become a key development direction for navigation technology. Designing GNSS basebands with limited hardware resources has become a key issue restricting the development of various navigation products, including those for aircraft, missiles, vehicles, and satellites.
[0003] In the design of multi-mode, multi-frequency baseband architectures, different signal modulation schemes, code rates, and spreading code lengths lead to different baseband signal processing methods, which in turn impact the design of baseband structure and functionality. Therefore, how to fully account for these differences and develop a unique and flexible baseband architecture to process signals from systems such as GPS, BDS, GLONASS, and Galileo has become a pressing challenge in the design of miniaturized, low-power receivers. Summary of the Invention
[0004] The technical problem solved by the present invention is to overcome the shortcomings of the existing technology and propose a scalable GNSS baseband. M physical correlators are used to realize multi-system, multi-frequency, and multi-channel tracking. The GNSS baseband can be arbitrarily configured from a single system and a single frequency point to multiple systems and multiple frequencies. The configuration method is simple and the component modules of the GNSS baseband system can be flexibly selected.
[0005] The solution of the present invention is:
[0006] A scalable GNSS baseband includes an IF interface module, a preprocessing module, a tracking engine FIFO module, a tracking engine group, and an arbitration module;
[0007] IF interface module: receives digital intermediate frequency data of different frequencies, converts it from the sampling clock domain to the system clock domain, converts the data format into the binary complement format, and sends it to the pre-processing module;
[0008] Preprocessing module: responsible for preprocessing the data of different frequencies from the IF interface module to obtain zero intermediate frequency data, and sending it to the tracking engine FIFO module; the preprocessing includes pre-down conversion, anti-aliasing filtering and downsampling processing;
[0009] Tracking engine FIFO module: buffers the zero-IF data from the pre-processing module and sends it as a block to the tracking engine group after accumulating a predetermined amount;
[0010] Tracking engine group: performs correlation processing on the zero-IF data blocks sent by the tracking engine FIFO module, performs coherent accumulation on the correlated data, and sends the accumulated data to the arbitration module;
[0011] Arbitration module: stores the coherent accumulated data sent by the tracking engine group in SRAM and sends it to the outside through the host interface.
[0012] Preferably, the IF interface module receives N channels of digital intermediate frequency data, converts the received data from the sampling clock domain to the system clock domain through a 4xNbit asynchronous FIFO, and then converts the data format to a binary complement format.
[0013] Preferably, the pre-processing module provides N separate signal processing channels, corresponding one-to-one to the N output data of the IF interface module. The N signal processing channels of the pre-processing module have their own independent enable and are controlled by the top-level global register.
[0014] Preferably, the tracking engine group processes data of multiple frequency points in a time-division multiplexing manner, and each time it processes data of one frequency point, it processes multiple channels in a time-division multiplexing manner; the data processing of each frequency point is called a tracking engine frequency point set. During processing, each tracking engine frequency point set is bound to an intermediate frequency signal in the tracking engine FIFO module, and the enable bit of the corresponding tracking engine frequency point set simultaneously controls the external enable control of the corresponding tracking engine FIFO channel.
[0015] Preferably, the tracking engine group includes M baseband related logic modules, a control logic module, and a coherent accumulation logic module; each baseband related logic module includes a channel correlator and a FIFO;
[0016] The zero-IF data blocks sent by the tracking engine FIFO module enter M channel correlators simultaneously. The M channel correlators select one channel of IF data for processing based on their respective control signals.
[0017] Each channel correlator reads its own status information from the control logic module, performs correlation processing on the received data based on its own status information, and the processed data enters the coherent accumulation logic module through the FIFO for coherent accumulation processing. The data after coherent accumulation processing is sent to the arbitration module;
[0018] The control logic module is used to store the status information of each channel correlator after processing a zero intermediate frequency data block, and also stores the control information of each tracking channel.
[0019] Preferably, M baseband-related logic modules process P tracking channels in a time division multiplexing manner, where P>M.
[0020] Preferably, the tracking engine group further includes a status buffer, wherein the status buffer sets an image for each channel correlator of the processed P tracking channels, and is used to store status information of the channel correlator.
[0021] Preferably, the status buffer includes a configuration register and a status register; the content of the configuration register represents the configuration information of each channel correlator and will not change during the channel correlation operation; the content of the status register represents the status information of each channel correlator and will change with the channel correlation.
[0022] Preferably, the control logic module maintains a set of independent read and write pointers for each frequency point, but the intermediate frequency data of all frequencies share a memory. Multiple channel correlators work simultaneously when writing, but at the same time, only one channel correlator in each tracking engine group is reading.
[0023] Preferably, the digital intermediate frequency data of different frequencies include GPS, BDS, GLONASS and Galileo digital intermediate frequency data of different frequencies.
[0024] The beneficial effects of the present invention compared with the prior art are:
[0025] (1) The present invention uses time-division multiplexing for tracking channels in satellite signal tracking, effectively saving chip area and improving hardware utilization. For intermediate frequency inputs of different satellite frequencies, independently configurable IF interfaces are used to receive and convert intermediate frequency signals of different constellation frequencies. The independent IF interfaces can be configured to track and process different spread spectrum codes, and can also use power statistics to feedback and adjust the gain of the internal amplifier of the RF front end to optimize the input power of different types of intermediate frequency signals.
[0026] (2) The baseband signal architecture of the present invention will be able to integrate and process signals from multiple satellite navigation systems, and is compatible with both regional and global signals. Furthermore, the circuit scale is small, and the number of equivalent channels is large, allowing the receiver to achieve higher processing capabilities while using fewer resources. This not only meets compatibility with existing satellite navigation systems, but also has sufficient flexibility to meet future expansion needs. The receiver does not need to establish a complete processing system for each navigation system, achieving multi-frequency, multi-mode tracking, and joint positioning. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a schematic diagram of the present invention;
[0028] Figure 2 Design module implementation diagram for IF interface;
[0029] Figure 3 Implement graph for preprocessing module;
[0030] Figure 4 This is a structural diagram of the tracking engine group. DETAILED DESCRIPTION
[0031] The present invention will be further described below with reference to the accompanying drawings.
[0032] The present invention provides a scalable GNSS baseband, such as Figure 1 As shown in the figure, the basic concept is as follows: the IF interface is responsible for input data format conversion and clock domain conversion. The preprocessing module is responsible for preprocessing data at different frequencies, converting it to zero-IF data and reducing the sampling rate as much as possible. The tracking engine FIFO module is responsible for storing the converted zero-IF data, providing data synchronization, and supplying data to the time-division multiplexed tracking engine group. The tracking engine group contains several independent baseband-related logic. A tracking engine group (TE Group) can process data at multiple frequencies in a time-division multiplexed manner. Each frequency is processed in a time-division multiplexed manner, and each frequency is processed in a time-division multiplexed manner. The data processed at each frequency is called a tracking engine frequency set (TE Set). During processing, each tracking engine frequency set is bound to an IF signal in the tracking engine FIFO. The enable bit of the corresponding tracking engine frequency set also controls the external enable control of the corresponding tracking engine FIFO channel. Whether a tracking engine group contains multiple tracking engine frequency sets is determined by the operating main frequency and sampling rate.
[0033] Specifically, the present invention includes:
[0034] S1: IF interface module
[0035] Provides conversion of digital intermediate frequency data from the sampling clock domain to the system clock domain and data format conversion. Figure 2 As shown, the IF interface module can process N channels of AD data in parallel. The digital intermediate frequency data is converted from the input interface to the system clock domain through a 4xN-bit asynchronous FIFO, and then format converted and unified into a two's complement format.
[0036] S2: Preprocessing module
[0037] Complete pre-down conversion, anti-aliasing filtering and down sampling. The pre-processing module provides independent N-channel signal processing, which are connected to the N-channel AD data of the IF interface module. The N channels of the pre-processing module have their own independent enable, which is controlled by the top-level global register. Figure 3 As shown, the pre-downconversion uses a 32-bit NCO. The upper 6 bits are used as the index for the sin / cos lookup table. The 5-bit input data is multiplied by the 4-bit sin / cos lookup table content to obtain 8-bit I / Q results. Downsampling uses decimation after anti-aliasing filtering, and the anti-aliasing filter is a 16-order FIR filter.
[0038] S3: Tracking Engine FIFO Module
[0039] It is used to cache input samples and, after a certain number of samples are accumulated, they are collectively treated as a block for processing by the tracking engine group.
[0040] The trace engine FIFO module outputs a block of samples each time. Because the trace engine group TE logic uses time division multiplexing, it will run repeatedly multiple times. During each run, the trace engine FIFO repeatedly outputs the same set of samples as a block until the trace engine group notifies the trace engine FIFO that this is the last round of output.
[0041] The IF data for all frequencies is handled by a single tracking engine FIFO. The FIFO control logic maintains a separate set of read and write pointers for each frequency. However, all IF data for all frequencies share a single memory. While multiple channels can write simultaneously, only one channel per tracking engine group can read at a time.
[0042] S4: Tracking Engine Group
[0043] It includes M baseband related logic modules, related accumulation logic modules, control logic modules and memory. Each baseband related logic module includes a physical correlator and a related data FIFO, such as Figure 4 shown.
[0044] (1) The control logic module independently controls the correlation of multiple correlators, using time-division multiplexing. When the intermediate frequency data corresponding to any channel is ready, the control logic module initiates the correlation operation for the corresponding channel. The channel enable register in the control logic module indicates which channel correlator is in the active state. When performing correlation, the state buffer contents of the M physical correlators are loaded sequentially, and then the correlation is performed.
[0045] (2) Each physical correlator is connected to a correlation data FIFO, which is used to store the correlation data of each tracking channel. The zero-IF data block sent by the tracking engine FIFO module enters M channel correlators simultaneously; each channel correlator reads its own status information from the control logic module and performs correlation processing on the received data based on its own status information. The processed data enters the coherent accumulation logic module through the FIFO.
[0046] (3) The coherent accumulation logic module is used to accumulate the results in the relevant data FIFO into the coherent accumulation data memory. The data will be accumulated to the corresponding address and sent to the arbitration module.
[0047] The arbitration module stores the coherent accumulation sent by the coherent accumulation logic module in the SRAM through the arbitration module. In addition, the data can also be sent to the outside through the host interface.
[0048] S5: State Buffer
[0049] The core data structure of the trace engine group. It is essentially the registers in the trace engine group. Due to channel multiplexing, during "fill / dump" operations, the register contents are mapped in SRAM for each channel correlator. This image is called the state buffer.
[0050] The contents of the state buffer are divided into two categories: configuration registers and status registers. Configuration registers contain channel configuration information and do not change during channel-related operations. Status registers contain channel status information and change with channel-related operations. Therefore, when switching between channels, a "load" operation requires loading the entire state buffer. After channel operation is complete, a "backfill" operation simply writes the status register contents back to SRAM.
[0051] This invention uses channel multiplexing technology, with P tracking channels sharing M physical correlators (P > M). The tracking channels are determined by the signal frequency and the number of satellites. This allows for flexible configuration of GNSS baseband system size based on actual application requirements, effectively conserving hardware resources and reducing costs. This technology lays the foundation for the design and development of miniaturized, low-power satellite navigation chips.
[0052] The present invention provides a configurable GNSS baseband, which uses a unique flexible baseband architecture to process navigation signals such as GPS, BDS, GLONASS and Galileo. In tracking satellite signals, the tracking channel is time-division multiplexed. When the corresponding channel multiplexing is switched, the status / control data of the corresponding channel is loaded, and after the channel operation is completed, the register status data of the corresponding channel is written back to the SRAM. The channel time-division multiplexing method effectively saves chip area and improves hardware utilization. The scale of the GNSS baseband can be arbitrarily configured from the simplest single system to multi-system multi-frequency point joint processing, and the configuration method is simple and easy to operate. According to the final implementation form of the GNSS baseband, the source and characteristics of the input intermediate frequency signal, and the type and purpose of the signal to be processed, the component modules of the system can be flexibly selected.
[0053] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.
Claims
1. A scalable GNSS baseband, characterized by: Includes IF interface module, pre-processing module, tracking engine FIFO module, tracking engine group, arbitration module; IF interface module: receives digital intermediate frequency data of different frequencies, converts it from the sampling clock domain to the system clock domain, converts the data format into the binary complement format, and sends it to the pre-processing module; Preprocessing module: responsible for preprocessing the data of different frequencies from the IF interface module to obtain zero intermediate frequency data, and sending it to the tracking engine FIFO module; the preprocessing includes pre-down conversion, anti-aliasing filtering and downsampling processing; Tracking engine FIFO module: buffers the zero-IF data from the pre-processing module and sends it as a block to the tracking engine group after accumulating a predetermined amount; Tracking engine group: performs correlation processing on the zero-IF data blocks sent by the tracking engine FIFO module, performs coherent accumulation on the correlated data, and sends the accumulated data to the arbitration module; Arbitration module: stores the coherent accumulated data sent by the tracking engine group in SRAM and sends it to the outside through the host interface.
2. The scalable GNSS baseband according to claim 1, characterized in that: The IF interface module receives N channels of digital intermediate frequency data, converts the received data from the sampling clock domain to the system clock domain through a 4xN-bit asynchronous FIFO, and then converts the data format to a binary complement format.
3. The scalable GNSS baseband according to claim 1, characterized in that: The pre-processing module provides N separate signal processing channels, which correspond one-to-one to the N output data of the IF interface module. The N signal processing channels of the pre-processing module have their own independent enable and are controlled by the top-level global register.
4. The scalable GNSS baseband according to claim 1, characterized in that: The tracking engine group processes data from multiple frequencies in a time-division multiplexing manner, and when processing data from each frequency point, it also processes multiple channels in a time-division multiplexing manner; The data processing for each frequency point is called a tracking engine frequency set. During processing, each tracking engine frequency set is bound to an intermediate frequency signal in the tracking engine FIFO module. The enable bit of the corresponding tracking engine frequency set also controls the external enable control of the corresponding tracking engine FIFO channel.
5. The scalable GNSS baseband according to claim 1, characterized in that: The tracking engine group includes M baseband-related logic modules, a control logic module, and a coherent accumulation logic module; Each baseband correlation logic module includes a channel correlator and a FIFO; The zero-IF data blocks sent by the tracking engine FIFO module enter M channel correlators simultaneously. The M channel correlators select one channel of IF data for processing based on their respective control signals. Each channel correlator reads its own status information from the control logic module, performs correlation processing on the received data based on its own status information, and the processed data enters the coherent accumulation logic module through the FIFO for coherent accumulation processing. The data after coherent accumulation processing is sent to the arbitration module; The control logic module is used to store the status information of each channel correlator after processing a zero intermediate frequency data block, and also stores the control information of each tracking channel.
6. The scalable GNSS baseband according to claim 5, characterized in that: M baseband-related logic modules process P tracking channels through time division multiplexing, where P>M.
7. The scalable GNSS baseband according to claim 6, characterized in that: The tracking engine group further includes a state buffer, wherein the state buffer sets an image for each channel correlator of the processed P tracking channels, and is used to store state information of the channel correlator.
8. The scalable GNSS baseband according to claim 7, characterized in that: The status buffer includes a configuration register and a status register; the content of the configuration register is the configuration information of each channel correlator, which will not change during the channel correlation operation; the content of the status register is the status information of each channel correlator, which will change with the channel correlation.
9. The scalable GNSS baseband according to claim 5, characterized in that: The control logic module maintains an independent set of read and write pointers for each frequency point, but the intermediate frequency data of all frequencies share a common memory. Multiple channel correlators work simultaneously when writing, but at the same time, only one channel correlator in each tracking engine group is reading.
10. The scalable GNSS baseband according to claim 1, characterized in that: The digital intermediate frequency data of different frequencies include GPS, BDS, GLONASS and Galileo digital intermediate frequency data of different frequencies.