Gallium nitride Darlington transistor and preparation method thereof

Abstract

The present invention discloses a gallium nitride Darlington transistor and its preparation method, belonging to the technical field of semiconductor electronic devices. The transistor comprises a driver transistor and an output transistor, both of which contain, from bottom to top, a collector region, a base region, an emitter region, and corresponding collector, base, and emitter electrodes. The driver transistor emitter is electrically connected to the output transistor base, and the collectors are connected in parallel. The output transistor active area is n times that of the driver transistor (n>1). Preparation methods include discrete integration and on-chip integration. This invention significantly improves the current amplification factor through a cascade structure, leveraging the advantages of gallium nitride materials, filling the technical gap of gallium nitride Darlington transistors and being suitable for high-temperature, high-voltage, and high-frequency scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor electronic devices, and in particular to a gallium nitride Darlington transistor and a preparation method thereof. Background Art

[0002] A Darlington transistor is a composite structure consisting of two bipolar transistors directly connected in cascade. Its overall current gain is the product of the current gains of the two transistors, often reaching thousands or even higher. Due to its ultra-high current gain and high input impedance, and its ability to replace multi-stage discrete amplifiers, thus simplifying circuit design, Darlington transistors are widely used in scenarios such as high-current switching and precision signal amplification.

[0003] Currently, Darlington transistors are mostly limited to silicon-based materials. Compared with silicon materials, gallium nitride materials have many advantages such as wide bandgap, high breakdown field strength, high thermal conductivity and high saturation electron mobility. Gallium nitride devices have broader development prospects in the field of high-temperature, high-voltage and high-frequency devices. Therefore, the concept of realizing Darlington transistors on gallium nitride materials has far-reaching significance. Summary of the Invention

[0004] In view of the above deficiencies in the prior art, the present invention provides a gallium nitride Darlington transistor and a method for preparing the same, thereby filling the gap in the existing Darlington transistor device system.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a gallium nitride Darlington transistor, comprising a driver transistor and an output transistor, wherein the gallium nitride semiconductor epitaxial structures of the driver transistor and the output transistor each comprise a collector region, a base region, and an emitter region stacked from bottom to top, and the electrode structures of the driver transistor and the output transistor each comprise a collector connected to the collector region, a base connected to the base region, and an emitter connected to the emitter region;

[0007] The emitter of the driving tube is electrically connected to the base of the output tube, the base of the driving tube serves as the base of the Darlington transistor, the emitter of the output tube serves as the emitter of the Darlington transistor, the collector of the driving tube and the collector of the output tube are connected in parallel to serve as at least part of the collector of the Darlington transistor; the area of ​​the emitter region is the area of ​​the active region, the area of ​​the active region of the output tube is n times the area of ​​the active region of the driving tube, and n>1.

[0008] As a further optimization solution of the present invention, the Darlington transistor includes a package tube shell and a driver tube and an output tube separately integrated on a metal electrode area of ​​the package tube shell, the metal electrode area of ​​the package tube shell is fixed to and electrically interconnected with the collectors of the driver tube and the output tube respectively; the collectors of the driver tube and the output tube and the metal electrode area of ​​the package tube shell are connected in parallel as the collector of the Darlington transistor.

[0009] As a further optimization solution of the present invention, the Darlington transistor includes a driver tube and an output tube integrated on the same wafer, and the driver tube and the output tube share a collector region and a collector electrode.

[0010] As a further optimization scheme of the present invention, the collector region includes a substrate, a buffer layer and a first gallium nitride semiconductor layer stacked from bottom to top, the substrate is made of gallium nitride, the first gallium nitride semiconductor layer is of n-type doping type, the base region includes a second gallium nitride semiconductor layer of p-type doping type, and the emitter region includes a third gallium nitride semiconductor layer of n-type doping type.

[0011] As a further optimization solution of the present invention, the components of the first gallium nitride semiconductor layer include In x1 Al y1 Ga 1-x1-y1 N, 0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1, and is doped with an n-type dopant; the components of the second gallium nitride semiconductor layer include In x2 Al y2 Ga 1-x2-y1=2 N, 0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1, and is doped with a p-type dopant; the components of the third gallium nitride semiconductor layer include In x3 Al y3 Ga 1-x3-y3 N, 0≤x3≤1, 0≤y3≤1, 0≤x3+y3≤1, and is doped with an n-type dopant.

[0012] As a further optimization solution of the present invention, the n-type dopant includes at least one of Si, Ge, Sn, and Se, and the p-type dopant includes at least one of Mg, Zn, Ca, Sr, and Ba.

[0013] As a further optimization solution of the present invention, the collector region, base region, emitter region, base and emitter are covered with a passivation layer; windows are opened on the passivation layer corresponding to the base and emitter, and metal pads are deposited in the windows.

[0014] In a second aspect, the present invention provides a method for preparing the gallium nitride Darlington transistor, comprising any one of the following methods:

[0015] Method 1:

[0016] The driver tube and output tube are prepared independently. After preparation, a conductive adhesive is applied to the collectors of the driver tube and the output tube. The driver tube and the output tube coated with the conductive adhesive are placed with the collector facing downward on the metal electrode area of ​​the package tube shell. The driver tube, the output tube and the package tube shell are fixed and electrically interconnected by heating and baking.

[0017] The emitter of the driving tube and the base of the output tube are electrically interconnected, the base of the driving tube is led out as the base of the Darlington transistor, the emitter of the output tube is led out as the emitter of the Darlington transistor, the collectors of the driving tube and the output tube and the metal electrode area are connected in parallel and led out as the collector of the Darlington transistor, and finally a discrete integrated Darlington transistor is obtained.

[0018] Method 2:

[0019] The collector region and collector are shared, and the driver tube and output tube are prepared simultaneously on the same wafer. After the preparation is completed, the emitter of the driver tube and the base of the output tube are electrically interconnected, the base of the driver tube is led out as the base of the Darlington transistor, the emitter of the output tube is led out as the emitter of the Darlington transistor, and the shared collector of the driver tube and the output tube is led out as the collector of the Darlington transistor, finally obtaining an on-chip integrated Darlington transistor.

[0020] As a further optimization solution of the present invention, in method 1, the preparation method of the driving tube or the output tube includes:

[0021] A buffer layer, a first gallium nitride semiconductor layer, a second gallium nitride semiconductor layer, and a third gallium nitride semiconductor layer are sequentially grown on the substrate to form the prototypes of a collector region, a base region, and an emitter region;

[0022] Etching and removing a portion of the periphery of the third gallium nitride semiconductor layer to obtain a formed emitter region and expose the base region mesa;

[0023] Etching away a portion of the second gallium nitride semiconductor layer and the periphery of the first gallium nitride semiconductor layer to obtain a formed collector region and base region to achieve electrical isolation of the device;

[0024] Depositing a base electrode on the formed base region mesa;

[0025] Depositing an emitter electrode and a collector electrode on the formed emitter region and collector region respectively;

[0026] Depositing and covering the formed collector region, base region, emitter region, base electrode and emitter electrode to form a passivation layer;

[0027] Windows are opened on the passivation layer corresponding to the formed base and emitter, and metal pads are deposited in the windows.

[0028] As a further optimization solution of the present invention, in method 2, the preparation method of the driving tube and the output tube includes:

[0029] A buffer layer, a first gallium nitride semiconductor layer, a second gallium nitride semiconductor layer, and a third gallium nitride semiconductor layer are sequentially grown on the same substrate, and the prototypes of the collector region, base region, and emitter region of the driver transistor and the output transistor are simultaneously formed;

[0030] Etching away a portion of the periphery and the middle of the third gallium nitride semiconductor layer to obtain the shaped emission regions of the driving tube and the output tube, and simultaneously exposing the base region mesas of the driving tube and the output tube;

[0031] Etching away the periphery and a portion of the middle of the second gallium nitride semiconductor layer and the first gallium nitride semiconductor layer to obtain the collector region and base region of the formed driver transistor and output transistor, thereby achieving electrical isolation of the device;

[0032] Depositing a base electrode on the base mesa of the formed driving tube and output tube;

[0033] Depositing an emitter electrode and a collector electrode on the emitter region and the collector region of the formed driving tube and output tube respectively;

[0034] Depositing and covering the collector region, base region, emitter region, base electrode and emitter electrode of the formed driving tube and output tube to form a passivation layer;

[0035] Windows are opened on the passivation layer corresponding to the formed base and emitter, and metal pads are deposited in the windows.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] (1) In view of the fact that existing Darlington transistors are mostly limited to silicon-based ones, the present invention realizes the Darlington transistor structure on gallium nitride materials for the first time, filling the gap of gallium nitride Darlington transistors in the device system and providing a new solution for the field of semiconductor device technology. Compared with traditional silicon-based Darlington transistors, the present invention adopts gallium nitride materials and utilizes its wide bandgap, high breakdown field strength, high thermal conductivity and high saturation electron mobility. This makes the transistor have a broader application prospect in the field of high-temperature, high-voltage and high-frequency devices and can adapt to more stringent working environments.

[0038] (2) The present invention provides two methods: discrete integration and on-chip integration. Discrete integration allows the selection of driver and output transistors with matching electrical characteristics, and the fixation and interconnection are achieved through the metal electrode area of ​​the package tube shell. On-chip integration is simultaneously prepared on the same wafer, sharing the collector area and collector electrode, simplifying the structure and process. Both methods can effectively realize the GaN Darlington structure, improving the flexibility of device design.

[0039] (3) The present invention adopts a GaN Darlington structure, which consists of a cascade of a driver transistor and an output transistor. The overall current gain is the product of the current gains of the two transistors. For example, in the embodiment, the maximum common emitter DC current gain of the driver transistor is 21, and that of the output transistor is 102. The maximum gain of the resulting GaN Darlington transistor is approximately 1900, which significantly improves the DC current amplification factor of the GaN bipolar transistor and effectively solves the problem of insufficient amplification factor of a single GaN bipolar transistor.

[0040] (4) The present invention designs the active area of ​​the output tube to be n times (n>1) that of the driver tube. The area ratio can be adjusted according to the matching relationship between the output current of the driver tube and the input current of the output tube, ensuring that the output current of the driver tube can drive the output tube to operate in the amplification area, thereby stably maintaining the amplification performance of the Darlington structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of the epitaxial structure of an NPN-type gallium nitride bipolar transistor provided by an embodiment of the present invention.

[0042] Figure 2 Schematic diagram of the epitaxial structure of an NPN-type gallium nitride bipolar transistor after the first etching provided by an embodiment of the present invention.

[0043] Figure 3 Schematic diagram of the epitaxial structure of an NPN-type gallium nitride bipolar transistor after two etchings provided by an embodiment of the present invention.

[0044] Figure 4 This is a schematic structural diagram of an NPN-type gallium nitride bipolar transistor with a prepared base provided by an embodiment of the present invention.

[0045] Figure 5 This is a schematic structural diagram of an NPN-type gallium nitride bipolar transistor with a base, emitter, and collector prepared according to an embodiment of the present invention.

[0046] Figure 6 This is a schematic structural diagram of an NPN-type gallium nitride bipolar transistor after a passivation layer is deposited on the surface provided by an embodiment of the present invention.

[0047] Figure 7 A schematic structural diagram of an NPN-type gallium nitride bipolar transistor after a window is opened in the passivation layer and a metal pad is fabricated according to an embodiment of the present invention.

[0048] Figure 8 A schematic diagram of the three-dimensional structure of a discrete integrated GaN Darlington transistor before interconnection provided by an embodiment of the present invention (the passivation layer and metal pad are omitted).

[0049] Figure 9A schematic diagram of the three-dimensional structure of a discrete integrated GaN Darlington transistor after interconnection provided by an embodiment of the present invention (the passivation layer and metal pad are omitted).

[0050] Figure 10 A schematic structural diagram of an on-chip integrated gallium nitride Darlington transistor before interconnection provided by an embodiment of the present invention.

[0051] Figure 11 A schematic structural diagram of an on-chip integrated gallium nitride Darlington transistor after interconnection provided by an embodiment of the present invention.

[0052] Figure 12 This is the common emitter output curve of the driver tube provided by the embodiment of the present invention.

[0053] Figure 13 This is the common emitter output curve of the output tube provided by the embodiment of the present invention.

[0054] Figure 14 This is a common emitter output curve of the Darlington transistor provided by an embodiment of the present invention.

[0055] Figure numerals: 1-driving tube, 2-output tube, 3-collector region, 31-substrate, 32-buffer layer, 33-first gallium nitride semiconductor layer, 4-base region, 41-second gallium nitride semiconductor layer, 5-emitter region, 51-third gallium nitride semiconductor layer, 6-collector, 7-base, 8-emitter, 9-passivation layer, 10-metal pad, 11-metal electrode region. DETAILED DESCRIPTION

[0056] To help those skilled in the art better understand the technical solutions of the present invention, the preferred embodiments of the present invention are described below in conjunction with specific examples. However, it should be understood that the drawings are for illustrative purposes only and are not to be construed as limiting this patent. To better illustrate this embodiment, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the drawings. The positional relationships described in the drawings are for illustrative purposes only and are not to be construed as limiting this patent.

[0057] An embodiment of the present invention provides a gallium nitride Darlington transistor, comprising a driver transistor 1 and an output transistor 2. Both driver transistors 1 and output transistor 2 are gallium nitride bipolar transistors with a vertical structure. An emitter 8 of driver transistor 1 is electrically connected to a base 7 of output transistor 2. Base 7 of driver transistor 1 serves as base 7 of the Darlington transistor, while emitter 8 of output transistor 2 serves as emitter 8 of the Darlington transistor. A collector 6 of driver transistor 1 and collector 6 of output transistor 2 are connected in parallel to serve as at least a portion of collector 6 of the Darlington transistor. The area of ​​emitter region 5 is the area of ​​the active region. The active region area of ​​output transistor 2 is n times the active region area of ​​driver transistor 1, where n>1. The specific value of n depends on the matching relationship between the output current of driver transistor 1 and the input current of output transistor 2.

[0058] like Figure 7 As shown, the gallium nitride bipolar transistor includes a gallium nitride semiconductor epitaxial structure and a base 7, a collector 6 and an emitter 8. The gallium nitride semiconductor epitaxial structure includes a collector region 3, a base region 4 and an emitter region 5 stacked from bottom to top. The base 7 is connected to the base region 4, the emitter 8 is connected to the emitter region 5, and the collector 6 is connected to the collector region 3. The collector region 3, the base region 4, the emitter region 5, the base 7 and the emitter 8 are covered with a passivation layer 9; windows are opened in the passivation layer 9 corresponding to the base 7 and the emitter 8, and metal pads 10 are deposited in the windows. It is particularly pointed out that the collector 6 used in the embodiment of the present invention is a back electrode method.

[0059] Specifically, the collector region 3 includes a substrate 31, a buffer layer 32 and a first gallium nitride semiconductor layer 33 stacked from bottom to top. The substrate 31 is made of gallium nitride, and the first gallium nitride semiconductor layer 33 is doped with n-type. The base region 4 includes a second gallium nitride semiconductor layer 41 with a p-type doping type, and the emitter region 5 includes a third gallium nitride semiconductor layer 51 with an n-type doping type.

[0060] Furthermore, the first gallium nitride semiconductor layer 33 comprises In x1 Al y1 Ga 1-x1-y1 N, 0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1, and is doped with an n-type dopant; the composition of the second gallium nitride semiconductor layer 41 includes In x2 Al y2 Ga 1-x2-y1=2 N, 0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1, and is doped with a p-type dopant; the composition of the third gallium nitride semiconductor layer 51 includes In x3 Al y3 Ga 1-x3-y3N, 0≤x3≤1, 0≤y3≤1, 0≤x3+y3≤1, and is doped with an n-type dopant. The doping concentration of the n-type dopant in the first gallium nitride semiconductor layer is in the range of 1e14-1e24 cm -3 , the preferred actual concentration is 1e16 cm -3 The doping concentration of the p-type dopant in the second GaN semiconductor layer is in the range of 1e14-1e24 cm -3 , the preferred actual concentration is 1e19 cm -3 The doping concentration of the n-type dopant in the third gallium nitride semiconductor layer is in the range of 1e14-1e24 cm -3 , the preferred actual concentration is 2e19 cm -3 The n-type dopant includes at least one of Si, Ge, Sn, and Se, and the p-type dopant includes at least one of Mg, Zn, Ca, Sr, and Ba.

[0061] In some embodiments, as Figure 8 and Figure 9 As shown, the Darlington transistor includes a package tube housing, and a driver transistor 1 and an output transistor 2, which are discretely integrated on a metal electrode region 11 of the package tube housing. The metal electrode region 11 of the package tube housing is fixed to and electrically interconnected with the collector electrodes 6 of the driver transistor 1 and output transistor 2, respectively. The collector electrodes 6 of the driver transistor 1 and output transistor 2, along with the metal electrode region 11 of the package tube housing, are connected in parallel to serve as the collector electrode 6 of the Darlington transistor. Two single transistors with matching electrical characteristics are selected from the fabricated gallium nitride bipolar transistor to serve as the driver transistor 1 and output transistor 2, respectively. Specifically, the output current of the driver transistor 1 must be comparable to the input current of the output transistor 2, meaning that the output current of the driver transistor 1 can drive the output transistor 2 to operate in the amplification region. Specifically, assuming that the output current density of the gallium nitride bipolar transistors is similar under the same gallium nitride semiconductor epitaxial structure and the same process conditions, the current can be controlled by adjusting the active area of ​​the driver transistor 1 and output transistor 2. Specifically, the active area of ​​the output transistor 2 can be n times that of the driver transistor 1. In the embodiment of the present invention, the active area of ​​the output tube 2 is selected to be 9 times the active area of ​​the driving tube 1 .

[0062] Based on the above structural design, an embodiment of the present invention provides a method for preparing a discrete integrated gallium nitride Darlington transistor, comprising the following steps:

[0063] (1) Prepare the drive tube 1 or output tube 2 independently:

[0064] like Figure 1As shown, a buffer layer 32, a first gallium nitride semiconductor layer 33, a second gallium nitride semiconductor layer 41 and a third gallium nitride semiconductor layer 51 are sequentially grown on a substrate 31 by metal organic chemical vapor deposition (MOCVD) to form the prototype of the collector region 3, the base region 4 and the emitter region 5 of the driving transistor 1 or the output transistor 2.

[0065] like Figure 2 As shown, inductively coupled plasma etching (ICP) and reactive ion etching (RIE) are used to etch away a portion of the periphery of the third gallium nitride semiconductor layer 51 to obtain a formed emitter region 5 and expose the mesa of the base region 4.

[0066] like Figure 3 As shown, inductively coupled plasma etching (ICP) and reactive ion etching (RIE) are used to etch away a portion of the periphery of the second gallium nitride semiconductor layer 41 and the first gallium nitride semiconductor layer 33 to obtain the formed collector region 3 and base region 4, thereby achieving electrical isolation of the device.

[0067] like Figure 4 As shown, a base electrode 7 is formed by deposition on the formed base region 4 table. Specifically, a metal deposition device such as electron beam evaporation (EBE) may be used to deposit one metal material selected from Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, Mo and ITO, or an alloy formed by two or more metal materials, and then rapid thermal annealing (RTA) is performed to achieve a low-resistance ohmic contact.

[0068] like Figure 5 As shown, emitter 8 and collector 6 are deposited on the formed emitter region 5 and collector region 3, respectively. Specifically, the manufacturing process can be to deposit one metal material selected from Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Sn, In, Ru, Mg, Zn, Pt, Mo, and ITO, or an alloy of two or more metal materials, using metal deposition equipment such as electron beam evaporation (EBE). The emitter 8 and collector 6 can be fabricated in any order.

[0069] like Figure 6 As shown, a passivation layer 9 is deposited over the formed collector region 3, base region 4, emitter region 5, base electrode 7, and emitter electrode 8 to form a covering. The passivation layer 9 can be made of SiO2, SixOy, Si3N4, SixNy, SiOxNy, or Al2O3. The specific deposition process can be plasma-enhanced chemical vapor deposition (PECVD), etc.

[0070] like Figure 7As shown, windows are opened in the passivation layer 9 corresponding to the formed base 7 and emitter 8, and metal pads 10 are deposited in the windows. The window opening method can be a dry etching method, such as reactive ion etcher (RIE), inductively coupled plasma etching (ICP), or a wet etching method, such as buffered oxide etchant (BOE), or a combination of dry and wet etching methods.

[0071] (2) After the driver tube 1 and the output tube 2 are prepared, a conductive adhesive is applied to the collector 6 of the driver tube 1 and the output tube 2. The driver tube 1 and the output tube 2 coated with the conductive adhesive are placed on the metal electrode area 11 of the package tube shell with the collector 6 facing downward. The driver tube 1 and the output tube 2 are fixed and electrically interconnected with the package tube shell by baking them on a hot plate at 180°C for 3 hours.

[0072] (3) The emitter 8 of the driver tube 1 and the base 7 of the output tube 2 are electrically interconnected by a gold wire bonding machine or an aluminum wire bonding machine, the base 7 of the driver tube 1 is led out as the base 7 of the Darlington transistor, the emitter 8 of the output tube 2 is led out as the emitter 8 of the Darlington transistor, and the collector 6 of the driver tube 1 and the output tube 2 and the metal electrode area 11 are led out in parallel as the collector 6 of the Darlington transistor, and finally a discrete integrated Darlington transistor is obtained.

[0073] In some embodiments, as Figure 10 and Figure 11 As shown, the Darlington transistor includes a driver transistor 1 and an output transistor 2 integrated on the same wafer. Driver transistor 1 and output transistor 2 share a collector region 3 and a collector electrode 6. Of the two adjacent gallium nitride bipolar transistors on the chip, the one with the smaller active area serves as driver transistor 1, and the one with the larger active area serves as output transistor 2. The active area of ​​driver transistor 1 must match the active area of ​​output transistor 2, so that both driver transistors 1 and output transistor 2 can operate in the optimal current amplification state. In this embodiment of the present invention, the active area of ​​output transistor 2 is selected to be 9 times the active area of ​​driver transistor 1.

[0074] Based on the above structural design, an embodiment of the present invention provides a method for preparing an on-chip integrated gallium nitride Darlington transistor, comprising the following steps:

[0075] (1) Synchronously prepare the drive tube 1 and output tube 2:

[0076] A buffer layer 32, a first gallium nitride semiconductor layer 33, a second gallium nitride semiconductor layer 41, and a third gallium nitride semiconductor layer 51 are sequentially grown on the same substrate 31, and the prototypes of the collector region 3, the base region 4, and the emitter region 5 of the driver transistor 1 and the output transistor 2 are simultaneously formed;

[0077] Etching away a portion of the periphery and the middle of the third gallium nitride semiconductor layer 51 to obtain the shaped emitter regions 5 of the driver transistor 1 and the output transistor 2, and simultaneously exposing the base regions 4 of the driver transistor 1 and the output transistor 2;

[0078] Etching away the outer periphery and a portion of the middle of the second gallium nitride semiconductor layer 41 and the first gallium nitride semiconductor layer 33 to obtain the collector region 3 and base region 4 of the driver transistor 1 and the output transistor 2, thereby achieving electrical isolation of the devices.

[0079] A base electrode 7 is formed by depositing the base region 4 of the formed driving transistor 1 and the output transistor 2;

[0080] The emitter 8 and the collector 6 are deposited on the emitter region 5 and the collector region 3 of the formed driving tube 1 and output tube 2 respectively;

[0081] A passivation layer 9 is deposited and covered on the collector region 3, base region 4, emitter region 5, base electrode 7 and emitter electrode 8 of the formed driving transistor 1 and output transistor 2;

[0082] Windows are opened on the passivation layer 9 corresponding to the formed base 7 and emitter 8, and metal pads 10 are deposited in the windows.

[0083] The above-mentioned deposition and etching methods can be used in related methods for preparing discrete integrated gallium nitride Darlington transistors.

[0084] (2) After the driver tube 1 and the output tube 2 are prepared, the emitter 8 of the driver tube 1 and the base 7 of the output tube 2 are electrically interconnected, the base 7 of the driver tube 1 is led out as the base 7 of the Darlington transistor, the emitter 8 of the output tube 2 is led out as the emitter 8 of the Darlington transistor, and the common collector 6 of the driver tube 1 and the output tube 2 is led out as the collector 6 of the Darlington transistor, finally obtaining an on-chip integrated Darlington transistor.

[0085] The emitter 8 of the driving transistor 1 and the base 7 of the output transistor 2 can be directly interconnected by preparing a connecting metal layer on the chip, or they can be interconnected by metal bonding after the device is prepared.

[0086] Based on the above structural design and preparation method, the drive tube and output tube are prepared. Figure 12 The following is the common emitter output curve of the driver tube. B =0.7 μA, V CE =35 V, the maximum common emitter DC current gain is achieved, and the maximum gain is 21; Figure 13 The following is the common emitter output curve of the output tube. B =9 μA, V CE=35 V, the maximum common emitter DC current gain is achieved, and the maximum gain is 102. The common emitter output curve of the discrete integrated gallium nitride Darlington transistor composed of the above two transistors is shown in the figure below. Figure 14 As shown, when it works at I B =0.6 μA, V CE =55 V, the maximum common emitter DC current gain is reached, and the maximum gain is about 1900. It can be seen that the maximum common emitter DC current gain of the GaN Darlington transistor is approximately the product of the maximum common emitter DC current gains of the driver tube and the output tube, which greatly improves the DC current amplification factor of the GaN bipolar transistor.

[0087] In summary, the gallium nitride Darlington transistor provided by the present invention interconnects two gallium nitride bipolar transistors through discrete integration or on-chip integration, achieving two-stage amplification of the input current, significantly improving the amplification factor of the transistor, and can achieve amplification of small signals, solving the problem of insufficient amplification factor of a single gallium nitride bipolar transistor.

[0088] According to the description and drawings of the present invention, those skilled in the art can easily manufacture or use the gallium nitride Darlington transistor and the preparation method thereof of the present invention, and can produce the positive effects described in the present invention.

[0089] Unless otherwise specified, in the present invention, if there are terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicating orientation or positional relationships, they are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the orientation or positional relationships in the present invention are only used for illustrative purposes and cannot be understood as limiting this patent. For ordinary technicians in this field, they can understand the specific meanings of the above terms in conjunction with the drawings and according to specific circumstances.

[0090] Unless otherwise specified or limited, the terms "disposed," "connected," and "connected" in this disclosure should be interpreted broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediary, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0091] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be construed as limiting the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims. Persons skilled in the art will appreciate that improvements and modifications may be made without departing from the spirit and scope of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A gallium nitride Darlington transistor, characterized in that: Comprising a driving tube (1) and an output tube (2), the gallium nitride semiconductor epitaxial structures of the driving tube (1) and the output tube (2) each comprise a collector region (3), a base region (4) and an emitter region (5) stacked from bottom to top, and the electrode structures of the driving tube (1) and the output tube (2) each comprise a collector (6) connected to the collector region (3), a base (7) connected to the base region (4) and an emitter (8) connected to the emitter region (5); The emitter (8) of the driving tube (1) is electrically connected to the base (7) of the output tube (2); the base (7) of the driving tube (1) serves as the base (7) of the Darlington transistor; the emitter (8) of the output tube (2) serves as the emitter (8) of the Darlington transistor; the collector (6) of the driving tube (1) and the collector (6) of the output tube (2) are connected in parallel to serve as at least part of the collector (6) of the Darlington transistor; the area of ​​the emitter region (5) is the area of ​​the active region; the area of ​​the active region of the output tube (2) is n times the area of ​​the active region of the driving tube (1), and n>1.

2. The gallium nitride Darlington transistor according to claim 1, wherein: The Darlington transistor comprises a package tube shell and a driver tube (1) and an output tube (2) which are separately integrated on a metal electrode region (11) of the package tube shell. The metal electrode region (11) of the package tube shell is respectively fixed to and electrically interconnected with the collectors (6) of the driver tube (1) and the output tube (2); the collectors (6) of the driver tube (1) and the output tube (2) and the metal electrode region (11) of the package tube shell are connected in parallel as the collector (6) of the Darlington transistor.

3. The gallium nitride Darlington transistor according to claim 1, wherein: The Darlington transistor comprises a driving tube (1) and an output tube (2) which are integrated on-chip on the same wafer, wherein the driving tube (1) and the output tube (2) share a collector region (3) and a collector electrode (6).

4. The gallium nitride Darlington transistor according to claim 1, wherein: The collector region (3) comprises a substrate (31), a buffer layer (32) and a first gallium nitride semiconductor layer (33) stacked from bottom to top, the substrate (31) is made of gallium nitride, the first gallium nitride semiconductor layer (33) is doped with an n-type, the base region (4) comprises a second gallium nitride semiconductor layer (41) doped with a p-type, and the emitter region (5) comprises a third gallium nitride semiconductor layer (51) doped with an n-type.

5. The gallium nitride Darlington transistor according to claim 4, wherein: The components of the first gallium nitride semiconductor layer (33) include In x1 Al y1 Ga 1-x1-y1 N, 0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1, and is doped with an n-type dopant; the components of the second gallium nitride semiconductor layer (41) include In x2 Al y2 Ga 1-x2-y1=2 N, 0≤x2≤1, 0≤y2≤1, 0≤x2+y2≤1, and is doped with a p-type dopant; the components of the third gallium nitride semiconductor layer (51) include In x3 Al y3 Ga 1-x3-y3 N, 0≤x3≤1, 0≤y3≤1, 0≤x3+y3≤1, and is doped with an n-type dopant.

6. The gallium nitride Darlington transistor according to claim 5, wherein: The n-type dopant includes at least one of Si, Ge, Sn, and Se, and the p-type dopant includes at least one of Mg, Zn, Ca, Sr, and Ba.

7. The gallium nitride Darlington transistor according to claim 1, wherein: The collector region (3), base region (4), emitter region (5), base electrode (7) and emitter electrode (8) are covered with a passivation layer (9); windows are provided on the passivation layer (9) corresponding to the base electrode (7) and emitter electrode (8), and metal pads (10) are deposited in the windows.

8. A method for preparing a gallium nitride Darlington transistor according to any one of claims 1 to 7, characterized in that: This includes any of the following methods: Method 1: The driving tube (1) and the output tube (2) are prepared independently. After the preparation is completed, a conductive adhesive is applied to the collectors (6) of the driving tube (1) and the output tube (2). The driving tube (1) and the output tube (2) coated with the conductive adhesive are placed on the metal electrode area (11) of the package tube shell with the collector (6) facing downward. The fixing and electrical interconnection of the driving tube (1), the output tube (2) and the package tube shell are achieved by heating and baking. The emitter (8) of the driving tube (1) and the base (7) of the output tube (2) are electrically interconnected, the base (7) of the driving tube (1) is led out as the base (7) of the Darlington transistor, the emitter (8) of the output tube (2) is led out as the emitter (8) of the Darlington transistor, the collector (6) of the driving tube (1) and the output tube (2) and the metal electrode region (11) are connected in parallel and led out as the collector (6) of the Darlington transistor, and finally a discrete integrated Darlington transistor is obtained; Method 2: A shared collector region (3) and a collector (6) are used, and a driving tube (1) and an output tube (2) are simultaneously prepared on the same wafer. After the preparation is completed, the emitter (8) of the driving tube (1) and the base (7) of the output tube (2) are electrically interconnected, the base (7) of the driving tube (1) is led out as the base (7) of the Darlington transistor, the emitter (8) of the output tube (2) is led out as the emitter (8) of the Darlington transistor, and the shared collector (6) of the driving tube (1) and the output tube (2) is led out as the collector (6) of the Darlington transistor, and finally an on-chip integrated Darlington transistor is obtained.

9. The method for preparing a gallium nitride Darlington transistor according to claim 8, wherein: In method 1, the preparation method of the driving tube (1) or the output tube (2) includes: A buffer layer (32), a first gallium nitride semiconductor layer (33), a second gallium nitride semiconductor layer (41), and a third gallium nitride semiconductor layer (51) are sequentially grown on a substrate (31) to form a prototype of a collector region (3), a base region (4), and an emitter region (5); Etching and removing a portion of the periphery of the third gallium nitride semiconductor layer (51) to obtain a formed emitter region (5) and expose the mesa of the base region (4); Etching and removing a portion of the periphery of the second gallium nitride semiconductor layer (41) and the first gallium nitride semiconductor layer (33) to obtain a formed collector region (3) and a base region (4), thereby achieving electrical isolation of the device; Depositing a base electrode (7) on the mesa of the formed base region (4); Depositing an emitter (8) and a collector (6) on the formed emitter region (5) and collector region (3) respectively; Depositing a passivation layer (9) on the formed collector region (3), base region (4), emitter region (5), base electrode (7) and emitter electrode (8); Windows are opened on the passivation layer (9) corresponding to the formed base (7) and emitter (8), and metal pads (10) are deposited in the windows.

10. The method for preparing a gallium nitride Darlington transistor according to claim 8, wherein: In the second method, the preparation method of the driving tube (1) and the output tube (2) includes: A buffer layer (32), a first gallium nitride semiconductor layer (33), a second gallium nitride semiconductor layer (41), and a third gallium nitride semiconductor layer (51) are sequentially grown on the same substrate (31), and the prototypes of the collector region (3), base region (4), and emitter region (5) of the driver tube (1) and the output tube (2) are simultaneously formed; Etching and removing a portion of the periphery and the middle of the third gallium nitride semiconductor layer (51) to obtain the shaped emission regions (5) of the driving tube (1) and the output tube (2), and simultaneously exposing the base regions (4) of the driving tube (1) and the output tube (2); Etching and removing the periphery and a portion of the middle of the second gallium nitride semiconductor layer (41) and the first gallium nitride semiconductor layer (33) to obtain the collector region (3) and base region (4) of the formed driving tube (1) and output tube (2), thereby achieving electrical isolation of the device; Depositing a base electrode (7) on the base region (4) of the formed driving tube (1) and the output tube (2); Depositing an emitter (8) and a collector (6) on the emitter region (5) and the collector region (3) of the formed drive tube (1) and output tube (2), respectively; Depositing a passivation layer (9) on the collector region (3), base region (4), emitter region (5), base electrode (7) and emitter electrode (8) of the formed driving tube (1) and output tube (2); Windows are opened on the passivation layer (9) corresponding to the formed base (7) and emitter (8), and metal pads (10) are deposited in the windows.

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