A system chip reset control structure based on PLL and FLASH

Abstract

The present invention belongs to the technical field of integrated circuit design, and specifically discloses a system chip reset control structure based on PLL and FLASH, comprising a PLL module, a FLASH controller, a reset control unit, and a gated clock. Based on a PLL lock signal and a FLASH initialization signal, the reset signals of various levels are sequentially released during system startup, ensuring stable initialization of key modules and resources of the system chip at each stage. The number of reset release cycles and the gated clock are set by a delay counter, compensating for the timing delay of the reset tree and the clock tree, ensuring synchronous release of the reset signal across the entire chip, and relaxing the timing constraints of back-end layout and routing. The reset control structure of the present invention improves the reliability of system chip startup, can effectively prevent hardware failures caused by reset sequence errors or unstable timing, and is suitable for complex multi-clock domain system chips with PLL and FLASH memories.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a system chip reset control structure based on PLL and FLASH. Background Art

[0002] In modern system-on-chips (SoCs), PLLs (phase-locked loops) and flash memory (Flash Memory) are two key components that play a vital role. The PLL is responsible for providing a stable clock signal for the SoC, while the Flash Memory is primarily used to store program code and data. In SoCs with PLLs and Flash, the release of reset signals must be controlled according to a strict sequence and timing to ensure that all key modules are released from reset sequentially after a stable clock signal and initialization are complete, ensuring the proper operation of the SoC. For complex SoCs, a single reset release cycle is insufficient to effectively transmit the reset release signal to all registers throughout the chip. Even if multi-cycle reset release is implemented, circuit complexity and significant routing delays can still increase the delay between the clock and reset trees, leading to inconsistent reset release across various systems. Summary of the Invention

[0003] In response to the problems existing in the prior art, the present invention provides a system chip reset control structure based on PLL and FLASH. This design addresses the startup reset sequence problem of modern system chips with PLL and FLASH memory, and provides an effective reset sequence control structure. Through the combined control of the PLL lock signal and the FLASH initialization signal, the system chip is ensured to release the reset signal in sequence after the clock is stabilized and fully initialized, ensuring stable system startup. To address the problem of single-cycle reset release being unable to be completed due to a high number of registers, complex logic, and high clock frequency, the present invention provides a multi-cycle reset release structure that can achieve multi-cycle reset release, determine the number of cycles for multi-cycle reset release, and implement a gated clock circuit during the reset release period to compensate for the delay between the reset tree and the clock number. This effectively resolves the metastable state problem and relaxes the constraints on back-end layout and routing.

[0004] Specifically, the present invention provides a system chip reset control structure based on PLL and FLASH, including a PLL module, a FLASH controller, a reset control unit and a gated clock;

[0005] The PLL module and the FLASH controller are both electrically connected to the reset control unit; the PLL module is used to generate a system clock signal, which includes a processor clock signal, a FLASH clock signal and a peripheral clock signal;

[0006] The FLASH controller is used to initialize the FLASH memory;

[0007] The reset control unit includes an initial reset control unit, a first-stage reset control unit, a second-stage reset control unit, and a multi-cycle reset release structure; the multi-cycle reset release structure is used to complete the reset and release of the third-stage reset control unit; by gradually completing the reset and release of the initial reset control unit, the reset and release of the PLL module, the reset and release of the first-stage reset control unit, the initialization of the FLASH controller, the reset and release of the second-stage reset control unit, and the reset and release of the third-stage reset control unit, the system is stably started;

[0008] The gated clock is used to compensate for the delay of the peripheral and / or processor reset tree and the clock number.

[0009] Furthermore, the initial reset control unit is triggered by an external reset signal, and the external reset signal is connected to the initial reset control unit through a logic gate; the external reset signal includes a source reset signal, a watchdog and a soft reset signal, and the source reset signal is connected to the logic gate after the burrs are filtered out by a delay filter.

[0010] Furthermore, the initial reset control unit is electrically connected to the PLL module and the first-stage reset control unit; after being reset, the initial reset control unit outputs a PLL reset signal and an initial reset signal, and triggers the PLL module through the PLL reset signal, so that the PLL module completes the reset and outputs the processor clock signal, the FLASH clock signal, the peripheral clock signal and the PLL lock signal; the input end of the first-stage reset control unit is connected to the PLL lock signal, the FLASH clock signal and the initial reset signal, and when the first-stage reset control unit receives the PLL lock signal, it starts the first-stage reset, and after completion, it outputs the FLASH controller reset signal and the first-stage reset signal, and the first-stage reset is released.

[0011] Furthermore, the second-stage reset control unit is electrically connected to the FLASH controller and the first-stage reset control unit; the input end of the FLASH controller is connected to the FLASH clock signal and the FLASH controller reset signal, and the FLASH controller is triggered by the FLASH controller reset signal to complete initialization, and outputs a FLASH initialization completion signal or a FLASH initialization timeout signal; the input end of the second-stage reset control unit is connected to the first-stage reset signal, the FLASH initialization completion signal or the FLASH initialization timeout signal, and the second-stage reset control unit completes the second-stage reset through the first-stage reset signal, the FLASH initialization completion signal, the FLASH initialization timeout signal and the off-chip input clock signal, and outputs the second-stage reset signal, and the second-stage reset is released.

[0012] Furthermore, the multi-cycle reset release structure includes a delay counter and a third-stage reset control unit; the delay counter is electrically connected to the second-stage reset control unit and the third-stage reset control unit; the delay counter is used to set the number of reset release cycles in the third stage;

[0013] The input end of the multi-cycle reset release structure is connected to the processor clock signal and the peripheral clock signal;

[0014] The input end of the delay counter is connected to the second-stage reset signal. When the delay counter reaches the third-stage reset release cycle number, the third-stage reset signal is output. The input end of the third-stage reset control unit is connected to the third-stage reset signal. After the reset is completed, the peripheral gated clock enable signal, the processor gated clock enable signal, the peripheral reset signal and the processor reset signal are synchronously output, and the third-stage reset release is completed.

[0015] Furthermore, the gated clock input end is connected to the peripheral gated clock enable signal, the processor gated clock enable signal, the peripheral clock signal and the processor clock signal, and its output end is connected to the peripheral and the processor; the gated clock is driven by the peripheral gated clock enable signal and the processor gated clock enable signal, so that the peripheral clock and the processor clock are turned off during the reset release of the peripheral and the processor.

[0016] Furthermore, the number of reset release cycles in the third stage is less than the number of peripheral clock and processor clock shutdown cycles.

[0017] Furthermore, the multi-cycle reset release structure further includes a two-choose-one selector, a first bitwise AND logic, a second bitwise AND logic, a third bitwise AND logic, a first register, a second register, and a third register;

[0018] One end of the delay counter is connected to the output end of the first register, the other end of the delay counter is connected to one end of the two-selector selector, the other end of the two-selector selector is connected to the trigger end of the first register, and the two-selector selector is used to select the count value input to the first register; one end of the first bitwise AND logic is connected to the delay counter, and the other end is connected to the two-selector selector, the reset end of the first register is connected to the second-stage reset signal, when the first register is reset and released, the signal is fed back to the delay counter, and the delay counter starts counting, and when the delay counter reaches the third-stage reset release cycle number, the reset release of the first register is completed, and the third-stage reset signal is output;

[0019] The output end of the first register is connected to the second bitwise AND logic input end and the third bitwise AND logic input end, the second bitwise AND logic output end is connected to the reset end of the second register, the third bitwise AND logic output end is connected to the reset end of the third register, the trigger ends of the second register and the third register are both powered, the second register outputs a peripheral reset signal and a processor reset signal, and the third register outputs a peripheral gated clock enable signal and a processor gated clock enable signal;

[0020] The clock ends of the first register, the second register and the third register are all connected to the peripheral clock signal and the processor clock signal;

[0021] The second register and the third register constitute a third-stage reset control unit.

[0022] Furthermore, the first stage reset control unit includes a five-bit shift register, a fourth register and a fifth register; the five-bit shift register is composed of a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a fifth flip-flop;

[0023] The trigger end of the first trigger is connected to the PLL lock signal, and the trigger ends of the second trigger, the third trigger, the fourth trigger and the fifth trigger are all connected to the output end of the previous trigger; the output end of the fifth trigger is connected to the trigger end of the fourth register, the trigger end of the fifth register is connected to the output end of the fourth register, and the output end of the fifth register outputs the FLASH controller reset signal; the clock ends of the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the fourth register and the fifth register are all connected to the FLASH clock signal, and their reset ends are all connected to the initial reset signal.

[0024] Furthermore, the second stage reset control unit includes a two-bit shift register, an OR logic gate and a sixth register, and the two-bit shift register is composed of a sixth flip-flop and a seventh flip-flop;

[0025] The trigger end of the sixth trigger is connected to the FLASH initialization completion signal, the trigger end of the seventh trigger is connected to the output end of the sixth trigger, the output end of the seventh trigger and the FLASH initialization timeout signal are both connected to the input end of the OR logic gate, the output end of the OR logic gate is connected to the trigger end of the sixth register, and the output end of the sixth register outputs the second stage reset signal; the clock ends of the sixth trigger, the seventh trigger and the sixth register are all connected to the off-chip input clock signal, and their reset ends are all connected to the first stage reset signal.

[0026] Compared with the prior art, the present invention has the following beneficial technical effects:

[0027] The system chip reset control structure based on PLL and FLASH proposed in the present invention gradually releases the reset signal in sequence, ensuring that each module of the system releases the reset signal in sequence under the conditions of clock stability and initialization completion. This phased reset mechanism effectively avoids the situation where the reset signal is released irrationally, ensuring that the system can start stably, and is particularly suitable for system chips with PLL and FLASH memory. The multi-cycle reset release structure proposed in the present invention can realize multi-cycle reset completion logic. For complex circuit systems that cannot complete single-cycle reset release due to large area, large number of registers, large number of logic resources and high clock frequency, multi-cycle reset release can be realized, and the number of cycles of multi-cycle reset release can be determined, as well as a gated clock circuit during reset release to compensate for the delay of the reset tree and the number of clocks, effectively solving the metastable problem and relaxing the constraints on the back-end layout and wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0029] Figure 1 This is the overall block diagram of the reset control structure based on PLL and FLASH provided by the present invention;

[0030] Figure 2 This is a structural diagram of the reset circuit provided by the present invention;

[0031] Figure 3 This is a circuit diagram of a multi-cycle reset release structure provided by the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0034] In the description of the present invention, it should be noted that the terms "upper," "lower," "left," "right," "inner," "outer," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and simplify the description, and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0036] The proposed PLL- and FLASH-based SoC reset control structure uses a phased reset release mechanism to ensure stable initialization of the SoC during each reset phase, ensuring system stability. Configurable reset cycles and a gated clock mechanism mitigate delays between the clock and reset trees, effectively reducing layout and routing constraints. This reset control structure is ideal for complex SoCs, particularly those involving multiple clock domains and FLASH memory, significantly improving the reliability and stability of SoC startup.

[0037] Specifically, Figures 1 to 3In the figure, CPU_CLK is the processor clock signal; FLASH_CLK is the FLASH clock signal; FPLL_LOCK is the PLL lock signal; PLL_nrst is the PLL reset signal; Flash_nrst is the FLASH controller reset signal; flash_init_finish is the FLASH initialization completion signal; flash_timeout is the FLASH initialization timeout signal; CPU_nrst is the processor reset signal; CPU_CE is the processor gated clock enable signal; Peripheral_nrst is the peripheral reset signal; Peripheral_CE is the peripheral gated clock enable signal; Peripheral_CLK is the peripheral clock signal; flash_rst is the initial reset signal; nrst_firststage is the first stage reset signal; nrst_secondstage is the second stage reset signal; clkin is the off-chip input clock signal; nrst_final is the third stage reset signal.

[0038] A PLL and FLASH-based system chip reset control structure includes a PLL module, a FLASH controller, a reset control unit, and a gated clock. By hierarchically controlling the gradual release of the reset signal, the stability and reliability of the system chip during the startup process are ensured.

[0039] The PLL module and the FLASH controller are both electrically connected to the reset control unit; the PLL module is used to generate a system clock signal, which includes a processor clock signal CPU_CLK, a FLASH clock signal FLASH_CLK and a peripheral clock signal Peripheral_CLK;

[0040] Specifically, the PLL module ensures the stable output of the clock signal through the PLL lock signal FPLL_LOCK. The system startup process depends on the clock stability of the PLL module. The reset is not released until the PLL lock signal FPLL_LOCK is valid.

[0041] The FLASH controller is used to initialize the FLASH memory and generate the FLASH initialization completion signal flash_init_finish;

[0042] The reset control unit includes an initial reset control unit, a first-stage reset control unit, a second-stage reset control unit, and a multi-cycle reset release structure; the multi-cycle reset release structure is used to complete the reset and release of the third-stage reset control unit; by gradually completing the reset and release of the initial reset control unit, the reset and release of the PLL module, the reset and release of the first-stage reset control unit, the initialization of the FLASH controller, the reset and release of the second-stage reset control unit, and the reset and release of the third-stage reset control unit, the system is stably started;

[0043] Clock gating is used to compensate for delays in the peripheral and processor reset tree and clock counts.

[0044] In the present invention, the first stage reset release, that is, the system startup process, depends on the clock stability of the PLL module, and the first stage reset and release will not start until the PLL lock signal FPLL_LOCK is valid; in the second stage reset release process, the second stage reset release depends on the FLASH initialization completion signal flash_init_finish, to ensure that the system is ready to load instructions from the memory after reset; after the first stage reset release and the second stage reset release are completed, the system enters the final reset release stage, that is, the third stage reset release, and synchronously releases the peripheral and processor reset signals and the peripheral and processor gated clock enable signals to ensure stable startup of the system; the reset control unit ensures that the system can continue to start only after it is fully initialized and stabilized at each stage through hierarchical release of the reset signal, avoiding the problems of timing conflicts and reset signal inconsistency.

[0045] In the present invention, the entire reset and reset release process is precisely controlled by the reset control unit, which controls the release of the reset signals of the initial reset control unit, the first-stage reset control unit, the second-stage reset control unit, and the third-stage reset control unit in stages, thereby completing the reset operation in a reasonable sequence within multiple clock cycles. During the reset process of the processor and various peripherals, the clock is controlled by adopting a gated clock to implement a multi-cycle reset release mechanism, effectively compensating for the timing delay between the reset tree and the clock tree, ensuring the synchronization of the reset signal and the clock signal, and avoiding metastable phenomena.

[0046] like Figure 1 As shown, the initial reset control unit is triggered by an external reset signal, and the external reset signal is connected to the initial reset control unit through a logic gate; the external reset signal includes a source reset signal, a watchdog and a soft reset signal, and the source reset signal is connected to the logic gate after being filtered out of glitches by a delay filter.

[0047] The initial reset control unit is electrically connected to the PLL module and the first-stage reset control unit; after the initial reset control unit is reset, the PLL reset signal PLL_nrst and the initial reset signal flash_rst are output, and the PLL module is triggered by the PLL reset signal PLL_nrst, so that the PLL module completes the reset and outputs the processor clock signal CPU_CLK, the FLASH clock signal FLASH_CLK, the peripheral clock signal Peripheral_CLK and the PLL lock signal FPLL_LOCK; the input end of the first-stage reset control unit is connected to the PLL lock signal FPLL_LOCK, the FLASH clock signal FLASH_CLK and the initial reset signal flash_rst. When the first-stage reset control unit receives the PLL lock signal FPLL_LOCK, the first-stage reset is started, and after completion, the FLASH controller reset signal Flash_nrst and the first-stage reset signal nrst_firststage are output, and the first-stage reset is released.

[0048] Specifically, the external reset signal composed of the source reset signal, the watchdog timer and the soft reset signal triggers the reset of the initial reset control unit through the logic gate, and outputs the PLL reset signal PLL_nrst and the initial reset signal flash_rst after the reset is released.

[0049] The second-stage reset control unit is electrically connected to the FLASH controller and the first-stage reset control unit; the input end of the FLASH controller is connected to the FLASH clock signal FLASH_CLK and the FLASH controller reset signal Flash_nrst, and the FLASH controller is triggered by the FLASH controller reset signal Flash_nrst to complete initialization, and outputs the FLASH initialization completion signal flash_init_finish or the FLASH initialization timeout signal flash_timeout; the input end of the second-stage reset control unit is connected to the first-stage reset signal nrst_firststage, the FLASH initialization completion signal flash_init_finish or the FLASH initialization timeout signal flash_timeout, and the second-stage reset control unit completes the second-stage reset through the first-stage reset signal nrst_firststage, the FLASH initialization completion signal flash_init_finish, the FLASH initialization timeout signal flash_timeout and the off-chip input clock signal clkin, and outputs the second-stage reset signal nrst_secondstage, and the second-stage reset is released.

[0050] The multi-cycle reset release structure includes a delay counter and a third-stage reset control unit; the delay counter is electrically connected to the second-stage reset control unit and the third-stage reset control unit; the delay counter is used to set the number of third-stage reset release cycles; the input end of the multi-cycle reset release structure is connected to the processor clock signal CPU_CLK and the peripheral clock signal Peripheral_CLK; the input end of the delay counter is connected to the second-stage reset signal nrst_secondstage, and when the delay counter reaches the third-stage reset release cycle number, the third-stage reset signal nrst_final is output, and the input end of the third-stage reset control unit is connected to the third-stage reset signal nrst_final. After the reset is completed, the peripheral gated clock enable signal Peripheral_CE, the processor gated clock enable signal CPU_CE, the peripheral reset signal Peripheral_nrst and the processor reset signal CPU_nrst are synchronously output, and the third-stage reset release is completed.

[0051] Figure 2 As shown, the first-stage reset control unit includes a five-bit shift register, a fourth register and a fifth register; the five-bit shift register consists of a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a fifth flip-flop; the trigger end of the first flip-flop is connected to the PLL lock signal FPLL_LOCK, and the trigger ends of the second flip-flop, the third flip-flop, the fourth flip-flop and the fifth flip-flop are all connected to the output end of the previous flip-flop; the output end of the fifth flip-flop is connected to the trigger end of the fourth register, the trigger end of the fifth register is connected to the output end of the fourth register, and the output end of the fifth register outputs the FLASH controller reset signal Flash_nrst; the clock ends of the first flip-flop, the second flip-flop, the third flip-flop, the fourth flip-flop, the fifth flip-flop, the fourth register and the fifth register are all connected to the FLASH clock signal FLASH_CLK, and their reset ends are all connected to the initial reset signal flash_rst.

[0052] The second-stage reset control unit includes a two-bit shift register, an OR logic gate and a sixth register. The two-bit shift register is composed of a sixth flip-flop and a seventh flip-flop; the trigger end of the sixth flip-flop is connected to the FLASH initialization completion signal flash_init_finish, the trigger end of the seventh flip-flop is connected to the output end of the sixth flip-flop, the output end of the seventh flip-flop and the FLASH initialization timeout signal flash_timeout are both connected to the input end of the OR logic gate, the output end of the OR logic gate is connected to the trigger end of the sixth register, and the output end of the sixth register outputs the second-stage reset signal nrst_secondstage; the clock ends of the sixth flip-flop, the seventh flip-flop and the sixth register are all connected to the off-chip input clock signal clkin, and their reset ends are all connected to the first-stage reset signal nrst_firststage.

[0053] Specifically, after the clock output by the PLL module to the FLASH memory stabilizes, it outputs the PLL_LOCK signal FPLL_LOCK, triggering the first trigger of the first-stage reset control unit, and transmitting it to the fifth trigger in sequence. The output signal of the fifth trigger passes through the fourth register and the fifth register twice, and then outputs the FLASH controller reset signal Flash_nrst; after the FLASH controller is reset, it initializes the FLASH memory and outputs the FLASH initialization completion signal flash_init_finish and the FLASH initialization timeout signal flash_timeout; the second-stage reset control unit triggers the sixth trigger through the FLASH initialization completion signal flash_init_finish, and transmits it to the seventh trigger. The output signal of the seventh trigger and the FLASH initialization timeout signal flash_timeout are both connected to one end of the OR logic gate, and output to the sixth register through the OR logic gate. After passing through the sixth register once, the second-stage reset signal nrst_secondstage is output, and then the third-stage reset signal nrst_final is reset and output through the delay timer.

[0054] In the present invention, the FLASH initialization timeout signal flash_timeout means that the FLASH controller does not send an initialization completion signal after initialization for a period of time, which is obtained by counting the clock counter of the off-chip input clock signal clkin, and the count value is determined by the FLASH memory initialization time.

[0055] like Figure 3 As shown, the multi-cycle reset release structure includes a two-to-one selector, a first bitwise AND logic, a second bitwise AND logic, a third bitwise AND logic, a first register, a second register, and a third register;

[0056] One end of the delay counter is connected to the output end of the first register, the other end of the delay counter is connected to one end of the two-selection selector, the other end of the two-selection selector is connected to the trigger end of the first register, and the two-selection selector is used to select the count value input to the first register; one end of the first bitwise AND logic is connected to the delay counter, and the other end is connected to the two-selection selector. The reset end of the first register is connected to the second-stage reset signal nrst_secondstage. When the first register is reset and released, the signal is fed back to the delay counter, and the delay counter starts counting. When the delay counter reaches the set third-stage reset release cycle number, the reset release of the first register is completed, and the third-stage reset signal nrst_final is output;

[0057] The output end of the first register is connected to the second bitwise AND logic input end and the third bitwise AND logic input end, the second bitwise AND logic output end is connected to the reset end of the second register, the third bitwise AND logic output end is connected to the reset end of the third register, the trigger ends of the second register and the third register are both powered, the second register outputs the peripheral reset signal Peripheral_nrst and the processor reset signal CPU_nrst, and the third register outputs the peripheral gated clock enable signal Peripheral_CE and the processor gated clock enable signal CPU_CE; the clock ends of the first register, the second register and the third register are all connected to the peripheral clock signal Peripheral_CLK and the processor clock signal CPU_CLK; the second register and the third register constitute a third-stage reset control unit.

[0058] Specifically, the gated clock input end is connected to the peripheral gated clock enable signal Peripheral_CE, the processor gated clock enable signal CPU_CE, the peripheral clock signal Peripheral_CLK and the processor clock signal CPU_CLK, and the gated clock output end is connected to the peripheral and the processor; the gated clock is driven by the peripheral gated clock enable signal Peripheral_CE and the processor gated clock enable signal CPU_CE, so that the peripheral clock and the processor clock are turned off during the reset release of the peripheral and the processor.

[0059] In the present invention, the delay counter takes the reset release cycle number set as 16 clock cycles as an example; the time for the peripheral and processor clocks to be turned off is from the start of the third stage reset release until the delay counter calculates the set maximum number of cycles, which is used to make up for the delay of the clock tree and the reset tree, and the third stage reset release cycle number set by the delay counter is less than the clock off cycle number of the peripheral and processor, and the gating of the peripheral and processor clocks lasts for 28 clock cycles; the delay counter is used to record the number of cycles, and starts counting after the third stage reset signal is released, and remains at 0 after completing the counting of 32 cycles until the reset signal is generated again and the counting starts again; the first bitwise AND logic generates a control signal according to the number of cycles recorded by the delay counter. The first bitwise AND logic indicates that the five-bit counter values ​​are all ANDed one by one. When the five-bit data are all 1, that is, when the count reaches 31, a high voltage is generated. A level signal is generated, and it is a low level at other times; the third bitwise AND logic indicates that the upper three-digit counter values ​​are ANDed one by one, and when the upper three-digit data are all 1, that is, when the count reaches 28 or above, a high level signal is generated, and it is a low level at other times; the second bitwise AND logic indicates that the highest bit counter value is 1, that is, when the count reaches 16 or above, a high level signal is generated, and it is a low level at other times; the two-selector selector is used to select the count value input to the first register. When the count value of the delay counter has not reached the maximum value, the control signal of the two-selector selector is 0, and the output of the delay counter is selected as the output of the two-selector selector. The value of the delay counter continues to increase by 1 with the arrival of the rising edge of the clock until the value of the delay counter reaches the maximum value. The value of the control signal of the two-selector selector is sent to change, and the two-selector selector will select the current count value as the output and keep the output value unchanged until the reset signal arrives again.

[0060] Specifically, the second-stage reset signal nrst_secondstage input at the reset end of the first register changes from a low level to a high level, that is, after the reset completion signal is generated, the delay counter starts counting. When the count value of the delay counter reaches the set reset cancellation cycle number, the reset cancellation of the first register is completed, the third-stage reset signal is completed and released, and the third-stage reset signal nrst_final is output. At this time, the processor and peripheral reset signals are still 0, and the second register and the third register beat the reset signal and the clock signal to achieve synchronous release and reduce the probability of metastable state.

[0061] The number of reset release cycles in the third stage is less than the number of clock shutdown cycles of the peripherals and processors, that is, the reset release count cycle value of the peripheral reset signal Peripheral_nrst and the processor reset signal CPU_nrst is less than the count cycle value of the peripheral gated clock enable signal Peripheral_CE and the processor gated clock enable signal CPU_CE, to ensure that the reset release signal arrives first and the clock signal arrives later. After the clock signal arrives, the reset release is truly completed, thereby achieving the effect of compensating for the delay of the clock tree and the reset tree.

[0062] The above embodiments are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions or replacements made by those skilled in the art based on the technical features of the present invention fall within the scope of protection of the present invention.

Claims

1. A system chip reset control structure based on PLL and FLASH, characterized in that: Including PLL module, FLASH controller, reset control unit and gated clock; The PLL module and the FLASH controller are both electrically connected to the reset control unit; the PLL module is used to generate a system clock signal, which includes a processor clock signal, a FLASH clock signal and a peripheral clock signal; The FLASH controller is used to initialize the FLASH memory; The reset control unit includes an initial reset control unit, a first-stage reset control unit, a second-stage reset control unit, and a multi-cycle reset release structure; the multi-cycle reset release structure is used to complete the reset and release of the third-stage reset control unit; by gradually completing the reset and release of the initial reset control unit, the reset and release of the PLL module, the reset and release of the first-stage reset control unit, the initialization of the FLASH controller, the reset and release of the second-stage reset control unit, and the reset and release of the third-stage reset control unit, the system is stably started; The initial reset control unit is electrically connected to the PLL module and the first-stage reset control unit; after being reset, the initial reset control unit outputs a PLL reset signal and an initial reset signal, and triggers the PLL module through the PLL reset signal, so that the PLL module completes the reset and outputs the processor clock signal, the FLASH clock signal, the peripheral clock signal and the PLL lock signal; the input end of the first-stage reset control unit is connected to the PLL lock signal, the FLASH clock signal and the initial reset signal, and when the first-stage reset control unit receives the PLL lock signal, it starts the first-stage reset, and after completion, it outputs the FLASH controller reset signal and the first-stage reset signal, and the first-stage reset is released; The second-stage reset control unit is electrically connected to the FLASH controller and the first-stage reset control unit; the input end of the FLASH controller is connected to the FLASH clock signal and the FLASH controller reset signal, and the FLASH controller is triggered by the FLASH controller reset signal to complete initialization and output a FLASH initialization completion signal or a FLASH initialization timeout signal; the input end of the second-stage reset control unit is connected to the first-stage reset signal, the FLASH initialization completion signal or the FLASH initialization timeout signal, and the second-stage reset control unit completes the second-stage reset through the first-stage reset signal, the FLASH initialization completion signal, the FLASH initialization timeout signal and the off-chip input clock signal, and outputs the second-stage reset signal, and the second-stage reset release is completed; The gated clock is used to compensate for the delay of the peripheral and processor reset tree and clock number.

2. The system chip reset control structure based on PLL and FLASH according to claim 1, characterized in that: The initial reset control unit is triggered by an external reset signal, and the external reset signal is connected to the initial reset control unit through a logic gate; the external reset signal includes a source reset signal, a watchdog and a soft reset signal, and the source reset signal is connected to the logic gate after being filtered out of glitches by a delay filter.

3. The system chip reset control structure based on PLL and FLASH according to claim 1, characterized in that: The multi-cycle reset release structure includes a delay counter and a third-stage reset control unit; the delay counter is electrically connected to the second-stage reset control unit and the third-stage reset control unit; the delay counter is used to set the number of reset release cycles in the third stage; The input end of the multi-cycle reset release structure is connected to the processor clock signal and the peripheral clock signal; The input end of the delay counter is connected to the second-stage reset signal. When the delay counter reaches the third-stage reset release cycle number, the third-stage reset signal is output. The input end of the third-stage reset control unit is connected to the third-stage reset signal. After the reset is completed, the peripheral gated clock enable signal, the processor gated clock enable signal, the peripheral reset signal and the processor reset signal are synchronously output, and the third-stage reset release is completed.

4. The system chip reset control structure based on PLL and FLASH according to claim 3, characterized in that: The gated clock input end is connected to the peripheral gated clock enable signal, the processor gated clock enable signal, the peripheral clock signal and the processor clock signal, and its output end is connected to the peripheral and the processor; The gated clock is driven by the peripheral gated clock enable signal and the processor gated clock enable signal, so that the peripheral clock and the processor clock are turned off during the reset release of the peripheral and the processor.

5. The system chip reset control structure based on PLL and FLASH according to claim 4, characterized in that: The number of reset release cycles in the third stage is less than the number of shutdown cycles of the peripheral clock and the processor clock.

6. The system chip reset control structure based on PLL and FLASH according to claim 3, characterized in that: The multi-cycle reset release structure further includes a two-to-one selector, a first bitwise AND logic, a second bitwise AND logic, a third bitwise AND logic, a first register, a second register, and a third register; One end of the delay counter is connected to the output end of the first register, the other end of the delay counter is connected to one end of the two-selector selector, the other end of the two-selector selector is connected to the trigger end of the first register, and the two-selector selector is used to select the count value input to the first register; one end of the first bitwise AND logic is connected to the delay counter, and the other end is connected to the two-selector selector, the reset end of the first register is connected to the second-stage reset signal, when the first register is reset and released, the signal is fed back to the delay counter, and the delay counter starts counting, and when the delay counter reaches the third-stage reset release cycle number, the reset release of the first register is completed, and the third-stage reset signal is output; The output end of the first register is connected to the second bitwise AND logic input end and the third bitwise AND logic input end, the second bitwise AND logic output end is connected to the reset end of the second register, the third bitwise AND logic output end is connected to the reset end of the third register, the trigger ends of the second register and the third register are both powered, the second register outputs a peripheral reset signal and a processor reset signal, and the third register outputs a peripheral gated clock enable signal and a processor gated clock enable signal; The clock ends of the first register, the second register and the third register are all connected to the peripheral clock signal and the processor clock signal; The second register and the third register constitute a third-stage reset control unit.

7. The system chip reset control structure based on PLL and FLASH according to claim 1, characterized in that: The first stage reset control unit includes a five-bit shift register, a fourth register and a fifth register; the five-bit shift register is composed of a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a fifth flip-flop; The trigger end of the first trigger is connected to the PLL lock signal, and the trigger ends of the second trigger, the third trigger, the fourth trigger and the fifth trigger are all connected to the output end of the previous trigger; the output end of the fifth trigger is connected to the trigger end of the fourth register, the trigger end of the fifth register is connected to the output end of the fourth register, and the output end of the fifth register outputs the FLASH controller reset signal; the clock ends of the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the fourth register and the fifth register are all connected to the FLASH clock signal, and their reset ends are all connected to the initial reset signal.

8. The system chip reset control structure based on PLL and FLASH according to claim 1, characterized in that: The second stage reset control unit includes a two-bit shift register, an OR logic gate and a sixth register, wherein the two-bit shift register is composed of a sixth flip-flop and a seventh flip-flop; The trigger end of the sixth trigger is connected to the FLASH initialization completion signal, the trigger end of the seventh trigger is connected to the output end of the sixth trigger, the output end of the seventh trigger and the FLASH initialization timeout signal are both connected to the input end of the OR logic gate, the output end of the OR logic gate is connected to the trigger end of the sixth register, and the output end of the sixth register outputs the second stage reset signal; the clock ends of the sixth trigger, the seventh trigger and the sixth register are all connected to the off-chip input clock signal, and their reset ends are all connected to the first stage reset signal.

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