Circuit netlist generation method supporting deep learning model multi-stage reasoning

Abstract

The invention discloses a circuit netlist generation method supporting deep learning model multi-stage reasoning, and belongs to the technical field of electronic circuit design and automation, and the method comprises the steps: obtaining a circuit diagram image through optical scanning, carrying out the preprocessing of the image, carrying out the recognition of a component through a deep learning model YOLOv5, and determining the boundary frame coordinates and class information. And further performing port fine identification on the component, and determining the position and the direction of the port. And eliminating character interference by using an optical character recognition technology, performing wire recognition, including Hough straight line detection and jumper processing, and determining starting point and ending point coordinates of the wire. And matching the identification results of the components, the ports and the wires, constructing a topological structure of a circuit diagram, finally generating a circuit netlist, and performing error elimination and JSON format output. According to the method, automatic netlist generation of the analog circuit diagram can be realized, the analog circuit diagram file is converted into the netlist file with device function annotations, and the efficiency and quality of circuit design and simulation are improved.

Description

Technical Field

[0001] The present invention belongs to the field of electronic circuit design and automation technology, and specifically provides a circuit netlist generation method that supports multi-stage reasoning of deep learning models. Background Art

[0002] With the widespread application of electronic products, the design and simulation of analog circuits play a vital role in the field of electronic engineering. However, the traditional analog circuit design process has many problems, which seriously restrict the efficiency and quality of circuit design.

[0003] On the one hand, manually drawing circuit diagrams and converting them into netlists is inefficient. Engineers need to spend a lot of time and energy to accurately draw each component and its connection relationship. Manual operations are also prone to errors, which may lead to inaccurate results of the entire circuit simulation, thereby affecting the reliability and performance of the circuit design.

[0004] On the other hand, some existing auxiliary tools have shortcomings in terms of device identification accuracy, connection relationship recognition, and circuit function identification. For example, some tools cannot accurately identify components with similar shapes or irregular markings, especially active components with positive and negative polarity directions, resulting in a high error rate. Complex cross-line and cross-line structures often lead to misjudgment of connection relationships, affecting the accuracy of the netlist. Moreover, most existing tools lack the ability to identify circuit functions, unable to provide engineers with more in-depth circuit information, which is not conducive to circuit optimization and innovation.

[0005] In addition, early projects and historical documents often lack circuit diagram information, which brings great difficulties to circuit maintenance, upgrading and innovation.

[0006] Therefore, in order to address the problems existing in the existing technology, such as low efficiency, easy errors, insufficient device identification accuracy, difficulty in identifying connection relationships, and lack of function identification, there is an urgent need for an analog circuit diagram to netlist conversion solution that is efficient, highly automated, and has high recognition accuracy. Summary of the Invention

[0007] In response to the above problems, the present invention provides a circuit netlist generation method that supports multi-stage reasoning of deep learning models, solves the problem of automatic conversion of analog circuit diagrams to netlists, and realizes automatic netlist generation of analog circuit diagrams through machine learning and image processing technology. It can convert analog circuit diagram files in standard format into netlist files with device function annotations, thereby improving the efficiency and quality of circuit design and simulation.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] This invention provides a circuit netlist generation method that supports multi-stage reasoning with deep learning models. This method acquires a circuit diagram image through optical scanning. After preprocessing the image, it uses the YOLOv5 deep learning model to identify components and determine their bounding box coordinates and category information. Component ports are then finely identified to determine their position and orientation. Optical character recognition technology is also used to eliminate text interference and identify wires, including Hough line detection and wire jumper processing, to determine the starting and ending coordinates of the wires. The identification results of components, ports, and wires are matched to construct the topology of the circuit diagram. Ultimately, a circuit netlist is generated, followed by error elimination and output in JSON format.

[0010] The beneficial effects of the above technical solution are: realizing the automatic parsing of circuit diagrams and improving the efficiency and accuracy of circuit netlist generation. Through multi-stage deep learning model reasoning, it is possible to accurately identify components, ports and wires in circuit diagrams, effectively solving the problem of identifying complex connection relationships in circuit diagrams. At the same time, combined with optical character recognition technology and Hough line detection and other methods, the accuracy and reliability of recognition are further improved. The JSON format netlist finally generated is convenient for subsequent circuit simulation, analysis and optimization, and has high practicality and scalability. Compared with the prior art, the present invention can significantly improve the efficiency and quality of circuit netlist generation, and provide strong support for circuit design and analysis.

[0011] As a further improvement to the above scheme, the training process of the deep learning model YOLOv5 includes: collecting component image data in the circuit diagram, annotating the bounding box coordinates and category information of the components, dividing the annotated data set into a training set and a validation set, training the YOLOv5 model using the training set, and testing it on the validation set to obtain the model's precision and recall rate indicators.

[0012] The beneficial effects of this technical solution include: through rational data set partitioning and model training optimization, it can improve the accuracy and generalization ability of the YOLOv5 model in component identification tasks, ensuring the model's good performance in practical applications. Compared with existing technologies, the model training method of this invention is more systematic and scientific, and can effectively improve the reliability of circuit netlist generation.

[0013] As a further improvement to the above scheme, the method for fine port identification includes determining the possible position and orientation of the port based on the category information of the component, performing local feature extraction within the bounding box of the component, using a deep learning model or a traditional image processing algorithm to determine the specific position and orientation of the port, calculating the center coordinates of the port, and associating them with the bounding box coordinates of the component to form a corresponding relationship between the port and the component.

[0014] The above technical solution has the beneficial effect of accurately identifying the position and orientation of component ports, improving the accuracy and reliability of port identification and providing more accurate data support for subsequent circuit topology construction and netlist generation. Compared with existing technologies, the present invention's refined port identification method combines the advantages of deep learning models and traditional image processing algorithms, and can better adapt to the port identification needs of different types of components.

[0015] As a further improvement to the above solution, optical character recognition technology uses OCR tools to recognize text in circuit diagrams, including character recognition and position positioning of text, and removes the recognized text information from the image to avoid its interference with wire identification.

[0016] The beneficial effects of the above technical solution are: effectively eliminating interference from text in circuit diagrams on wire recognition, improving the accuracy and reliability of wire recognition, and ensuring the correct construction of circuit topology. Compared with the existing technology, the present invention uses OCR tools for text recognition and elimination, with higher recognition efficiency and accuracy.

[0017] As a further improvement of the above solution, the Hough line detection method includes:

[0018] Perform edge detection on the image with text and component frames removed, and extract edge pixels in the image;

[0019] Convert edge pixels to Hough space and count the votes for different line parameters using the accumulator array;

[0020] Determine the straight line in the image based on the number of votes and obtain the coordinates of the starting and ending points of the straight line;

[0021] The Hough line detection method is divided into two stages:

[0022] Stage 1: initial line extraction;

[0023] Perform edge detection on the image;

[0024] Use probabilistic Hough transform to detect all possible straight line segments;

[0025] Get the endpoint coordinates of each line;

[0026] The output of the first stage is a large number of short line segments, which may belong to the same electrical conductor but are cut by image noise, symbol interference, etc.

[0027] Phase 2: Greedy coupling as wire;

[0028] Set a distance threshold, such as no more than δ pixels between endpoints;

[0029] A greedy algorithm is used to merge line segments that are close to each other and have the same direction into one wire;

[0030] The final output wire is a combination of multiple original Hough segments, representing a Net in the circuit;

[0031] The greedy coupling algorithm in the second stage is used to deal with the practical problem that the electrical conductor may be a "broken line" or "multi-segment splicing", and is part of the geometric topology reconstruction.

[0032] The beneficial effect of the above technical solution is: efficient and accurate wire identification is achieved through phased processing. The first phase uses the probabilistic Hough transform to extract short line segments in the image, effectively addressing the problem of wire breakage caused by image noise and symbol interference. The greedy coupling algorithm in the second phase innovatively merges short line segments into complete wires, accurately solving the problem of broken or spliced ​​electrical wires and ensuring the integrity of wire identification. This method significantly improves the accuracy of wire identification, provides a reliable basis for circuit topology construction, reduces incorrect connections, enhances the accuracy and reliability of netlist generation, reduces the cost of manual corrections, and promotes the efficiency of circuit design and simulation.

[0033] As a further improvement to the above scheme, the method of wire jumper processing includes designing specific convolution kernels to detect different types of node connections, or using a trained deep learning model to distinguish node types, determining the node connection method based on the detection results, and performing corresponding processing on the wires.

[0034] The above technical solution has the beneficial effect of effectively solving the problem of identifying jumpers in circuit diagrams, improving the accuracy of determining wire connection relationships, and ensuring the correctness of circuit topology. Compared with existing technologies, the jumper processing method of the present invention combines the advantages of convolution kernel detection and deep learning models, and can better adapt to the identification needs of different types of nodes.

[0035] As a further improvement to the above scheme, the matching method includes determining the connection relationship between the port and the component based on the bounding box coordinates of the component and the position information of the port, determining the connection relationship between the wire and the port based on the starting and ending point coordinates of the wire, and constructing the topological structure of the circuit diagram, including nodes, edges and connection relationships.

[0036] The beneficial effects of the above technical solution include achieving accurate matching between components, ports, and wires, improving the efficiency and accuracy of circuit topology construction, and providing reliable data support for subsequent netlist generation. Compared with existing technologies, the matching method of the present invention can better adapt to complex connection relationships in circuit diagrams and ensure the correctness of circuit topology.

[0037] As a further improvement to the above solution, the method for generating a circuit netlist includes integrating the component type, port connection information and wire connection information to form a netlist data structure, assigning a unique identifier to each component and wire, and verifying and optimizing the netlist data.

[0038] The beneficial effects of the above technical solution are: the generated circuit netlist has a clear structure and complete data, accurately reflecting the connection relationships and electrical characteristics of the circuit diagram, and providing a reliable data foundation for subsequent circuit simulation, analysis, and optimization. Compared with the existing technology, the netlist generation method of the present invention combines the advantages of data integration and verification optimization, which can improve the quality and reliability of the netlist.

[0039] As a further improvement to the above solution, the error troubleshooting method includes verifying the validity of the connection object model, ensuring that each connection object is correctly defined in the netlist, checking the integrity of the netlist numbering, ensuring that each component is connected to at least one valid wire, eliminating isolated straight lines and floating devices, and correcting incorrect connections in the circuit diagram.

[0040] The above technical solution has the beneficial effects of effectively improving the accuracy and reliability of netlists, avoiding incorrect connections during circuit diagram analysis, and ensuring that every connection in the netlist conforms to the intended design. Compared with existing technologies, the error-correcting method of the present invention can better adapt to the complex connection relationships in circuit diagrams, improving the quality and usability of netlists.

[0041] As a further improvement to the above solution, the output content in JSON format includes a list of components, a list of wires, a list of special ports, and the correspondence between the netlist numbers and the actual numbers to ensure consistency with the numbers in the circuit diagram.

[0042] The above technical solution has the beneficial effect of outputting a JSON-formatted netlist with good scalability and ease of processing, facilitating data reading and processing by subsequent circuit simulation, analysis, and optimization tools, thereby improving work efficiency and data compatibility. Compared with existing technologies, the netlist output method of the present invention can better meet the data exchange and processing requirements of practical applications, and is highly practical and convenient.

[0043] Compared with the prior art, the technical solution of the present invention has the following specific technical effects:

[0044] 1. Breakthrough in Port Precision Identification

[0045] For precise identification of component ports, this invention innovatively combines component category information with local feature extraction. For example, for an operational amplifier, this method can precisely locate and orient ports within their bounding box. Compared to existing technologies, this method more accurately identifies port position and orientation, providing high-precision data for subsequent circuit topology construction, effectively resolving the ambiguity and inaccuracy of existing port identification techniques.

[0046] 2. High-precision wire identification

[0047] The wire identification of the present invention integrates Hough line detection, greedy algorithm and jumper processing. The image is first edge detected to extract pixel points, and then converted to Hough space to determine the line parameters. For jumpers, an innovative processing method combining convolution kernel and deep learning model is adopted. First, Hough line detection is used to extract short line segments in the image, and then the greedy algorithm is used to set the distance threshold between the endpoints to merge short line segments that are close and have the same direction into a complete wire. Compared with the existing technology, this method can more accurately identify the complex wire connection relationship in the circuit diagram, especially when dealing with obstructed and interfered wires. It has more advantages, effectively solving the problems of the existing technology in wire identification and providing a reliable data foundation for the construction of circuit topology structure.

[0048] 3. Accurate matching and topological structure construction

[0049] An innovative matching algorithm determines connections based on component bounding boxes and port locations, and determines wire-to-port connections based on wire coordinates, thereby constructing a topology that accurately reflects the circuit diagram's connectivity and electrical characteristics. Compared to existing technologies, this method significantly improves matching efficiency and topology construction accuracy, solves the challenge of determining complex connection relationships, and lays a solid foundation for netlist generation.

[0050] 4. High-quality netlist generation and verification optimization

[0051] When generating a circuit netlist, this invention integrates component, port, and wire information into a standardized data structure, assigns unique identifiers, and performs comprehensive verification and optimization, including checking the legitimacy of connections and eliminating redundant information. Compared to existing technologies, the generated netlist is of higher quality and more complete data, accurately reflecting circuit connections and characteristics. This provides reliable data support for subsequent circuit simulation, analysis, and optimization, effectively resolving the inaccuracies and incompleteness issues inherent in existing netlist generation techniques.

[0052] 5. Innovation in Multi-stage Reasoning of Deep Learning Models

[0053] This invention innovatively applies deep learning models to multiple stages of circuit diagram parsing, including component identification, port identification, and jumper processing, giving full play to its advantages in image recognition and feature extraction. Compared with existing technologies that rely solely on a single deep learning model or traditional image processing algorithm, the multi-stage reasoning mechanism improves the accuracy and efficiency of circuit diagram parsing. Each stage cooperates with each other to achieve accurate parsing of complex circuit diagrams. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 Generate an overall system architecture diagram for the circuit netlist.

[0055] Figure 2 Complete workflow for circuit netlist generation.

[0056] Figure 3 This is the specific implementation process of the two modules: components and ports.

[0057] Figure 4 The specific process of wire identification is demonstrated, using two steps: greedy algorithm and deep learning.

[0058] Figure 5 Schematic diagram of the function identification process.

[0059] Figure 6 These are example diagrams of circuit diagram device symbol recognition results, where (a) is the original circuit diagram, (b) is the component recognition diagram, and (c) is the port refined recognition diagram.

[0060] Figure 7 Figure 1 shows an example of the device connection relationship recognition results, where (a) is the original image, (b) is the image after removing the OCR text, and (c) is the final wire recognition display.

[0061] Figure 8 Figure 3 shows the recognition results of the trained model for three circuit nodes, where (a) is the recognition result of wire interconnection, (b) and (c) are the recognition results of two different formats of jumper connection methods.

[0062] Figure 9 Flowchart for the line overflow fitting algorithm combined with boundary and device interior detection.

[0063] Figure 10 The following are example results of the straight line overflow fitting algorithm combined with boundary and device internal detection, where (a) is the MOS tube connection judgment result and (b) is the resistor connection judgment result.

[0064] Figure 11 Example of generated JSON format netlist information Figure 1 ,where (a) is the result display diagram after the simulation circuit diagram recognition, and (b) is the result display diagram of the generated netlist.

[0065] Figure 12 Example of generated JSON format netlist information Figure 2 ,where (a) is the result display diagram after the simulation circuit diagram recognition, and (b) is the result display diagram of the generated netlist.

[0066] Figure 13 Example of generated JSON format netlist information Figure 3 ,where (a) is the result display diagram after the simulation circuit diagram recognition, and (b) is the result display diagram of the generated netlist. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the technical solution, the present invention is described in detail below in conjunction with embodiments. The description in this section is only exemplary and explanatory and should not have any limiting effect on the scope of protection of the present invention.

[0068] 1. System Architecture and Module Composition

[0069] like Figure 1 As shown in the figure, the overall architecture of the circuit netlist generation system that supports multi-stage reasoning of deep learning models is shown:

[0070] 1. Image Input Module: This module acquires image data of analog circuit diagrams through an optical scanner or digital camera, supporting common image formats such as JPEG, PNG, and BMP. This module provides raw image data input for the entire system and serves as the fundamental starting point for system operation.

[0071] 2. Image Preprocessing Module: Connects to the Image Input Module and preprocesses image data. This primarily involves converting color images to grayscale and performing binarization (with a threshold of 120-150, with values ​​greater than 255 set to white and values ​​less than or equal to 0 set to black). This module then extracts line and graphic information, applies a Gaussian filter to remove noise, and utilizes optical character recognition (OCR) technology to identify and filter out text, resulting in a pure binary image containing only the circuit diagram's lines and graphic symbols. This preprocessed image data is then used for subsequent component and wire identification.

[0072] 3. Component Identification Module: Based on the YOLOv5 deep learning model, this module accurately identifies common components such as resistors, capacitors, diodes, transistors, MOSFETs, and operational amplifiers, outputting their categories and location coordinates. Trained on a large amount of annotated circuit diagram image data, this model learns the characteristics and categories of different components. During actual identification, the model inputs a preprocessed image, outputs the location coordinates and category of the component area, and transmits the results to the port fine-grained identification module.

[0073] 4. Port Refinement Identification Module: Utilizing a two-stage YOLO algorithm, the second stage employs the YOLOv5m model to precisely locate component ports, achieving an identification accuracy exceeding 98.5%. A coordinate matching algorithm precisely associates ports with their respective components. Initially, the YOLOv5 model is used for preliminary identification to determine the approximate location of the component. The image of this area is then fed into the YOLOv5m model for refined identification, accurately determining the location coordinates of the component port. Based on the coordinate matching algorithm, the coordinate matching algorithm determines which component the port belongs to, achieving precise association between the port and the component to which it belongs. After refined port identification is complete, the port information is passed to the automatic netlist generation module.

[0074] 5. Connecting Wire Identification Module: Based on the Hough transform algorithm, the detection angle range is 0°-180°, and the detection threshold is set between 100-150, which can detect wire connections. When identifying circuit diagrams, the Hough transform algorithm is first used to detect straight lines in the image, covering wires of different directions. A threshold is set to filter out straight line segments that meet the wire characteristics. Subsequently, a greedy algorithm is used to process the detected straight line segments. A threshold is set between the endpoints to merge short line segments that are close together and have the same direction into a complete wire. This enables accurate identification of complex wire connections, especially when dealing with obstructed and interfering wires. For special crossing and crossing wire structures, a pre-trained deep learning model is used for identification. This model is trained on a large amount of relevant circuit diagram image data and can accurately distinguish between crossing and crossing connections between wires. For example, it can accurately identify when a wire crosses over from another component lead without connecting to it. The starting and ending coordinates of the wire and the connection relationship are recorded. The identified wire connection relationship is then passed to the automatic netlist generation module.

[0075] 6. Netlist automatic generation module: With the help of straight line overflow fitting algorithm and boundary detection algorithm, it realizes automatic matching of component ports and connecting wires, and generates netlist files in standard format, supporting mainstream netlist formats such as JSON. After completing the identification of components, ports and wires, taking a port [x3, y3] of a resistor and the starting point [x3, y3] and end point [x5, y5] of the wire connected to it as an example, the straight line overflow fitting algorithm determines that the wire is connected to the port based on the coordinate information of the port and wire, and uses the boundary detection algorithm to determine which port of which component the other end point of the wire connection belongs to, thereby realizing automatic matching of component ports and connecting wires. Finally, all matching results are organized and packaged according to the JSON format requirements to generate a netlist file containing component information, port information, and wire connection relationships. This file can clearly and accurately reflect the circuit topology and can be directly read and parsed by circuit simulation software for subsequent simulation analysis.

[0076] 7. Function Identification Module: Based on a voting mechanism, the module outputs the circuit function identification results by determining whether specific components and specific netlist structures exist in the circuit. For example, when it is identified that the circuit contains components such as operational amplifiers, resistors, and capacitors, and the netlist structure conforms to the characteristics of a filter circuit, such as a typical filter circuit topology where the input of an operational amplifier is connected to a resistor and capacitor to form a filter network, and the output feedback is connected to the input, the voting mechanism in the function identification module votes on each key feature according to the preset filter function judgment rules. When a certain number of votes is met, the circuit is judged to have a filtering function, and further judged to have a low-pass filtering function based on the filter component parameters and connection method. This function information is added to the netlist file, providing circuit designers with more comprehensive circuit information to assist in circuit design and optimization.

[0077] like Figure 2-Figure 7 As shown, this embodiment provides a circuit netlist generation method that supports multi-stage reasoning of a deep learning model, and the specific steps are as follows:

[0078] 1. Image Acquisition

[0079] Use an optical scanning device or digital camera to scan or photograph the circuit diagram to obtain an image of the circuit diagram. The image resolution must be no less than 300dpi to ensure that the details in the circuit diagram are clearly presented, providing a high-quality image foundation for subsequent recognition processing.

[0080] 2. Image Preprocessing: De-noising, grayscaling, binarization, edge detection, and morphological operations are performed on the circuit diagram image. De-noising uses a Gaussian filter with a 3×3 kernel; grayscaling uses the formula GRAY = 0.299×R + 0.587×G + 0.114×B; binarization uses the Otsu method to automatically determine the threshold; edge detection uses the Sobel operator; morphological operations include erosion and dilation, with a 3×3 rectangle as the structuring element to remove noise and close broken lines.

[0081] 3. Component Identification: Use the YOLOv5 model to identify components in preprocessed images. Collect common component image data and annotate bounding box coordinates and category information. The annotation format is:

[0082] [x_center,y_center,width,height,class_id]

[0083] The dataset was split into training and validation sets with a ratio of 8:2. The YOLOv5 model was used for training, with a learning rate of 0.01, 300 iterations, and a batch size of 16. Hyperparameters were adjusted during training to optimize performance. After training, the model was tested on the validation set, with a minimum accuracy of 90% and a minimum recall of 85%.

[0084] 4. Port fine identification

[0085] Based on the component's bounding box coordinates and category information, component ports are precisely identified. For an operational amplifier, for example, the possible location and orientation of the port are determined based on its category information. Within the op amp's bounding box, local features are extracted from the image, and a template matching algorithm is used to determine the specific location and orientation of the port. In this algorithm, the template image is a predefined op amp port feature image, and the matching threshold is set to 0.8. The port's center coordinates are calculated and associated with the component's bounding box coordinates to establish a port-component correspondence. For other component types, similar template matching or other traditional image processing algorithms are used for precise port identification.

[0086] 5. Wire identification

[0087] Perform wire recognition on images with text and component boxes removed.

[0088] (1) Combination of Hough line detection and greedy algorithm

[0089] First, perform edge detection on the image to extract edge pixels. Use the Canny edge detection algorithm with threshold 1 set to 50 and threshold 2 set to 150. Convert the edge pixels to Hough space, and use an accumulator array to count the votes for different line parameters. Set the accumulator array size to 180×180, with an angular resolution of 1 degree and a distance resolution of 1 pixel. Determine the lines in the image based on the number of votes, and obtain the start and end coordinates of the lines. The minimum length of a line must be 10 pixels, and the maximum gap must be 3 pixels.

[0090] Then, the greedy algorithm is used to optimize the detected straight line. The specific steps are as follows:

[0091] Step 1: Initialize the parameters of the greedy algorithm, including setting the distance threshold (e.g., δ pixels) and angle threshold (e.g., θ degrees) between endpoints to determine whether short line segments can be merged.

[0092] Step 2: Perform endpoint screening on the short line segments obtained by Hough line detection and extract the start and end point coordinates of each short line segment.

[0093] Step 3: Construct a proximity table. Based on the distance threshold δ and angle threshold θ, detect and record pairs of adjacent short line segments with the same direction. Specifically, calculate the distance between each short line segment and the endpoints of other short line segments, as well as the angle between the segments.

[0094] Step 4: Following the greedy algorithm, select a pair of short segments with the greatest potential for merging. For example, you can select the longest pair of short segments that meets the conditions, or select the pair of short segments that can generate the largest possible complete wire.

[0095] Step 5: Update the neighbor relationship table, remove the merged short line segments, and add the newly merged long line. At the same time, recalculate the neighbor relationship related to the new long line.

[0096] Step 6: Repeat steps 3 through 5, continuing to merge short segments until no short segment pairs that meet the distance and angle thresholds are found. The final output wire is a combination of multiple original Hough segments, representing a net in the circuit.

[0097] By applying the above greedy algorithm, broken lines or wires composed of multiple segments in circuit diagrams can be effectively processed to ensure the integrity and accuracy of wire identification.

[0098] (2) Jumper processing

[0099] A trained deep learning model was used to distinguish different types of node connections. Image data of current nodes, cross-connections, and cross-line nodes in the circuit diagram was collected and annotated with node category information. A convolutional neural network (CNN) model was used for training. The model architecture consisted of three convolutional layers and two fully connected layers. The convolutional layer filters had filter sizes of 3×3, 5×5, and 7×7, with a stride of 1 and padding of the same. The fully connected layers had 128 and 3 neurons, respectively. After training, the nodes in the circuit diagram were classified and identified, their connection patterns determined, and the wires were processed accordingly.

[0100] 7. Matching and topology construction

[0101] (1) Port and component matching

[0102] Based on the component's bounding box coordinates and the port's location information, the connection relationship between the port and the component is determined. The distance between the port's center coordinates and the component's bounding box center coordinates is calculated. If the distance is less than a set threshold (for example, 10 pixels), the port is considered to belong to the component.

[0103] (2) Wire and port matching

[0104] Based on the coordinates of the wire's start and end points, the connection between the wire and the port is determined. The distance between the wire's start and end points and the port's center coordinates is calculated. If the distance is less than a set threshold (e.g., 5 pixels), the wire is considered connected to the port. The topology of the circuit diagram is constructed, consisting of nodes, edges, and connections. Each node represents a port or connection point, each edge represents a wire, and connections represent the electrical connections between nodes.

[0105] 8. Netlist generation

[0106] (1) Netlist data integration

[0107] The component type, port connection information, and wire connection information are integrated to form a netlist data structure. Each component and wire is assigned a unique identifier using a combination of letters and numbers, such as R1, C1, and Q1. The netlist data structure uses a dictionary format, with the key being the component identifier and the value being the component type and port connection information; the key being the wire identifier and the value being the wire's start and end coordinates and the connected port information.

[0108] (2) Netlist verification and optimization

[0109] Verify and optimize the netlist data, including checking the legitimacy of connection relationships and eliminating redundant information. Check whether the ports of each component are connected correctly, whether the wires are connected to valid ports, and exclude non-existent components or port information.

[0110] 9. Troubleshooting

[0111] (1) Connection object model verification

[0112] Verify the validity of the connection object model to ensure that each connection object is correctly defined in the netlist. Check that the number and type of ports of each component match its electrical characteristics. For example, a resistor should have two ports, and a capacitor should also have two ports. If a connection object's model is undefined or incomplete, the connection object is considered invalid and removed from the netlist.

[0113] (2) Netlist number integrity check

[0114] Check the integrity of the netlist numbering to ensure that each component is connected to at least one valid wire. Iterate through each component in the netlist and check that its port connection information contains valid wire identifiers. Eliminate orphaned lines and dangling components to correct incorrect connections in the schematic.

[0115] 10. Netlist output

[0116] Output the corrected netlist in JSON format. The output in JSON format includes:

[0117] (1) Components list

[0118] Each component contains type, identifier, and port connection information. For example: {"R1":{"type":"Resistor","pins":{"pos":"net1","neg":"net2"}},"C1":{"type":"Capacitor","pins":{"pos":"net3","neg":"net4"}}}.

[0119] (2) Wire list

[0120] Each wire contains the coordinates of the start and end points as well as the connected port information. For example: {“W1”:{“start”:[x1,y1],“end”:[x2,y2],“net”:“net1”}}.

[0121] (3) Special port list

[0122] This includes port information for power and ground connections such as VDD and GND. For example: {“VDD”:{“net”:“net5”},“GND”:{“net”:“net6”}}.

[0123] (4) Netlist number correspondence

[0124] Make sure the netlist numbers correspond to the actual numbers to ensure they match the numbers in the circuit diagram. For example: {"net1":"VCC","net2":"GND","net3":"IN","net4":"OUT"}.

[0125] Through the above steps, this embodiment implements a circuit netlist generation method that supports multi-stage reasoning of deep learning models. This method can accurately identify components, ports, and wires in a circuit diagram, construct the topology of the circuit diagram, generate an accurate circuit netlist, and output it in JSON format, providing reliable data support for subsequent circuit simulation, analysis, and optimization. At the same time, this method undergoes rigorous verification and optimization at each step to ensure the accuracy and completeness of the netlist and meet the needs of high-precision circuit analysis.

[0126] like Figure 3 As shown in the figure, it is the specific implementation process of the two modules of components and ports:

[0127] 1. Data preparation: Provide 2,200 pieces of data in JSON format for model training.

[0128] 2. Data conversion and import: Convert json data into txt file and import it into the YOLOv5 model.

[0129] 3. Model training and validation: Use the training data to train the YOLOv5 model and test the model's recognition effect on the validation set to ensure that the model can accurately identify the components in the circuit diagram.

[0130] 4. Supplementary recognition: Additional recognition processing is performed on specific information (such as adders, operational amplifier inputs, arrows, labels, etc.) to improve the comprehensiveness and accuracy of the model.

[0131] like Figure 4 The figure shows the specific process of wire identification, which uses two steps: greedy algorithm and deep learning. The specific steps are as follows:

[0132] 1. Read coordinate information: Read the coordinates of components recognized by the YOLO model and the coordinates of OCR text recognition.

[0133] 2. Preprocess the image: Preprocess the image to enhance the effect of feature extraction.

[0134] 3. Pixel traversal and algorithm processing:

[0135] Iterate over the black pixels in the image.

[0136] Apply greedy algorithm for path planning and identification.

[0137] Path processing is performed to extract the complete path information.

[0138] 4. Path output: Output the identified path information to provide a basis for subsequent netlist generation.

[0139] like Figure 5 The figure shows the identification verification and function judgment process of the method of the present invention, and the specific steps are as follows:

[0140] 1. Verify the connection relationship: Determine whether the connection method of the identified MOS tube is correct, including the connection status of the source (S), gate (G), and drain (D).

[0141] 2. Identify specific components: Determine whether the circuit contains only specific components such as BIT, SIGN, DIDO, etc. to determine the type and function of the circuit.

[0142] 3. Determine the operational amplifier connections: Identify the components connected to the output ports of the operational amplifier to further analyze the circuit's functionality.

[0143] 4. Function identification and output: Output corresponding function labels based on the identification results, such as comparator, LOGIC, etc., to provide a basis for functional identification of the circuit.

[0144] Figure 6This is an example of the circuit diagram device symbol recognition results. Through different colors or marks, it shows the model's recognition results of the components and connection relationships in the circuit diagram, intuitively presenting the model's recognition effect.

[0145] The detailed implementation process of the present invention is as follows:

[0146] 1. Overall framework

[0147] The design structure of the framework is as follows Figure 1 As shown in the figure, the overall framework of this system relies on the coordinated operation of three core modules: port identification, wire identification, and netlist output. It aims to achieve automatic parsing of analog circuit diagrams through computer vision and deep learning technology.

[0148] Specifically, when it comes to component identification in circuit diagrams, the wide variety of components involved, represented by varying symbols, often leads to connecting lines intersecting or obscuring component symbols. Furthermore, the diagrams may contain additional annotations, further complicating the identification task. Therefore, the use of deep learning models (such as YOLOv5 and YOLOv8) for component identification is particularly important. These models excel in image classification and object detection, efficiently identifying various components in circuit diagrams. Data augmentation techniques (such as rotation, scaling, and cropping) can be used to enrich the diversity of training datasets and further improve the model's generalization capabilities. Furthermore, the introduction of techniques such as attention mechanisms or region proposal networks (RPNs) can help improve the model's accuracy in identifying component boundaries and connection points.

[0149] When identifying connections between components, circuit diagrams may use bridged lines or node annotations, and the diverse and irregular shapes of circuit lines complicate the determination of connection relationships. Furthermore, due to varying drawing styles, line widths may be inconsistent within circuit diagrams, further impacting the determination of connection integrity. To this end, it is necessary to combine image processing techniques (such as Hough transforms and edge detection) to extract circuit information and design optimization algorithms to perform post-processing on the extracted circuit information, such as smoothing and denoising. Furthermore, using technologies such as graph neural networks (GNNs), it is possible to construct the topological structure of circuit diagrams, accurately reflecting the connection relationships between components.

[0150] Through the above methods, the entire framework can achieve efficient and automatic parsing of analog circuit diagrams, accurately extract component and connection information, and provide a reliable data foundation for subsequent netlist generation and circuit analysis.

[0151] 2. Port identification

[0152] 2.1 Two-stage YOLO port identification (port and device matching algorithm, specific location coordinate algorithm)

[0153] For the port identification task, this study employed a two-stage YOLO recognition method to improve both accuracy and speed. First, the YOLO neural network identified all components and ports in the circuit diagram, quickly and preliminarily determining the locations of the components within the diagram and extracting their coordinate information. The results of this stage provided preliminary data support for subsequent netlist generation. Manual verification of the recognition results demonstrated an accuracy of 98.5%.

[0154] To achieve accurate port-level netlist generation, especially for port identification of directional components such as diodes, transistors, MOS transistors, and operational amplifiers, we proposed a two-stage port identification method based on YOLO.

[0155] Existing mainstream methods typically perform secondary recognition by cropping a region of interest (ROI) based on initial recognition to extract port information. However, when the number of ports to be identified in a circuit diagram exceeds 10, the overall computation time increases significantly.

[0156] In order to balance the accuracy and efficiency of recognition, we proposed an improved two-stage YOLO recognition algorithm, as follows:

[0157] In the first stage, we use the YOLOv5 model to perform preliminary device recognition on the entire circuit diagram and identify the locations of all components.

[0158] In the second phase, we performed detailed port-level identification on the identified circuit components. To this end, we reconstructed a port-level dataset and added a YOLOv5m model tailored to the characteristics of different circuit components to optimize port identification accuracy and efficiency. During the dataset construction process, we redesigned the port identification framework by summarizing and analyzing 2,216 circuit diagrams and supplemented the training data for the second-phase model with data tailored to the characteristics of different component types.

[0159] After the dataset is optimized, the circuit diagram identified by YOLO in the first stage is preprocessed and input into the second stage YOLOv5m model for port identification to obtain the corresponding port information.

[0160] The port information from this stage is associated with the device identification results from the first stage using a coordinate matching algorithm. To effectively address the overlap between the port identification box and the component identification box, we have strictly constrained the port identification box during dataset construction to ensure that it always remains within the corresponding component identification box, thus avoiding the possibility of overlapping identification.

[0161] To implement port matching, we used a double for loop to match each identified box. Specifically, we first determined the possible port area based on each component's bounding box. Then, we used a double loop to iterate through all identified component information, searching for coordinates that matched the port within the current component box. We further confirmed the port-component matching relationship by calculating whether the port center point fell within the component box. The formula is shown below.

[0162] Two sets of box data can be obtained by two yolo recognitions, which are recorded as 、 , the center point of box2 for:

[0163]

[0164] Given the coordinates of the four corners of box1 , determine whether the center point of box2 is inside box1, by the following conditions:

[0165]

[0166] in and are the x and y coordinates of the center point of box2, respectively. Through this algorithm, we effectively combine the two-stage YOLO recognition and coordinate matching process, greatly reducing the computational complexity.

[0167] After completing the matching of components and ports, we use the coordinate operation algorithm to further calculate the precise position of each port relative to the component frame.

[0168] For each different component , all have different ports that are matched , at this time, box2 must be located inside box1. In order to determine the orientation of box2 relative to box1, we need to compare the four distances of up, down, left and right.

[0169] Top distance:

[0170]

[0171] Bottom distance:

[0172]

[0173] Left distance:

[0174]

[0175] Right distance:

[0176]

[0177] After calculating the distances of the four sides, we can determine the position of box2 based on the minimum two distances. Calculate the minimum two distances to determine the orientation:

[0178]

[0179] For example, when identifying a MOS transistor, we determine the orientation of the component by calculating the distances between the gate, source, and drain relative to the frame. Based on the component's characteristics and the distances between the ports, we ultimately determine the exact location of each port (such as the gate, source, and drain) in the circuit diagram. This process effectively converts the location of each port into precise coordinates, which are stored in a dictionary.

[0180] The port identification of other circuit components is also processed according to similar algorithm steps to ensure the accurate extraction of port information.

[0181] Through this two-stage YOLO port identification method, combined with coordinate matching and precise positioning algorithms, we can efficiently and accurately extract the location information of each component and its ports in the circuit diagram, providing solid data support for subsequent netlist generation and circuit analysis.

[0182] 3. Wire identification

[0183] 3.1 Preprocessing and component exclusion

[0184] In circuit topology diagrams, wire connections are typically represented as straight horizontal and vertical lines, making wire identification crucial for structural analysis. To accurately identify wire connections in circuit diagrams, this study combined optical character recognition (OCR) technology with the component recognition results of the YOLO model. This method removes text and component information from the diagrams, minimizing their impact on subsequent line detection.

[0185] OCR technology is primarily used to identify text annotations (such as VDD, GND, etc.) in circuit diagrams, which can interfere with wire identification. Meanwhile, the YOLO model is used to identify components in the circuit diagram and remove their location boxes. This two-step process effectively eliminates text and component information from the circuit diagram, providing a clean circuit diagram for subsequent wire detection, retaining only the wire connection information.

[0186] After performing OCR text recognition, the device boxes identified by YOLO and the character boxes identified by OCR are simultaneously removed from the original circuit diagram, leaving only the isolated straight lines. This process greatly simplifies the wire detection process, allowing the Hough line detection algorithm to more accurately extract the connecting lines in the circuit diagram.

[0187] 3.2 Hough Line Detection and Application

[0188] After filtering out interference identified by OCR and YOLO, we applied the Hough Transform algorithm to detect the remaining isolated lines. The Hough Transform is a classic image processing technique widely used for geometric shape recognition in images, particularly line detection. In this study, the Hough Transform helped us identify the connecting lines between components in circuit diagrams, further revealing the circuit's topology.

[0189] Because we've removed all text and component boxes from the circuit diagram during preprocessing, the Hough line detection algorithm only detects isolated lines in the diagram. This approach has the advantage of avoiding interference caused by occlusions from text and components, resulting in more accurate line detection.

[0190] The Hough transform maps each point in the image space to the parameter space, finding the peaks in the parameter space to identify the straight lines in the image. In the parameter space, each straight line in the image space corresponds to a point, and by finding the intersection of these points, we can identify the connecting parts in the circuit diagram.

[0191] 3.3 Jumper Processing

[0192] In a circuit topology diagram, there are usually three ways for wires to cross:

[0193] (a) Current node Two wires are connected together.

[0194] (b) Two wires cross but are not connected.

[0195] (c) Similar to (b), two wires cross but are not connected, which is called a flying wire.

[0196] In order to distinguish these three node connection methods, we use deep learning algorithms:

[0197] Deep learning solutions use trained models to identify different types of node connections. Through machine learning, the model automatically learns the characteristics of circuit diagrams and distinguishes node types. This approach offers high accuracy and low computational cost, particularly in complex circuit diagrams.

[0198] Deep learning methods can more accurately identify different nodes in circuit diagrams by training models with low computing resource consumption. This significantly improves recognition accuracy and efficiency. Figure 8 As shown in the figure above, the trained model recognizes the three circuit nodes shown in the figure above.

[0199] 3.4. Innovative Method Combining YOLO and Hough Transform

[0200] The innovation of this research lies in the organic combination of three technologies: YOLO component recognition, OCR character filtering, and Hough line detection. YOLO is used for component recognition, OCR removes text interference, and Hough transform is used to extract wire connections, forming an efficient and accurate processing flow.

[0201] This combined approach solves the problem of detecting complex connecting lines in circuit diagrams, especially when there are obstructions or interference. By removing the interference first and then extracting the lines, detection accuracy is significantly improved. Furthermore, the Hough transform focuses only on isolated lines, not those obscured by text or component frames, ensuring accurate extraction of circuit diagram connecting lines.

[0202] This method not only effectively improves the analysis accuracy of circuit diagrams, but also provides strong data support for subsequent circuit netlist generation and circuit functional module identification.

[0203] 4. Netlist output

[0204] 4.1 Coordinate Matching

[0205] 4.1.1 Wire and component coordinate matching

[0206] In circuit diagram parsing, after determining the node type, the next step is to identify the wires connected to each node to distinguish current branches and the connection relationships between modules. This study proposes a method based on a "straight line overflow fitting algorithm" that determines the connection relationship between wires and ports by detecting pixels in different regions.

[0207] Specifically, this method, based on a machine learning model, uses a regional detection algorithm to detect pixels near a device and approximates these pixels as a straight line. The straight line selected by the algorithm is the wire connected to the device.

[0208] While machine learning models can effectively identify wires connected to devices, they can encounter overfitting during model training. In this study, this problem manifested itself when the four corners of the detection box, where no wires were present, caused the model to rely on specific patterns in the training data that were overfitted. This reduced recognition accuracy in these areas, affecting the final judgment.

[0209] To eliminate this defect, we designed a boundary detection algorithm that can handle special cases. For example, when the wire is not identified, the direction of the wire can be further determined by detecting the distance from the pixel point to the region boundary.

[0210] In addition, some wires may pass through the interior of the device, affecting the recognition results. To solve this problem, we further expand the detection area to cover the interior of the device.

[0211] By combining the above optimized straight line overflow fitting algorithm with the boundary and internal detection of the device, the connection relationship between the wire and the device can be determined more accurately. Figure 9 The process shown in the following example is executed. Figure 10 shown.

[0212] 4.2 Port and Wire Matching

[0213] Once the wire and device connections are determined, the next step is to match the connection point coordinates with the port coordinates. This process is done by calculating the distance between points. Specifically, we use the following mathematical formula to calculate the connection point and ports The Euclidean distance between

[0214]

[0215] in, are the coordinates of the connection points, are the coordinates of the port.

[0216] We set a threshold , if the calculated distance Less than threshold , the wire is considered to be connected to the port, that is:

[0217]

[0218] The threshold Minimum values ​​are set for component boxes to ensure accurate results. By matching ports and wires, we ultimately create a dictionary containing the connection relationships between wires and component ports. The dictionary uses netlist numbers as keys and connection information as values. This information provides reliable data support for subsequent circuit analysis and netlist generation.

[0219] 5. Eliminate errors in netlist and output format

[0220] During the circuit diagram parsing process, we implemented a series of steps to eliminate errors in the generated netlist to ensure its accuracy and completeness. Ultimately, the corrected netlist was output in JSON format to ensure data scalability and ease of subsequent processing. The specific process includes the following steps:

[0221] 5.1 Troubleshooting incorrect connections

[0222] First, we verify the validity of the connection object model to ensure that each connection object is correctly defined in the netlist. If a connection object's model is undefined or incomplete, it is deemed invalid and removed from the netlist. This step effectively avoids incorrect connections during circuit diagram analysis and ensures that every connection in the netlist conforms to the intended design.

[0223] Next, after verifying the connection objects, we checked the integrity of the netlist numbering. We ensured that each component in the netlist was connected to at least one valid wire, eliminating isolated lines and dangling components. Isolated lines and dangling components are incorrect connections in the circuit diagram and should not appear in a valid netlist. Through this elimination process, the connection relationships in the netlist were corrected to the correct circuit structure.

[0224] 5.2 Netlist Output

[0225] After troubleshooting, the final netlist will be output in JSON format. Since the netlist numbers are not renumbered during troubleshooting, the original netlist numbers will remain unchanged to ensure consistency with the numbers in the schematic. However, in some cases, if the connection in the netlist involves VDD or GND, the netlist number will directly use VDD and GND as the connection number. Specifically, when a port connection in the netlist is marked as "VDD" or "GND", the system will automatically use this as the netlist number to correspond to the power and ground connections in the schematic.

[0226] An example of generated JSON format netlist information is as follows Figure 11-13 As shown in the figure, the final output netlist contains each component type (such as NMOS, PMOS, etc.) and its corresponding port connection information. Each port connection is associated with a corresponding net number (such as net4, net5, etc.). If the connection is to VDD or GND, the corresponding netlist number is "VDD" or "GND".

[0227] 5.3 Summary

[0228] Through the above steps, we ensure that the generated netlist is accurate and eliminates all invalid connections. The final netlist retains the original netlist numbering and is output in JSON format. In particular, when the netlist is connected to VDD or GND, VDD and GND are directly used as the netlist numbering. This output format ensures a structured and efficient netlist processing, making it suitable for subsequent circuit simulation, analysis, and optimization tasks.

[0229] It should be noted that, in this article, the terms: include, contain and any other variations are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or device. Specific examples are used herein to illustrate the principles and implementation methods of the technical solution of the present invention. The above examples are only used to help understand the method of the present invention and its core idea. The above is only a preferred embodiment of the present invention. It should be pointed out that due to the limitations of textual expression, there are objectively infinite specific structures. For ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements, modifications or changes can be made, and the above technical features can be combined in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concept and technical solution of the present invention to other occasions without improvement, should be regarded as the scope of protection of the present invention.

Claims

1. A circuit netlist generation method supporting multi-stage reasoning of deep learning models, characterized in that: The following steps are involved: Step 1: Obtain an image of the circuit diagram using an optical scanning device or a digital camera; Step 2: Preprocess the image, including denoising, grayscale, binarization, edge detection and morphological operations; Step 3: Use the deep learning model YOLOv5 to identify components in the preprocessed image and determine the bounding box coordinates and category information of the components; Step 4: Based on the bounding box coordinates and category information of the component, the component port is finely identified, including determining the position and orientation of the port; Step 5: Use optical character recognition technology to identify the text in the circuit diagram to eliminate the interference of text on wire identification; Step 6: Perform wire recognition on the image, including Hough line detection and wire jump processing, to determine the starting and ending coordinates of the wire; Step 7: Match the identification results of components, ports, and wires to construct the topology of the circuit diagram; Step 8: Generate a circuit netlist based on the topological structure, including component types, port connection information, and wire connection information; Step 9: Troubleshoot the generated netlist, including troubleshooting incorrect connections and checking the integrity of the netlist numbering; Step 10: Export the corrected netlist in JSON format to ensure data scalability and facilitate subsequent processing.

2. A circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step three, the training process of the deep learning model YOLOv5 includes: collecting component image data in the circuit diagram, marking the bounding box coordinates and category information of the components, dividing the marked data set into a training set and a validation set, using the training set to train the YOLOv5 model, and testing it on the validation set to obtain the model's precision and recall rate indicators.

3. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step 4, the method for fine port identification includes: For each identified component, determine the possible position and direction of the port based on its category information; Extract local features from the image within the bounding box of the component and use deep learning models or traditional image processing algorithms to determine the specific location and orientation of the port; The center coordinates of the port are calculated and associated with the bounding box coordinates of the component to form a corresponding relationship between the port and the component.

4. A circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step five, the optical character recognition technology uses an OCR tool to recognize the text in the circuit diagram, including character recognition and position positioning of the text, and removes the recognized text information from the image to avoid interference with wire recognition.

5. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step six, the Hough line detection method includes: Perform edge detection on the image with text and component frames removed, and extract edge pixels in the image; Convert edge pixels to Hough space and count the votes for different line parameters using the accumulator array; Determine the straight line in the image based on the number of votes and obtain the coordinates of the starting and ending points of the straight line; The Hough line detection method is divided into two stages: Stage 1: initial line extraction; Perform edge detection on the image; Use probabilistic Hough transform to detect all possible straight line segments; Get the endpoint coordinates of each line; Phase 2: Greedy coupling as wire; Set a distance threshold and use a greedy algorithm to merge line segments that are close to each other and have the same direction into one line.

6. A circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step six, the jumper processing method includes: Design specific convolution kernels to detect different types of node connections in circuit diagrams, including current nodes, cross nodes, and cross-line nodes; Alternatively, a trained deep learning model can be used to automatically learn features in the circuit diagram and distinguish node types; Determine the node connection method based on the detection results and process the wires accordingly.

7. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step seven, the matching method includes: Determine the connection relationship between the port and the component based on the bounding box coordinates of the component and the position information of the port; Determine the connection relationship between the wire and the port based on the starting and ending coordinates of the wire; Construct the topological structure of the circuit diagram, including nodes, edges and connection relationships.

8. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step eight, the method for generating a circuit netlist includes: Integrate the component type, port connection information and wire connection information to form a netlist data structure; Assign unique identifiers to each component and wire to ensure the uniqueness and accuracy of the netlist; Verify and optimize the netlist data, including checking the legitimacy of connection relationships and eliminating redundant information.

9. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step nine, the error troubleshooting method includes: Verify the validity of the connection object model to ensure that each connection object is correctly defined in the netlist; Check the integrity of the netlist number to ensure that each component is connected to at least one valid wire; Eliminate isolated lines and dangling components, and correct incorrect connections in the circuit diagram.

10. The circuit netlist generation method supporting multi-stage reasoning of a deep learning model according to claim 1, characterized in that: In step 10, the output content in JSON format includes: Component list, each component contains type, identifier and port connection information; A list of wires, each containing the start and end coordinates and the connected port information; Special port list, including VDD and GND power and ground connection port information; The correspondence between the netlist numbers and the actual numbers ensures that they are consistent with the numbers in the circuit diagram.

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