Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor material layer which is used for forming at least two grooves; a first hard mask layer is formed on one side of the semiconductor material layer, the first hard mask layer is etched to form at least two openings, and the openings are used for defining the key size of the groove; forming an etching guide structure in the opening, wherein the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer; forming a dielectric layer covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure; forming a photoresist layer on one side, deviating from the first hard mask layer, of the dielectric layer, and performing exposure of different depths on the photoresist layer at the corresponding position of the opening to form photoresist grooves of different depths; and performing one-time etching on the etching guide structure and the semiconductor material layer based on the photoresist grooves with different depths so as to form grooves with different depths in the semiconductor material layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In the field of semiconductor manufacturing, it is often necessary to prepare grooves of different depths in a semiconductor and then fill the grooves with materials to further form structures of different depths, such as forming shallow trench isolation (STI) structures of different depths.

[0003] Traditional processes typically involve two photolithography and two etching steps to fabricate dual shallow trench isolation structures of varying depths. Specifically, the first and second trenches are first etched to the same depth. The first trench is then covered with photoresist, and the second trench is further etched to the desired depth. During this process, the etch mask surrounding the second trench is consumed, while the etch mask surrounding the first trench remains protected by the photoresist, resulting in a height difference in the etch mask. As the second trench is further etched, the opening at the top of the second trench expands further, becoming larger than that at the top of the first trench. This results in significant deviations in the critical dimension (CD) of the dual shallow trench isolation structure, impacting the dimensional control of the active area. Furthermore, the second trench is etched twice, resulting in different sidewall slopes. Typically, the first etch results in a larger slope, while the second etch results in a smaller slope, resulting in poor morphology in the second trench.

[0004] Therefore, preparing grooves of different depths according to conventional process methods will result in reduced precision and yield in producing semiconductor structures. Summary of the Invention

[0005] Based on this, it is necessary to provide a method for preparing a semiconductor structure to address the problems in the above background technology, which can at least avoid the height difference of the etching mask and the critical dimension deviation of the groove, and improve the accuracy and yield of the production of semiconductor structures.

[0006] To achieve the above-mentioned and other related objectives, one aspect of the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0007] Providing a semiconductor material layer, wherein the semiconductor material layer is used to form at least two grooves;

[0008] forming a first hard mask layer on one side of the semiconductor material layer, and etching the first hard mask layer to form at least two openings, wherein the openings are used to define a critical dimension of the groove;

[0009] forming an etch guide structure in the opening, wherein an upper surface of the etch guide structure is higher than an upper surface of the first hard mask layer;

[0010] forming a dielectric layer covering the first hard mask layer and the etch guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etch guide structure;

[0011] forming a photoresist layer on a side of the dielectric layer away from the first hard mask layer, and exposing the photoresist layer to different depths at corresponding positions of the opening to form photoresist grooves of different depths;

[0012] The etching guide structure and the semiconductor material layer are etched at one time based on the photoresist grooves of different depths, so as to form grooves of different depths in the semiconductor material layer.

[0013] In one embodiment, the etching selectivity ratio between the etch guide structure and the first hard mask layer is greater than a preset value, so that when the etch guide structure and the semiconductor material layer are etched at one time, the size of the opening in the first hard mask layer remains unchanged.

[0014] In one embodiment, the first hard mask layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the etch guide structure includes at least one of an organic dielectric material, a spin-on carbon material, and amorphous carbon.

[0015] In one embodiment, forming an etch guide structure in the opening includes:

[0016] forming a soft film layer, wherein the soft film layer covers the first hard mask layer and the opening;

[0017] forming a second mask layer on a side of the soft film layer facing away from the first hard mask layer, and patterning the second mask layer based on the position of the opening to form a patterned second mask layer;

[0018] The soft film layer is etched based on the patterned second mask layer to form an etch guide structure, at least a portion of the etch guide structure is located in the opening, and an upper surface of the etch guide structure is higher than an upper surface of the first hard mask layer.

[0019] In one embodiment, exposing the photoresist layer to different depths at corresponding positions of the opening to form photoresist grooves of different depths includes:

[0020] The photoresist layer is exposed based on a half-tone mask, wherein the semi-transparent portion and the transparent portion of the half-tone mask are respectively located at corresponding positions of at least two openings, so as to form photoresist grooves of different depths in the photoresist layer.

[0021] In one embodiment, performing one-time etching on the etch guide structure and the semiconductor material layer based on photoresist grooves of different depths includes:

[0022] performing a dry etching process, etching the etch guide structure using a first etching gas, until one of the openings in the first hard mask layer exposes a top surface of the semiconductor material layer;

[0023] The dry etching process is continued, and the second etching gas is switched to etch the semiconductor material layer until the grooves of different depths in the semiconductor material layer reach a predetermined depth.

[0024] In one embodiment, the first etching gas includes oxygen, and the second etching gas includes at least one of a chlorine-based gas, a fluorine-based gas, and a bromine-based gas.

[0025] In one embodiment, the semiconductor material layer includes a semiconductor substrate, and the grooves of different depths are used to form a double shallow groove isolation structure of different depths.

[0026] In one embodiment, after forming grooves of different depths in the semiconductor material layer, the step further includes removing the dielectric layer to expose the upper surface of the first hard mask layer, and the upper surface of the first hard mask layer is flat.

[0027] Another aspect of the present invention provides a semiconductor structure comprising:

[0028] The grooves of different depths are prepared according to any one of the above methods for preparing a semiconductor structure.

[0029] According to the semiconductor structure and preparation method provided by the present invention, before forming grooves of different depths in the semiconductor material layer, an opening for defining the critical dimensions of the groove is first formed in the hard mask layer, and then an etching guide structure penetrating the hard mask layer and the dielectric layer is formed in the opening, a photoresist layer is formed on the etching guide structure, photoresist grooves of different depths are formed by performing exposure of different depths on the photoresist layer, and the etching guide structure and the semiconductor material layer are etched based on the photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer, thereby avoiding deviations in the critical dimensions of the grooves and avoiding height differences in the hard mask layer. The sidewall morphology of the formed grooves is uniform, thereby improving the performance of the semiconductor structure and increasing the yield rate of the generated semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to better describe and illustrate the embodiments and / or examples of the applications disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed applications, the presently described embodiments and / or examples, and any of the best modes currently understood for these applications.

[0031] Figure 1 A schematic diagram of a semiconductor structure provided in the prior art;

[0032] Figure 2is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0033] Figure 3A 1 is a schematic cross-sectional view of a structure obtained after an opening is formed in the first mask layer in step S202 of the method for preparing a semiconductor structure provided in one embodiment;

[0034] Figure 3B Schematic diagram of the cross-sectional structure of the obtained structure after the soft film layer and the second mask layer are formed in step S203 of the method for preparing a semiconductor structure provided in one embodiment;

[0035] Figure 3C Schematic diagram of the cross-sectional structure of the structure obtained after the etching guide structure is formed in step S203 of the method for preparing a semiconductor structure provided in one embodiment;

[0036] Figure 3D Schematic diagram of a cross-sectional structure of a structure obtained after forming a dielectric layer in step S204 of a method for preparing a semiconductor structure provided in one embodiment;

[0037] Figure 3E Schematic diagram of the cross-sectional structure of the obtained structure after forming photoresist grooves of different depths in step S205 of the method for preparing a semiconductor structure provided in one embodiment;

[0038] Figure 3F Schematic diagram of the cross-sectional structure of a structure obtained by etching the guide structure in step S206 of the method for preparing a semiconductor structure provided in one embodiment;

[0039] Figure 3G Schematic diagram of the cross-sectional structure of a structure obtained by etching the semiconductor material layer in step S206 of the method for preparing a semiconductor structure provided in one embodiment;

[0040] Figure 3H Schematic diagram of the cross-sectional structure of the structure obtained after removing the dielectric layer in the method for preparing the semiconductor structure provided in one embodiment;

[0041] Figure 4 Schematic diagram of the cross-sectional structure of an etching guide structure formed when there is an overlay accuracy problem provided in one embodiment.

[0042] Description of reference numerals:

[0043] 100. Semiconductor material layer; 101. First groove; 102. Second groove; 103. First dielectric layer; 110. First hard mask layer; 111. First opening; 112. Second opening; 120. Soft film layer; 121. First etch guide structure; 122. Second etch guide structure; 130. Second mask layer; 140. Second dielectric layer; 150. Third hard mask layer; 160. Bottom anti-reflective layer; 170. Photoresist layer; 171. First photoresist groove; 172. Second photoresist groove; 180. Half-tone mask; 181. Semi-transparent portion; 182. Transparent portion. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0046] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0047] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. The regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.

[0050] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed at will, and the component layout type may also be more complicated.

[0051] Reference Figure 1As shown in the figure, two grooves of different depths are prepared using a traditional process method. The etching masks of the two grooves have a height difference. The opening size of the top of the deep groove is larger than the opening size of the top of the shallow groove. The critical dimensions (CD) of the two grooves deviate greatly, and the slope of the sidewall of the deep groove is different.

[0052] In view of the above problems, the present invention provides a method for preparing a semiconductor structure, such as Figure 2 As shown, the following steps are included:

[0053] Step S201: providing a semiconductor material layer, wherein the semiconductor material layer is used to form at least two grooves;

[0054] Step S202: forming a first hard mask layer on one side of the semiconductor material layer, and etching the first hard mask layer to form at least two openings, where the openings are used to define a critical dimension of the groove;

[0055] Step S203: forming an etching guide structure in the opening, wherein the upper surface of the etching guide structure is higher than the upper surface of the first hard mask layer;

[0056] Step S204: forming a dielectric layer covering the first hard mask layer and the etching guide structure, wherein the upper surface of the dielectric layer is flush with the upper surface of the etching guide structure;

[0057] Step S205: forming a photoresist layer on a side of the dielectric layer away from the first hard mask layer, and exposing the photoresist layer to different depths at corresponding positions of the opening to form photoresist grooves of different depths;

[0058] Step S206 : performing a one-time etching on the etch guide structure and the semiconductor material layer based on the photoresist grooves of different depths, so as to form grooves of different depths in the semiconductor material layer.

[0059] First, execute step S201, refer to Figure 3A , providing a semiconductor material layer 100, the semiconductor material layer is used to form at least two grooves.

[0060] In one embodiment, the semiconductor material layer 100 includes, but is not limited to, at least one of a substrate and an interlayer dielectric layer. The grooves formed in the substrate can be used to further form shallow trench isolation structures, field oxide structures, etc., and the grooves formed in the interlayer dielectric layer can be used to further form interconnect structures, bonding structures, etc. Specifically, the substrate can be at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).

[0061] Next, execute step S202, refer to Figure 3A As shown, a first hard mask layer 110 is formed on one side of the semiconductor material layer 100 , and the first hard mask layer 110 is etched to form at least two openings, where the openings are used to define a critical dimension of the groove.

[0062] In one embodiment, before forming the first hard mask layer 110, the step of forming the first dielectric layer 103 is also included. Optionally, the material of the first dielectric layer includes but is not limited to silicon oxide (SiO2), and the first dielectric layer 103 can be formed by processes familiar to those skilled in the art, such as thermal oxidation. Next, a first hard mask layer 110 is formed on the first dielectric layer 103. The material of the first hard mask layer 110 includes but is not limited to at least one of silicon nitride (SiN), silicon oxide (SiO2), and silicon oxynitride (SiON). Optionally, the first hard mask layer 110 is made of silicon nitride (SiN), and the first hard mask layer 110 can be formed by process technologies familiar to those skilled in the art, such as chemical vapor deposition (CVD). Next, a patterned photoresist layer (not shown) is formed on the first hard mask layer 110, and the first hard mask layer 110 is etched using the patterned photoresist layer as a mask until the surface of the semiconductor material layer 100 is exposed, so as to form at least two openings in the first hard mask layer 110. Specifically, refer to Figure 3A As shown, a first opening 111 and a second opening 112 are formed in the first hard mask layer 110. Furthermore, the first opening 111 is used to define the critical dimension (CD) of the first groove, and the second opening 112 is used to define the CD of the second groove. Optionally, the CDs of the first groove and the second groove are the same, so the widths of the first opening 111 and the second opening 112 are the same. Furthermore, the thickness of the first hard mask layer 110 is less than the width of the opening. By making the thickness of the first hard mask layer 110 less than the width of the opening, the width of the opening formed in the first hard mask layer 110 is uniform, and the cross-section of the opening is rectangular, avoiding a situation where the width of the upper portion of the opening is greater than the width of the lower portion of the opening, resulting in the opening forming an inverted trapezoidal shape.

[0063] Next, execute step S203, refer to Figures 3B to 3C As shown, an etch guide structure is formed in the opening, wherein the upper surface of the etch guide structure is higher than the upper surface of the first hard mask layer. Exemplarily, forming the etch guide structure in the opening includes: forming a soft film layer, the soft film layer covering the first hard mask layer and the opening; forming a second mask layer on a side of the soft film layer facing away from the first hard mask layer, and patterning the second mask layer based on the position of the opening to form a patterned second mask layer; etching the soft film layer based on the patterned second mask layer to form the etch guide structure, wherein at least a portion of the etch guide structure is located in the opening, and the upper surface of the etch guide structure is higher than the upper surface of the first hard mask layer.

[0064] In one embodiment, first refer to Figure 3B As shown, a soft film layer 120 is formed, and the soft film layer 120 covers the first hard mask layer 110 and fills the first opening 111 and the second opening 112. The material of the soft film layer 120 includes but is not limited to at least one of an organic dielectric layer (ODL) material, a spin-on-carbon (SOC) material, and amorphous carbon. The soft film layer 120 can be formed by a coating method, a spin coating method, or other process techniques familiar to those skilled in the art. Next, a photoresist layer is formed on the soft film layer 120 as a second mask layer 130, and then the second mask layer 130 is patterned according to the position of the opening in the first hard mask layer 110. Specifically, the photoresist at the position corresponding to the opening is retained, and the photoresist at other positions is removed to form a patterned second mask layer 130, as shown in FIG. Figure 3B Next, the soft film layer 120 is etched using the patterned second mask layer 130 as a mask to form etching guide structures in and above the openings. Specifically, a first etching guide structure 121 is formed in and above the first opening 111, and a second etching guide structure 122 is formed in and above the second opening 112. Figure 3C shown.

[0065] In one embodiment, Figure 3C The morphology of the desired etching guide structure formed according to the above steps is shown. However, in the actual process, there is an overlay accuracy (OVL) problem, and the morphology of the formed etching guide structure is as follows. Figure 4 As shown, the top and bottom widths of the etch guide structure are uneven, with the bottom width being greater than the top. Consequently, the sidewalls of the etch guide structure form an angle α with the surface of the first mask layer. Tan(α) = x / y, where x represents the thickness of the soft mask layer and y represents the overlap between the etch guide structure and the first hard mask. Taking a 40nm process as an example, if the overlay accuracy (OVL) is 5nm (i.e., y = 5nm), the post-lithography linewidth (ADI) is 62nm. The angle α is approximately 87°, and x = 954Å. Therefore, controlling the thickness of the soft mask layer 120 to above 954Å can resolve the 5nm OVL issue. Furthermore, setting the thickness of the soft mask layer 120 to 2000Å can resolve the OVL issue above 10nm.

[0066] In one embodiment, taking the thickness of the first hard mask layer 110 as 50 nm to 60 nm and the width of the opening formed in the first hard mask as 62 nm as an example, the line width dimension (ADI) of the etch guide structure after the photolithography process is 62 nm. Optionally, the thickness of the soft film layer 120 is set to 100 nm to 150 nm, and the ratio of the thickness of the soft film layer to the thickness of the first hard mask layer ranges from 2:1 to 3:1. Furthermore, the height of the formed etch guide structure ranges from 150 nm to 200 nm, and the ratio of the height of the etch guide structure to the thickness of the first hard mask layer ranges from 3:1 to 4:1.

[0067] Next, execute step S204, refer to Figure 3D As shown, a second dielectric layer 140 is formed to cover the first hard mask layer 110 and the etch guide structure. The upper surface of the second dielectric layer 140 is flush with the upper surface of the etch guide structure.

[0068] In one embodiment, the material of the second dielectric layer 140 includes but is not limited to at least one of silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON). Optionally, the second dielectric layer 140 is made of silicon oxide (SiO2). The second dielectric layer 140 can be formed by a process technology familiar to those skilled in the art, such as chemical vapor deposition (CVD). After the second dielectric layer 140 is formed, chemical mechanical polishing (CMP) is further performed to make the upper surface of the second dielectric layer 140 flush with the upper surface of the etch guide structure, as shown in FIG. Figure 3D shown.

[0069] Next, execute step S205, refer to Figure 3E As shown, a photoresist layer 170 is formed on a side of the second dielectric layer 140 away from the first hard mask layer 110 , and the photoresist layer 170 is exposed to different depths at corresponding positions of the opening to form photoresist grooves of different depths.

[0070] In one embodiment, before forming the photoresist layer on the second dielectric layer 140, the process further includes sequentially forming a third hard mask layer 150 and a bottom anti-reflective layer 160 on the second dielectric layer 140. The material of the third hard mask layer 150 includes, but is not limited to, at least one of silicon oxynitride (SiON), silicon nitride (SiN), and silicon oxide (SiO2). Optionally, silicon oxynitride (SiON) is used for the third hard mask layer 150. Chemical vapor deposition (CVD) or other process techniques familiar to those skilled in the art can be used to form the third hard mask layer 150. The material of the bottom anti-reflective layer 160 includes, but is not limited to, amorphous carbon or other organic anti-reflective materials. Coating, spin coating, or other process techniques familiar to those skilled in the art can be used to form the bottom anti-reflective layer 160. The photoresist layer 170 includes either a positive photoresist or a negative photoresist. Positive photoresist can be used for the photoresist layer 170. Coating, spin coating, or other process techniques familiar to those skilled in the art can be used to form the photoresist layer 170.

[0071] Exemplarily, exposing the photoresist layer to different depths at corresponding positions of the openings to form photoresist grooves of different depths includes: exposing the photoresist layer 170 based on a half-tone mask 180, the semi-transparent portion 181 and the transparent portion 182 of the half-tone mask 180 being respectively located at corresponding positions of at least two openings to form photoresist grooves of different depths in the photoresist layer 170.

[0072] In one embodiment, referring to Figure 3E As shown, a half-tone mask 180 is used as a mask for the photoresist layer 170. The half-tone mask 180 includes at least a semi-transparent portion 181 and a transparent portion 182. The semi-transparent portion 181 and the transparent portion 182 are arranged corresponding to the openings in the first hard mask layer 110. Next, exposures of different depths are performed using the half-tone mask 180 as a mask for the photoresist layer 170. The photoresist at the semi-transparent portion 181 forms a first photoresist groove 171. The width of the first photoresist groove 171 is equal to the width of the first opening 111 and the width of the first etching guide structure 121. The photoresist at the transparent portion 182 forms a second photoresist groove 172. The width of the second photoresist groove 172 is equal to the width of the second opening 112 and the width of the second etching guide structure 122. Since the photoresist layer 170 adopts positive photoresist, the depth of the formed first photoresist groove 171 is smaller than the depth of the second photoresist groove 172, as shown in FIG. Figure 3E shown.

[0073] exist Figure 4In the example shown, when there is an overlay (OVL) problem causing the bottom width of the etch guide structure to be wider than the top width, the widths of the semi-transparent portion 181 and the transparent portion 182 need to be the same as the width of the widest part of the etch guide structure, for example 72 nm.

[0074] Next, execute step S206, refer to Figures 3F to 3H As shown, the etch guide structure and the semiconductor material layer 100 are etched at one time based on the photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer 100. Exemplarily, the etch guide structure and the semiconductor material layer are etched at one time based on the photoresist grooves of different depths, including: performing a dry etching process, etching the etch guide structure using a first etching gas until one of the openings in the first hard mask layer exposes the top surface of the semiconductor material layer; continuing the dry etching process, switching to a second etching gas to etch the semiconductor material layer, until the grooves of different depths in the semiconductor material layer reach a predetermined depth.

[0075] In one embodiment, a one-time dry etching process is performed to first etch the photoresist layer 170 until the first photoresist groove 171 or the second photoresist groove 172 exposes the top surface of the bottom anti-reflective layer 160. Figure 3E As shown, when the second photoresist groove 172 exposes the top surface of the bottom anti-reflection layer 160 without etching, the photoresist layer does not need to be etched. Next, the bottom anti-reflection layer 160 and the third hard mask layer 150 exposed by the second photoresist groove 172 are etched away until the second etch guide structure 122 is exposed.

[0076] Next, oxygen (O2) may be used as the first etching gas to etch the etching guide structure. When a portion of the second etching guide structure 122 is removed by etching, the first photoresist groove 171 exposes the top surface of the bottom anti-reflection layer 160. The etching gas is switched to etch away the bottom anti-reflection layer 160 and the third hard mask layer 150 exposed by the first photoresist groove 171. Then, the first etching gas is switched back to simultaneously etch the first etching guide structure 121 and the second etching guide structure 122 until the second etching guide structure 122 is completely etched and the second opening 112 exposes the surface of the first dielectric layer 103. Figure 3F As shown, the etching gas is then switched to etch away the first dielectric layer 103 exposed by the second opening 112 until the top surface of the semiconductor material layer 100 is exposed. While etching the first and second etch guide structures 121 and 122, the photoresist layer 170, the bottom anti-reflective layer 160, and the third hard mask layer 150 are removed.

[0077] Next, at least one of a chlorine-based gas, a fluorine-based gas, and a bromine-based gas can be used as a second etching gas to etch the semiconductor material layer 100. The chlorine-based gas includes one or a combination of chlorine or carbon tetrachloride, the fluorine-based gas includes one or a combination of commonly used fluorine-containing gases such as CF4, CHF3, NF3, SF6, and the bromine-based gas is one or a combination of bromine or hydrogen bromide. When a portion of the semiconductor material layer 100 is removed, the first etching guide structure 121 is completely removed to expose the top surface of the first dielectric layer 103, and then the etching gas is switched to etch away the first dielectric layer 103 exposed by the first opening 111, and then the second etching gas is switched back to simultaneously etch the semiconductor material layer 100 until the groove in the semiconductor material layer 100 reaches a predetermined depth, forming a first groove 101 and a second groove 102, with reference to FIG. Figure 3G The depth of the first groove 101 is less than that of the second groove 102 , the first groove 101 is a shallow groove, and the second groove 102 is a deep groove.

[0078] In one embodiment, after forming grooves of different depths in the semiconductor material layer 100, the second dielectric layer 140 is removed to expose the upper surface of the first hard mask layer 110, so as to form Figure 3H The first hard mask layer 110 formed according to this embodiment has a flat upper surface and a uniform thickness without any "steps" caused by height differences.

[0079] In one embodiment, it should be noted that the first etching gas has a high etching selectivity for the etch guide structure and the first etch mask layer, and its etching selectivity is greater than a preset value. Therefore, when the first etching gas etches the etch guide structure, the size of the opening in the first hard mask layer 110 remains unchanged, that is, the widths of the first opening 111 and the second opening 112 remain unchanged. Therefore, the critical dimensions of the first groove 101 and the second groove 102 formed in the semiconductor material layer 100 remain unchanged, that is, the top widths of the first groove 101 and the second groove 102 are equal. After the etch guide structure is removed by etching, an etch guide channel is formed in the second dielectric layer 140 and the first hard mask layer 110. Due to the presence of the etch guide channel, the top width and bottom width of the groove formed in the semiconductor material layer 100 are the same or similar. Therefore, the sidewall slope of the groove formed in the semiconductor material layer 100 is 90° or close to 90°, and the sidewall of the groove is substantially perpendicular to the bottom surface, thereby preventing the groove formed in the semiconductor material layer 100 from tilting or even having different sidewall slopes.

[0080] This concludes the introduction to the relevant steps of the method for fabricating a semiconductor structure according to an embodiment of the present invention. It is understood that the method for fabricating a semiconductor structure according to this embodiment includes not only the aforementioned steps but may also include other necessary steps before, during, or after the aforementioned steps, all of which are within the scope of this embodiment of the manufacturing method.

[0081] The present invention also provides a semiconductor structure, referring to Figure 3H As shown, including:

[0082] Grooves of different depths are formed according to the method for preparing the semiconductor structure as described above.

[0083] In one embodiment, the semiconductor material layer 100 includes, but is not limited to, at least one of a substrate and an interlayer dielectric layer. The grooves formed in the substrate can be used to further form shallow trench isolation structures, field oxide structures, etc., and the grooves formed in the interlayer dielectric layer can be used to further form interconnect structures, bonding structures, etc. Specifically, the substrate can be at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).

[0084] In one embodiment, a first groove 101 and a second groove 102 of different depths are formed in the semiconductor material layer 100, wherein the depth of the first groove 101 is less than the depth of the second groove 102, the first groove 101 being a shallow groove, and the second groove 102 being a deep groove. Furthermore, the critical dimensions of the first groove 101 and the second groove 102 are equal, that is, the top widths of the first groove 101 and the second groove 102 are equal, thereby avoiding deviation in the critical dimensions of the first groove 101 and the second groove 102. The sidewalls of the first groove 101 and the second groove 102 have a slope of 90° or close to 90°, and the sidewalls of the grooves are substantially perpendicular to the bottom surface, thereby avoiding tilted sidewalls or even different slopes of the sidewalls of the grooves.

[0085] In one embodiment, a first hard mask layer 110 is formed on one side of the semiconductor material layer 100 . The upper surface of the first hard mask layer 110 is flat and the overall thickness is uniform without any “steps” caused by height differences.

[0086] The specific structure of the semiconductor structure can refer to the description of the corresponding part above, and will not be repeated here for the sake of brevity.

[0087] According to the semiconductor structure and preparation method provided by the present invention, before forming grooves of different depths in the semiconductor material layer, an opening for defining the critical dimensions of the groove is first formed in the hard mask layer, and then an etching guide structure penetrating the hard mask layer and the dielectric layer is formed in the opening, a photoresist layer is formed on the etching guide structure, photoresist grooves of different depths are formed by performing exposure of different depths on the photoresist layer, and the etching guide structure and the semiconductor material layer are etched based on the photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer, thereby avoiding deviations in the critical dimensions of the grooves and avoiding height differences in the hard mask layer. The sidewall morphology of the formed grooves is uniform, thereby improving the performance of the semiconductor structure and increasing the yield rate of the generated semiconductor structure.

[0088] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0089] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0090] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present application, and such modifications and improvements are all within the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: providing a semiconductor material layer, wherein the semiconductor material layer is used to form at least two grooves; forming a first hard mask layer on one side of the semiconductor material layer, and etching the first hard mask layer to form at least two openings, wherein the openings are used to define a critical dimension of the groove; forming an etch guide structure in the opening, wherein an upper surface of the etch guide structure is higher than an upper surface of the first hard mask layer; forming a dielectric layer covering the first hard mask layer and the etch guide structure, wherein an upper surface of the dielectric layer is flush with an upper surface of the etch guide structure; forming a photoresist layer on a side of the dielectric layer facing away from the first hard mask layer, and exposing the photoresist layer to different depths at corresponding positions of the opening to form photoresist grooves of different depths; The etching guide structure and the semiconductor material layer are etched at one time based on the photoresist grooves of different depths to form grooves of different depths in the semiconductor material layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: An etching selectivity ratio between the etch guide structure and the first hard mask layer is greater than a preset value, so that when the etch guide structure and the semiconductor material layer are etched at one time, a size of the opening in the first hard mask layer remains unchanged.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The first hard mask layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the etch guide structure includes at least one of organic dielectric material, spin-on carbon material, and amorphous carbon.

4. The method for preparing a semiconductor structure according to claim 1, wherein: Forming an etch guide structure in the opening includes: forming a soft film layer, wherein the soft film layer covers the first hard mask layer and the opening; forming a second mask layer on a side of the soft film layer facing away from the first hard mask layer, and patterning the second mask layer based on the position of the opening to form a patterned second mask layer; The soft film layer is etched based on the patterned second mask layer to form the etch guide structure, at least a portion of the etch guide structure is located in the opening, and an upper surface of the etch guide structure is higher than an upper surface of the first hard mask layer.

5. The method for preparing a semiconductor structure according to claim 1, wherein: Exposing the photoresist layer at different depths at corresponding positions of the opening to form photoresist grooves of different depths includes: The photoresist layer is exposed based on a half-tone mask, wherein a semi-transmissive portion and a transparent portion of the half-tone mask are respectively located at corresponding positions of the at least two openings, so as to form photoresist grooves of different depths in the photoresist layer.

6. The method for preparing a semiconductor structure according to claim 1, wherein: Performing one-time etching on the etching guide structure and the semiconductor material layer based on the photoresist grooves of different depths includes: Performing a dry etching process to etch the etch guide structure using a first etching gas until one of the openings in the first hard mask layer exposes a top surface of the semiconductor material layer; The dry etching process is continued, and a second etching gas is switched to etch the semiconductor material layer until the grooves of different depths in the semiconductor material layer reach a predetermined depth.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The first etching gas includes oxygen, and the second etching gas includes at least one of chlorine-based gas, fluorine-based gas, and bromine-based gas.

8. The method for preparing a semiconductor structure according to claim 1, wherein: The semiconductor material layer includes a semiconductor substrate, and the grooves of different depths are used to form a double shallow groove isolation structure of different depths.

9. The method for preparing a semiconductor structure according to claim 1, wherein: After forming grooves of different depths in the semiconductor material layer, the method further includes removing the dielectric layer to expose the upper surface of the first hard mask layer, wherein the upper surface of the first hard mask layer is flat.

10. A semiconductor structure, characterized in that include: Grooves of different depths are prepared according to the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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