ESD clamped transistor body contact induced clamping device activation

Abstract

An ESD circuit includes an ESD clamping device having an ESD clamping transistor. The ESD clamp transistor has two sets of one or more body contacts. One set is coupled to the supply voltage rail and the other set is coupled to the clamp activation circuit. The clamping activation circuit is coupled to a clamping device. The activation circuit conducts the clamping device to transfer charge between the supply voltage rails during a sufficiently severe electrical stress event affecting the supply voltage rails.

Description

Technical Field

[0001] The present invention relates to an ESD circuit having a clamp device activation circuit coupled to one or more body contacts of an ESD clamp transistor. Background Art

[0002] Some semiconductor dies utilize electrostatic discharge (ESD) clamping devices to discharge charge from ESD events that impact the die terminals. An example of an ESD clamping device is a clamping transistor such as a field effect transistor (FET) (eg, NFET).

[0003] An ESD event is a type of electrical stress event. An ESD event can occur when a charged object (e.g., a human finger) inadvertently contacts a conductive surface of a semiconductor die (e.g., a contact pad) or a conductive surface of a semiconductor die package coupled to a pad, whereby a charge at an elevated voltage is applied to the conductive surface as a result of the contact. This charge, at an elevated voltage, can cause a voltage differential across the semiconductor die devices that can exceed the safe operating area of ​​the devices and damage them. An ESD event can also occur when a charged conductive surface of a circuit contacts an external object, whereby charge is transferred between the conductive surface and the external object. Semiconductor dies can experience other types of electrical stress events, such as overcurrent conditions or overvoltage conditions. Summary of the Invention

[0004] Features specifically shown or described with respect to one embodiment set forth herein may be implemented in other embodiments set forth herein.

[0005] In one embodiment, a circuit includes an ESD clamp device comprising a clamp transistor. The clamp transistor includes a first current terminal coupled to a first power supply voltage rail and a second current terminal coupled to a second power supply voltage rail. When rendered conductive, the clamp transistor conducts electricity to transfer charge between the first power supply voltage rail and the second power supply voltage rail. During normal operation, the clamp transistor is biased into a non-conductive state. The clamp transistor includes a first set of one or more body contacts coupled to one of the first power supply voltage rail or the second power supply voltage rail, and a second set of one or more body contacts. The circuit includes an electrostatic discharge (ESD) trigger circuit configured to detect an ESD event affecting the first power supply voltage rail. In response to detecting the ESD event, the ESD trigger circuit asserts an output signal to render the clamp transistor conductive. The circuit includes a clamp activation circuit including an input coupled to the second set of one or more body contacts and an output coupled to a control terminal of a clamp device, the clamp device including a first current terminal coupled to the first power supply voltage rail and a second current terminal coupled to the second power supply voltage rail. During a sufficiently severe electrical stress event as indicated by a condition of the second set of one or more body contacts, the clamp activation circuit causes the clamp device to conduct to transfer charge between the first power supply voltage rail and the second power supply voltage rail.

[0006] In one or more embodiments, the clamp activation circuit includes a set transistor including a control terminal coupled to the second set of one or more body contacts;

[0007] In one or more embodiments, the clamping device includes a mirror transistor, the mirror transistor including a first current terminal coupled to the first power supply voltage rail, a second current terminal coupled to the second power supply voltage rail, and a control terminal coupled to the second set of one or more body contacts; wherein the set transistor and the mirror transistor are configured in a current mirror configuration.

[0008] In one or more embodiments, during a sufficiently severe electrical stress event in which impact ionization is generated in the clamp transistor, an impact ionization current flows from the second set of one or more body contacts through the first current terminal and the second current terminal of the set transistor to control the current through the mirror transistor from the first power supply voltage rail to the second power supply voltage rail for transferring charge from the first power supply voltage rail to the second power supply voltage rail.

[0009] In one or more embodiments, the clamping device is the clamping transistor.

[0010] In one or more embodiments, the clamp activation circuit includes a latch transistor having a first current terminal coupled to one of the first supply voltage rail or the second supply voltage rail, and a second current transistor coupled to a control terminal of the clamp transistor.

[0011] In one or more embodiments, during a sufficiently severe electrical stress event, with the clamp transistor in a conductive state in which charge is transferred between the first power supply rail and the second power supply rail, the latch transistor becomes conductive to pull the voltage of the control terminal of the clamp transistor to the voltage of the one of the first power supply voltage rail or the second power supply voltage rail.

[0012] In one or more embodiments, the clamping device includes a second clamping transistor, the second clamping transistor including a first current terminal coupled to the first power supply voltage rail, a second current terminal coupled to the second power supply voltage rail, and a control terminal; the clamp activation circuit includes a signal line, one end of the signal line is coupled to the second set of one or more body contacts, and a second end thereof is coupled to the control terminal of the second clamping transistor.

[0013] In one or more embodiments, the threshold voltage of the second clamping transistor is 0.6 volts or less.

[0014] In one or more embodiments, the clamp activation circuit includes at least one inverter configured in a series signal path between the second set of one or more body contacts and a control terminal of the clamp device.

[0015] In one or more embodiments, a first inverter of the at least one inverter in the series signal path includes a transistor having a threshold voltage of 0.6 volts or less.

[0016] In one or more embodiments, the clamping device includes a second clamping transistor, the second clamping transistor including a first current terminal coupled to the first power supply voltage rail, a second current terminal coupled to the second power supply voltage rail, and a control terminal; the clamp activation circuit includes two inverters, wherein the output of the second inverter in the series signal path is connected to the control terminal of the second clamping transistor.

[0017] In one or more embodiments, the second set of one or more body contacts is connected to a control terminal of a transistor having a threshold voltage of 0.6 volts or less.

[0018] In one or more embodiments, the clamp transistor is implemented in a semiconductor die using a group of one or more segment regions of the semiconductor die, wherein each segment region includes: an active region of alternating elongated source and drain regions separated by a body region; and wherein body contacts of the second set of one or more body contacts of the segment region are located in a middle 10% geometric portion of the active region of the segment region.

[0019] In one or more embodiments, the body contacts of the first set of one or more body contacts are located in an edge region of the one or more segment areas.

[0020] In one or more embodiments, for each segment region, the body contacts in the second group are located in a portion of the body region having a first net conductivity type dopant concentration, wherein the body contacts in the first group are each coupled to the portion of the body region through a second portion of the body region in a path in the body region, and the net conductivity type dopant concentration of the second portion is lower than the first net conductivity type dopant concentration.

[0021] In one or more embodiments, in response to detecting an ESD event, the ESD trigger circuit asserts the output signal to cause the clamp transistor to conduct for a period of time, wherein if the ESD event is a sufficiently severe electrical stress event, then the clamp activation circuit causes the clamp device to conduct for a certain time, including after the period of time.

[0022] In one or more embodiments, during a sufficiently severe electrical stress event, the input of the clamp activation circuit is at a higher voltage than the first set of one or more body contact regions.

[0023] In one or more embodiments, during normal operation, the clamping device is biased to be non-conductive.

[0024] In another embodiment, a circuit includes an ESD clamp transistor. The ESD clamp transistor includes a first current terminal coupled to a first power supply voltage rail and a second current terminal coupled to a second power supply voltage rail. When rendered conductive, the ESD clamp transistor conducts electricity to transfer charge between the first power supply voltage rail and the second power supply voltage rail. During normal operation, the ESD clamp transistor is in a non-conductive state. The ESD clamp transistor includes a first set of one or more body contacts coupled to one of the first power supply voltage rail or the second power supply voltage rail, and a second set of one or more body contacts. The circuit includes an electrostatic discharge (ESD) trigger circuit configured to detect an ESD event affecting the first power supply voltage rail. In response to detecting the ESD event, the ESD trigger circuit asserts an output signal to render the ESD clamp transistor conductive. The circuit includes a clamp activation circuit including an input coupled to the second set of one or more body contacts and an output coupled to a control terminal of a clamp device, the clamp device including a first current terminal coupled to the first power supply voltage rail and a second current terminal coupled to the second power supply voltage rail. During a sufficiently severe electrical stress event in which impact ionization is generated in the ESD clamp transistor as indicated by the second set of one or more body contacts, the clamp activation circuit renders the clamp device conductive to transfer charge between the first and second supply voltage rails.

[0025] In one or more embodiments, the circuit is responsive to detecting an ESD event, the ESD trigger circuit asserting the output signal to cause the ESD clamp transistor to conduct for a period of time, wherein if the ESD event is a sufficiently severe electrical stress event, then the clamp activation circuit causes the clamp device to conduct for a certain time, including after the period of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0027] Figure 1 FIG. 4 is a circuit diagram of a conventional ESD circuit.

[0028] Figure 2 FIG. 4 is a circuit diagram of a conventional ESD circuit.

[0029] Figure 3 FIG. 4 is a circuit diagram of a conventional ESD circuit.

[0030] Figure 4 FIG. 5 is a graph showing the current and voltage of a prior art ESD circuit during an electrical stress event.

[0031] Figure 5FIG. 4 is a circuit diagram of an ESD circuit according to an embodiment of the present invention.

[0032] Figure 6 FIG. 1 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention.

[0033] Figure 7 FIG. 1 is a graph of current and voltage during an electrical stress event of an ESD circuit according to one embodiment of the present invention.

[0034] Figure 8 FIG. 1 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention.

[0035] Figure 9 FIG. 1 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention.

[0036] Figure 10 FIG. 1 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention.

[0037] Figure 11 FIG. 1 is a top view of a portion of a substrate of a semiconductor die according to one embodiment of the present invention.

[0038] Unless otherwise indicated, the use of the same reference numerals in different drawings indicates the same items.The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0039] The following is a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be considered limiting.

[0040] As disclosed herein, an ESD circuit includes an ESD clamp device having an ESD clamp transistor. The ESD clamp transistor has two sets of one or more body contacts. One set is coupled to a power supply voltage rail, and the other set is coupled to a clamp activation circuit. The clamp activation circuit is coupled to the clamp device. During a sufficiently severe electrical stress event affecting the power supply voltage rails, the activation circuit causes the clamp device to conduct electricity to transfer charge between the power supply voltage rails.

[0041] In some embodiments, providing a clamp activation circuit having an input to a second set of one or more body contacts can allow the clamp activation circuit to detect impact ionization conditions of the ESD clamp transistor due to an electrical stress event and provide a mechanism for transferring charge between the supply voltage rails to mitigate the impact ionization, where such a mechanism can operate effectively over a relatively wide temperature range.

[0042] Figure 1FIG1 is a circuit diagram of a prior art ESD circuit 101. ESD circuit 101 includes a trigger circuit 103 and an ESD clamping device implemented using a clamping transistor 105. Clamping transistor 105 is an NFET having a drain connected to a VDD power supply voltage rail 117 and a source connected to a VSS power supply voltage rail 119. The body contact of transistor 105 is connected to the VSS power supply voltage rail 119. The gate of transistor 105 is connected to the output of trigger circuit 103 to receive a TRIGGER signal. Trigger circuit 103 includes a resistor 109 and a capacitor 107, each of which includes a terminal connected to the gate of a PFET 111. The source of PFET 111 is connected to the VDD power supply voltage rail 117. The drain of PFET 111 is connected to the gate of transistor 105 and to resistor 113 to provide the TRIGGER signal.

[0043] The trigger circuit 103 is characterized as an RC trigger circuit and is configured to be activated by a fast rise time voltage difference between the VDD supply voltage rail 117 and the VSS supply voltage rail 119. Prior to an ESD event affecting the VDD supply voltage rail 117, the voltage difference between the voltage at the gate of the PFET 111 and the voltage of the VDD supply voltage rail 117 is less than a threshold voltage of the PFET 111. At the start of a detected ESD event affecting the VDD supply voltage rail 117, the voltage at the gate of the PFET 111 is initially at a low voltage relative to the ESD-raised voltage of the VDD supply voltage rail 117. With the gate of PFET 111 at a low voltage relative to rail 117, PFET 111 begins conducting to bias the gate of ESD clamp transistor 105 from a low voltage, non-conductive state to a high voltage, conductive state, in which clamp transistor 105 becomes conductive to transfer charge from the ESD event on rail 117 to rail 119 to reduce the voltage difference between rails 117 and 119. PFET 111 remains conductive for a predetermined period of time that depends on the RC time constant of resistor 109 and capacitor 107. As the charge on capacitor 107 rises from the increased voltage on the VDD supply voltage rail 117, the voltage at the gate of PFET 111 also rises. When the voltage difference between the voltage of rail 117 and the voltage at the gate of PFET 111 falls below the threshold voltage of PFET 111, the TRIGGER signal is deasserted to the non-conductive bias voltage, and transistor 105 becomes non-conductive.

[0044] Figure 2FIG2 is a circuit diagram of another prior art ESD circuit 201 having a different type of trigger circuit 203, which includes a resistor 207 and a diode string 209 coupled in series between a VDD power supply voltage rail 215 and a VSS power supply voltage rail 217. The gate of a PFET 211 is connected to a node between the resistor 207 and the diode string 209. The source of the PFET 211 is connected to the VDD power supply rail 215, and the drain is connected to the gate of the ESD clamp transistor 205 to provide the TRIGGER signal. A resistor 213 is connected to the gate of the transistor 205 and the VSS power supply rail 217.

[0045] During an ESD event affecting rail 215, the voltage of rail 215 rises above the cumulative threshold voltage of diode string 209. When the voltage difference between rail 215 and the gate of PFET 211 is greater than the threshold voltage of PFET 211, PFET 211 becomes conductive, asserting the trigger signal. With the trigger signal asserted, clamp transistor 205 becomes conductive, discharging the ESD charge from rail 215 to rail 217. As long as the voltage difference between the voltage of rail 215 and the threshold voltage of diode string 209 is greater than the threshold voltage of MTF 211, the TRIGGER signal can be asserted. One problem with using diode string trigger signal control is that the activation and deactivation voltages are relatively sensitive to temperature, especially at higher voltages. Therefore, it can be extremely difficult to achieve proper operation of the trigger circuit over the entire temperature range (e.g., -40°C to 125°C).

[0046] Figure 3 FIG. 3 is a circuit diagram of another prior art ESD circuit. The ESD circuit 301 includes a trigger circuit 303 and an ESD clamp transistor 305 for releasing ESD current from a VDD power supply voltage rail 317 to a VSS power supply voltage rail 319. The trigger circuit 303 is Figure 1 The RC trigger mechanism of trigger circuit 103 is combined with the overvoltage detection diode string 309 mechanism of trigger circuit 203. The conduction time of the RC mechanism of trigger circuit 303 is determined by the RC time constant of resistor 310 and capacitor 307. However, as long as the drain of PFET 311 is above the cumulative threshold voltage of diode string 309 plus the threshold voltage of PFET 311, the TRIGGER signal can remain active. Trigger circuit 303 also includes resistor 313. In some examples, Figure 2 and 3 The diode strings 209 and 309 in the example can be replaced by Zener diodes respectively.

[0047] Problems can arise when an ESD clamp transistor experiences electrical stress for longer than its designed on-time. These electrical stress events are typically longer than the pulse from a typical ESD event. Most ESD events last no longer than 500 nanoseconds, but some electrical stress events can last as long as 5-10 microseconds. Examples of such electrical stress events include cable discharge events or transient ringing events that occur when a semiconductor die (or a board containing a semiconductor die) is connected to some other system or device. Furthermore, electrical stress events can occur during a "hot plug," where two devices are connected together and at least one of the devices is powered on.

[0048] During electrical stress events of less than the maximum intensity for which the ESD clamp transistor is designed (e.g., according to a typical ESD event), the clamp transistor operates entirely in MOS mode to absorb the ESD current and is therefore immune to damage. However, for more intense electrical stress events, when additional mechanisms for current conduction are active, the IV curve of the ESD clamp transistor deviates from the linear MOS mode behavior. In addition to conducting the electrical stress current in MOS mode, the clamp transistor also begins to conduct current generated by impact ionization in the transistor. Where the MOS mode current flows through the ESD clamp transistor from its drain to its source, the impact ionization current flows through the clamp transistor from its drain to its body contact. Generally, the clamp transistor is relatively immune to damage as long as the pulse duration of the stress event is significantly shorter than the on-time of the trigger circuit (103).

[0049] However, if the relatively intense electrical stress pulse lasts longer than the trigger circuit's on-time, the impact ionization mode of operation can damage the clamp transistor. When the clamp transistor conducts current, including the impact ionization current, it generates heat internally, which raises the temperature of the transistor's semiconductor material. If the temperature exceeds a critical limit, the clamp transistor can be damaged.

[0050] When the ESD clamp transistor experiences even more intense electrical stress events, it can be completely damaged. At such intensities, the current generated by internal impact ionization becomes strong enough to bias the internal NPN bipolar transistor of the NFET. In such situations, the transistor can become unstable. When one component of the clamp transistor conducts more current than other components, the internally generated impact ionization current in that region becomes stronger, which increases the total current in that region, leading to even more localized impact ionization and more ionization current, and so on. The end result is that almost all the current is confined to a small subregion of the clamp transistor. This effect is sometimes referred to as "second snapback" or "current filamentation." The typical end result is a short circuit between the drain and source of the ESD clamp transistor. Therefore, because the ESD clamp transistor needs to be non-conductive when the semiconductor die is in normal operation (i.e., when no ESD event or other electrical stress event is occurring), the semiconductor die may no longer operate normally. The severity of an electrical stress event has both an intensity component and a duration component.

[0051] In some cases, the clamp device may experience an electrical stress pulse that lasts longer than the designed on-time of the ESD clamp transistor. This problem can arise when a pulse of a relatively low electrical stress voltage (e.g., between the nominal voltage of VDD and twice the nominal voltage of VDD) is applied to the drain of an RC-triggered clamp device via a cable with significant inductance. For example, a one-leg charger cable may have a parasitic inductance of approximately 300nH.

[0052] When current flows through a device with inductance, the system resists changes in that current. When the current through the inductive device increases, an induced voltage is generated across the device, which counteracts the increase in current. When the current through the inductive device decreases, a similar induced voltage is generated across the device, attempting to maintain the current at its original value. It's important to note that these voltage increases are temporary and diminish over time.

[0053] Figure 4 FIG1 is a graph of current and voltage of clamp transistor 105 during an electrical stress event, wherein a power supply voltage is suddenly applied to the VDD pad (not shown) of the semiconductor die via a cable (not shown) containing a relatively large amount of inductance. Due to the sudden application of voltage, trigger circuit 103 triggers and asserts the TRIGGER signal to make transistor 105 conductive for a certain period of time (ON-TIME), causing transistor 105 to begin conducting current. At the end of the ON-TIME period, the conductivity of transistor 105 becomes increasingly poor. This is achieved by Figure 4 At the end of the ON-TIME period, OFFDuring this time interval, depending on the situation (although Figure 4 The example shows that it remains the same), the voltage seen by the clamp transistor 105 may remain the same, increase, or decrease.

[0054] In t OFF At a given point, transistor 105 turns completely off, which often happens abruptly because the gate-source bias voltage of transistor 105 drops below its threshold voltage. Because the cables that deliver voltage to semiconductor die VDD rail 117 have relatively high inductance, this sudden decrease in current causes an induced voltage spike 401 in the cables, which appears at the drain of clamp transistor 105. In some cases, this voltage spike can generate an impact ionization current in transistor 105 that can damage it. The induced voltage overshoot scenario described above is just one of several mechanisms by which an overvoltage condition can occur in an RC-triggered clamp device.

[0055] What is needed is an ESD circuit that can selectively continue to discharge electrical stress charge after the ESD conduction period has expired to prevent damage to the clamp device under certain circumstances. What is also needed is a circuit that can detect when a severe electrical stress event affects the ESD clamp transistor and can assert the clamp device to prevent damage to the ESD clamp device. What is also desired is an ESD circuit that can effectively implement these features over a wide operating temperature range.

[0056] Figure 5 is a circuit diagram of an ESD circuit according to one embodiment of the present invention. ESD circuit 501 is located in a semiconductor die and is used to protect other circuit systems (not shown) of the die during an ESD event that affects VDD power rail 517, which is a power rail leading to another circuit system. The ESD event affecting rail 517 may occur due to an ESD event at the die pad or package pad (not shown) that supplies rail 517. Examples of other circuit systems that may be located in a semiconductor die protected by ESD circuit 501 include digital, analog, and mixed-signal circuit systems, memory, processing circuit systems, communication circuit systems, and sensors, but other types of circuit systems may also be protected. In addition, the die may include multiple circuits similar to circuit 501 located on rails 517 distributed throughout the die. Furthermore, the die may include multiple ESD circuits similar to circuit 501 for each power supply voltage rail.

[0057] ESD circuit 501 includes a trigger circuit 503 that detects an ESD event affecting rail 517 and asserts a trigger signal (TRIGGER) to cause an ESD clamp to conduct to discharge the ESD current from the ESD event. In the illustrated embodiment, the ESD clamp is implemented using a single NFET 505 having a drain connected to the VDD supply voltage rail 517 and a source connected to the VSS supply voltage rail 519. However, other embodiments may include other types of ESD clamps that become conductive in response to a trigger signal. Other types of ESD clamps may include a PFET, another type of transistor (e.g., a bipolar transistor), or multiple transistors connected in series between the VDD rail 517 and the VSS rail 519. In some embodiments, the clamp may be implemented using a thyristor, where at least one of the N-well or P-well is driven by the TRIGGER signal. In some embodiments, the trigger circuit output may be connected to a trigger circuit bus that triggers multiple ESD clamps connected to rail 517. In one embodiment, the VSS supply voltage rail 519 is at ground, but may be at another voltage (eg, a negative voltage) in another embodiment. During normal operation, the control terminal of the ESD clamp device is biased non-conductive.

[0058] Trigger circuit 503 is characterized as an RC trigger circuit and operates in a similar manner to trigger circuit 103. The circuit includes resistor 509 and capacitor 507, where the on-time period of circuit 503 is based on the RC constant of resistor 509 and capacitor 507. Trigger circuit 503 also includes NFET 505 and resistor 513. The source of PFET 511 is connected to rail 517, and the drain of PFET 511 provides the TRIGGER signal. In some embodiments, trigger circuit 503 is coupled to a separate boosted bus (not shown), which is itself coupled to rail 517 through other means. In such embodiments, the trigger circuit senses the condition of the boosted bus to determine the presence of an ESD event affecting rail 517. Trigger circuits of other embodiments may have other configurations, other circuitry, and / or operate in other manners (e.g., similar to trigger circuits 203 and 303). For example, the trigger signal may be a current signal where the clamping transistor comprises a bipolar transistor.

[0059] In the embodiment shown, the ESD clamp transistor NFET 505 includes two sets of one or more body contacts. A first set of one or more body contacts 525 is connected to the VSS rail 119. A second set of body contacts 525 is connected to the input of the clamp activation circuit 531. The two sets 523 and 525 are located in different areas of the body region of the transistor 505 such that an internal resistance 521 exists between the two sets in the body region. See, for example, Figure 11 and the following discussion.

[0060] As explained above, for electrical stress events of sufficient severity (intensity / duration), impact ionization may occur in the ESD clamp device (transistor 505) that may permanently damage the clamp device. Therefore, the ESD circuit 501 includes a clamp activation circuit 531 having an input connected to the body contact set 523. Based on the condition of the set 523 indicating a sufficiently severe electrical stress event, the circuit 531 activates the clamp devices coupled to both rails 517 and 519 to transfer the charge of the electrical stress event between the rails in order to reduce the possibility of damaging the NFET 505 (and other circuitry). In some embodiments, the circuit 531 activates a separate clamp device 533 to transfer the electrical stress charge (see Figure 6 、 8 and 9). In other embodiments, clamp activation circuit 531 includes an output 541 connected to the input of NFET 505 for asserting a signal to cause NFET 505 to conduct, thereby delivering the electrical stress charge (see Figure 10 embodiment).

[0061] In embodiments where the ESD clamp device includes multiple clamp transistors connected in series, a clamp activation circuit may be connected to the body contact set of one of the multiple clamp transistors in the series, or a separate clamp activation circuit may be connected to each of the multiple clamp transistors in the series. For example, in some embodiments where the clamp transistors share a common body region and the transistor gates are very close to each other so that the two clamp transistors have a shared bipolar mode, one activation circuit is connected to the body contact set of one clamp transistor (or to the common body contact set of both clamp transistors) in the region where impact ionization is most likely to occur. In some embodiments where the body regions of each clamp transistor are isolated from each other or the body regions of each clamp transistor are physically separated from each other by a sufficient substrate distance so that they have separate bipolar modes, a separate clamp activation circuit will be connected to the body contact set of each clamp transistor.

[0062] Figure 6 FIG. 5 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention. Figure 5 5. The RC trigger circuit 503 shown in FIG. 5 is similar to the trigger circuit 503 shown in FIG. 5, where items with the same reference numbers are similar. However, other types of trigger circuits may be used in other embodiments. In the embodiment shown, the ESD clamp device is implemented using a single NFET 505, but other types of clamp devices may be used in other embodiments.

[0063] The clamp activation circuit of circuit 601 is implemented with NFET 605, which has its drain and gate connected to body contact set 523 and its source and body region connected to VSS rail 519. The clamping device is implemented with NFET 607, which has its drain connected to rail 517, its gate connected to the gate of NFET 605, and its drain and body region connected to VSS rail 519.

[0064] NFET 605 and NFET 607 are arranged in a current mirror configuration (current mirror 603), where NFET 605 is a set transistor and NFET 607 is a mirror transistor. In one embodiment, the threshold voltages of NFETs 605 and 607 are 0.6 volts or less. During a stress event in which impact ionization occurs in clamp transistor 505, an ionization current flows from body contact set 523 through NFET 605 to set the voltage at the gate of NFET 607, which controls the amount of stress current released from rail 517 to rail 519. In one embodiment, NFET 607 is significantly larger (e.g., 2-100 times) than NFET 605, so that the discharge current through NFET 607 is proportionally greater than the ionization current through NFET 605. Therefore, clamp NFET 607 is conductive only when impact ionization occurs in clamp transistor 505.

[0065] Figure 7 The ESD clamp transistor (NFET 505) is Figure 4 Graphs of current and voltage during an electrical stress event similar to the one described, where a supply voltage is suddenly applied to the VDD pad (not shown) of the semiconductor die via a cable (not shown) containing a relatively large amount of inductance, and the electrical stress event is severe enough to cause impact ionization in NFET 505. At the end of the on-time of trigger circuit 503, the current through NFET 505 begins to decrease to a point t where NFET 505 turns off. OFF However, as mentioned above with respect to Figure 4 As depicted, the inductance of the power cable continues to feed current, with the voltage of rail 517 spiking (see spike 701 ) to cause impact ionization in NFET 505 .

[0066] Because current mirror 603 conducts current in response to impact ionization current from body contact set 523, after the on-time of NFET 505 elapses, the electrical stress charge from VDD supply rail 517 is transferred across NFET 607 to rail 519 to reduce the power consumption compared to the NFET 505. Figure 4The voltage spike 401 is reduced by the voltage spike 701. Thus, by utilizing the clamp activation circuit and clamping device (implemented as current mirror 603) of circuit 601, NFET 505 can be protected from impact ionization damage from electrical stress events that are more severe than typical ESD events.

[0067] Figure 8 FIG. 5 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention. Figure 5 5. The RC trigger circuit 503 shown in FIG. 5 is similar to the trigger circuit 503 shown in FIG. 5, where items with the same reference numbers are similar. However, other types of trigger circuits may be used in other embodiments. In the embodiment shown, the ESD clamp device is implemented using a single NFET 505, but other types of clamp devices may be used in other embodiments.

[0068] The clamp activation circuit of ESD circuit 801 is implemented using signal line 805, and the clamping device is implemented using NFET 803. One end of signal line 805 is connected to body contact set 523, and the other end is connected to the gate of NFET 803. NFET 803 includes a drain connected to VDD supply voltage rail 517 and a source and body region connected to VSS supply voltage rail 519. In some embodiments, the threshold voltage of NFET 803 is 0.6 volts or less.

[0069] During impact ionization in NFET 505, an ionization current originates from the drain of NFET 505, flows through the body region of NFET 505, flows through the body contact set 525, and reaches the VSS supply voltage rail 519. Due to the resistance 521 between the body contact set 523 in the body region and the body contact set 525, a voltage difference is generated between the body contact set 523 and the VSS supply voltage rail 519 during impact ionization. When the voltage difference exceeds the threshold voltage of NFET 803, NFET 803 conducts to discharge the electrical stress current from the VDD rail 517. The lower threshold voltage of NFET 803 allows the clamping device to turn on faster and remain on longer during impact ionization. Figure 8 In the embodiment, the clamp activation circuit has a simpler design.

[0070] Figure 9 FIG. 5 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention. Figure 5 5. The RC trigger circuit 503 shown in FIG. 5 is similar to the trigger circuit 503 shown in FIG. 5, where items with the same reference numbers are similar. However, other types of trigger circuits may be used in other embodiments. In the embodiment shown, the ESD clamp device is implemented using a single NFET 505, but other types of clamp devices may be used in other embodiments.

[0071] The clamp activation circuit of circuit 901 is implemented using two inverters (905 and 907) coupled in series in a series signal path. Inverter 905 includes an NFET 913 having a gate connected to body contact set 523, a drain connected to resistor 911, and a source and body region connected to VSS rail 519. Resistor 911 is connected to VDD rail 517. The drain of NFET 913 is connected to the input of inverter 907, which is connected to the gates of PFET 915 and NFET 917. The source and body region of PFET 915 are connected to rail 517, and the drain is connected to the drain of NFET 917 at the output of inverter 907. The source and body region of NFET 917 are connected to rail 519.

[0072] The clamping device of circuit 901 is implemented with an NFET 903 having a drain connected to the VSS rail 517, a gate connected to the drains of PFET 915 and NFET 917, and a drain and body region connected to the VSS rail 519. However, other types of clamping devices (e.g., a PFET, multiple transistors in series) may be used in other embodiments.

[0073] During a severe electrical stress event that causes impact ionization in clamp transistor 505, the voltage difference between the voltage of body contact set 523 and the voltage of rail 519 rises above the threshold voltage of NFET 913 (e.g., 0.6 volts or less), causing NFET 913 to conduct, thereby pulling the input node of inverter 907 to the voltage of VSS. In response, the output of inverter 907 rises above the threshold voltage of NFET 903, causing NFET 903 to conduct, thereby discharging the electrical stress current from rail 517 to rail 519. Once the impact ionization current decays to the point where the voltage difference between body contact set 523 and VSS rail 519 is below the threshold voltage of NFET 913, NFET 903 stops conducting.

[0074] In other embodiments, the clamp activation circuit includes a different number of inverters connected in series (e.g., one, three, or more). Furthermore, in other embodiments, the inverters may have other configurations. For example, inverter 905 may include a PFET in place of resistor 911, and inverter 907 may include a resistor in place of NFET 917.

[0075] For the activation clamp circuit a series of inverters is used instead of Figure 8One advantage of using only one signal line 805 in embodiments of the present invention is that a clamping transistor (NFET 903) having a higher threshold voltage can be used. Additionally, an inverter can be used to increase the drive strength of the asserted signal provided to the gate of the clamping transistor (NFET 903). Furthermore, in some embodiments, if an odd number of inverters is used, a PFET can be used as the clamping device.

[0076] Figure 10 FIG. 5 is a more detailed circuit diagram of an ESD circuit according to an embodiment of the present invention. Figure 5 5. The RC trigger circuit 503 shown in FIG. 5 is similar to the trigger circuit 503 shown in FIG. 5, where items with the same reference numbers are similar. However, other types of trigger circuits may be used in other embodiments. In the embodiment shown, the ESD clamp device is implemented using a single NFET 505, but other types of clamp devices may be used in other embodiments.

[0077] The clamp activation circuit of circuit 1001 is implemented using inverter 1003 and a latching transistor (PFET 1009). In the illustrated embodiment, inverter 1003 includes resistor 1005 and NFET 1007, which has a gate connected to body contact set 523, a drain connected to resistor 1005 and the gate of PFET 1009, and a source and body region connected to VSS rail 519. The voltage difference between rails 317 and 319 that causes assertion of the TRIGGER signal of circuit 303 depends on the cumulative threshold voltage of diode string 309 and the threshold voltage of PFET 311. Resistor 1005 is connected to VDD rail 517. In some embodiments, the threshold voltage of NFET 1007 is 0.6 volts or less.

[0078] The source and body regions of PFET 1009 are connected to the VDD rail 517. The drain of PFET 1009 is connected to the gate of ESD clamp transistor 505. If, during an electrical stress event when impact ionization occurs in clamp transistor 505, where the voltage difference between body contact set 523 and VSS rail 519 exceeds the threshold voltage of NFET 1007, NFET 1007 pulls the voltage of the gate of PFET 1009 toward the voltage of VSS, which causes PFET 1009 to conduct, biasing the gate of clamp transistor 505 in a conductive state to continue to discharge the electrical stress current. Thus, in the scenario described above, where the inductive power cable continues to supply current to VDD rail 517 after trigger circuit 503 has timed out and impact ionization occurs in transistor 505, PFET 1009 will become conductive to turn transistor 505 back on, thereby discharging the electrical stress current and alleviating the ionization condition in transistor 505.

[0079] One advantage of the configuration of circuit 1001 is that no additional clamping device is required because the ESD clamping device (transistor 505) is used to dissipate the charge.

[0080] Figure 11 is a partial top view of a substrate 1101 including a semiconductor die and an ESD circuit according to one embodiment. Figure 11 Not shown, but located on top of substrate 1101, are gate structures, interconnect layers, and die terminals (e.g., bond pads, bond studs, etc.). Substrate 1101 comprises a semiconductor material (e.g., silicon, silicon germanium, gallium nitride) in which semiconductor devices (e.g., transistors, diodes) are formed from regions doped with conductive dopants.

[0081] Figure 11 An embodiment of a segment of an ESD clamp transistor (e.g., transistor 505) is shown. Segment 1103 is located in a well of P-type conductivity dopants forming the transistor's body region 1104. Located within the well's active region 1116 are elongated N-type regions (doped with N-type dopants) that alternately serve as source regions (designated "S") (e.g., source region 1107) and drain regions (designated "D") (e.g., drain region 1109). The elongated doped regions are separated by portions of the body region 1104. An elongated gate structure (not shown) is located above the body region 1104, between the source region (S) and the drain region (D).

[0082] Figure 11 Several contact locations are shown (in Figure 11 11 (represented as squares in FIG. 11 ), wherein contacts are made to the doped substrate region to connect the substrate region to other circuitry via interconnect structures (not shown) in the interconnect region. For example, source region 1107 includes three contact locations (1111) and drain region 1109 includes three contact locations (1113). Contacts for each source region of segment 1103 (e.g., at location 1111) are electrically connected together and to VSS rail 519 (which is located in the interconnect layer). Contacts for each drain region of segment 1103 (e.g., at contact location 1113) are electrically connected together and to VDD rail 517 (which is located in the interconnect layer). Elongated gate structures (not shown) are electrically connected together and to a signal line that provides a TRIGGER signal to the gate of clamp transistor 505. In some embodiments, P-type body region 1104 is isolated from the underlying P-type doped substrate by a buried N-type layer (not shown) or a buried dielectric layer (not shown).

[0083] Figure 11The locations of two sets of body contacts for body region 1104 are shown. Body contact set 525 is located around the perimeter of body region 1104 (e.g., at contact location 1115). Body contact set 523 is located in central portion 1118 of region 1116. Each set of body contact locations is surrounded by an isolation structure (1114, 1121) that isolates the formed body contact from adjacent semiconductor material. For example, dielectric structure 1211 isolates body region 1104 at the surface of substrate 1101 at contact location 1119 from oppositely doped source region 1129.

[0084] In the illustrated embodiment, center portion 1118 is the geometric center portion of area 1116. In one embodiment, all of the second set of body contacts are located within 1% of the geometric center portion of area 1116. In other embodiments, all of the second set of body contacts are located within 10% of the geometric center portion of area 1116. In still other embodiments, all of the second set of body contacts are located within 20% of the geometric center portion of area 1116.

[0085] In some embodiments, during an electrical stress event, impact ionization first occurs in the geometric center of the bulk region of the active region of a transistor segment. Therefore, positioning the second set 523 of body contacts in the geometric center region enables the body contacts to provide an early indication of impact ionization. Thus, the clamping device can be activated before damage to the clamped transistor occurs.

[0086] exist Figure 11 1 , the body contacts in the body contact group 525 (e.g., contact location 1115) are located on the periphery of the body region 1104 outside of the active region 1116. Thus, there is lateral spacing in the body region between the body contacts in group 523 and the body contacts in group 525. Providing spacing between the body contacts in group 525 connected to the power rails (e.g., VSS for NFET clamp transistors and VDD for PFET clamp transistors) and the body contacts in group 523 connected to the clamp activation circuit 531 can provide resistance 521 between the body contact group 525 and the body contact group 523 in the body contact region. Such resistance can allow for Figure 5-10 The ionization current between the body contact set 523 in and the power rail (VSS rail 519 ) creates a voltage difference that provides an indication of the severity of the electrical stress event and that impact ionization is occurring in transistor 505 .

[0087] Located within the body region 1104 is a region 1106 having a lower net concentration of the same type of conductive dopant than the remainder of the body region 1104. In the embodiment shown, region 1106 is implemented as a square ring surrounding the active region 1116 and located between the inner set of body contacts (e.g., at contact location 1119) and the outer set of body contacts (e.g., at contact location 1115). The lower net conductivity type doped region 1106 between the two sets of body contacts can contribute to the resistance 521 between the body contact set 525 and the body contact set 523. The amount of resistance provided by region 1106 depends on the net dopant concentration difference between region 1106 and the remainder of the body region 1104 and the lateral width of region 1106. In one embodiment, the net P-type doping concentration of region 1106 is 10-100 times less than the net P-type doping concentration of the remainder of region 1104. In one example, resistance 521 may be in the range of 50-100 ohms, but may have other values ​​in other embodiments. However, in other embodiments, the regions may have different net concentration differences.

[0088] In one embodiment, the doping concentration of region 1106 is the epitaxial layer of substrate 1101 (whose top surface is at Figure 11 1104). During wafer processing, region 1106 is masked during the implantation of additional P-type dopant into region 1104. However, in other embodiments, region 1106 may be formed differently. For example, region 1106 may be formed by relatively lightly counter-doping N-type dopants into body region 1104, wherein the net P-type doping concentration is lower than the net P-type doping concentration of the remainder of body contact region 1104. In some embodiments, the body contacts in the outer set of body contacts (e.g., at contact location 1115) will be located in, or at least partially located in, a region of the body region having a lower net conductive dopant concentration than the inner set of body contacts (e.g., at contact location 1119). In still other embodiments, the clamp transistor will not include a region of lower net doping concentration (e.g., like region 1106).

[0089] In other embodiments, the body contacts of the two groups 523 and 525 will be intermixed in section 1603. Also, the number of contacts of each group in a section may be different from Figure 11 . For example, each group may include only one body contact. In one embodiment, the body contact group 525 will include a ring-shaped body contact surrounding the active region 116. In still other embodiments, the clamp transistor may include multiple sections, wherein similar regions and structures in each section are electrically connected to each other to provide a 5-terminal device (source, drain, gate, first body contact, and second body contact).

[0090] As described herein, providing a clamp activation circuit having two sets of at least one body contact and an output for asserting a signal to cause the clamp device to conduct in response to a sufficiently severe electrical stress event, as indicated by the condition of one or more of the body contacts, can provide a system that prevents damage to an ESD clamp transistor due to impact ionization from an electrical stress event. Furthermore, such a mechanism can operate effectively over a relatively wide temperature range.

[0091] As disclosed herein, a structure or region is "directly between" two structures or regions on a line if the two structures or regions are on opposite sides of the other two structures or regions on a line. Figure 11 In Figure 1, region 1109 is located horizontally between region 1107 and region 1129. A first structure or region is "directly transverse" to a second structure or region if the first and second structures or regions lie on a line parallel to the main side of the generally planar surface of the substrate. For example, region 1107 and region 1109 are directly transverse to each other. A first structure or region directly surrounds a second structure or region if the first structure or region surrounds the second structure or region on a line parallel to the main side of the generally planar surface of the substrate. A vertical line is a line perpendicular to the main side of the generally planar surface of the substrate.

[0092] The gate is the control terminal of the FET. The source and drain are the current terminals of the FET.

[0093] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and, therefore, it is intended that the appended claims cover within their scope all such changes and modifications that come within the true spirit and scope of this invention.

Claims

1. A circuit, characterized in that: include: An ESD clamping device includes a clamping transistor, wherein the clamping transistor includes: a first current terminal coupled to a first power supply voltage rail; a second current terminal coupled to a second supply voltage rail, wherein when becoming conductive, the clamp transistor conducts to transfer charge between the first supply voltage rail and the second supply voltage rail, wherein during normal operation, the clamp transistor is biased in a non-conductive state; a first set of one or more body contacts coupled to one of the first supply voltage rail or the second supply voltage rail; a second set of one or more body contacts; an electrostatic discharge (ESD) trigger circuit configured to detect an ESD event affecting the first power supply voltage rail, the ESD trigger circuit asserting an output signal to render the clamp transistor conductive in response to detecting the ESD event; a clamp activation circuit including an input coupled to the second set of one or more body contacts and including an output coupled to a control terminal of a clamp device, the clamp device including a first current terminal coupled to the first supply voltage rail and a second current terminal coupled to the second supply voltage rail, wherein during a sufficiently severe electrical stress event as indicated by a condition of the second set of one or more body contacts, the clamp activation circuit causes the clamp device to conduct to transfer charge between the first supply voltage rail and the second supply voltage rail.

2. The circuit according to claim 1, wherein: the clamp activation circuit comprising a set transistor including a control terminal coupled to the second set of one or more body contacts; the clamping device comprising a mirror transistor including a first current terminal coupled to the first supply voltage rail, a second current terminal coupled to the second supply voltage rail, and a control terminal coupled to the second set of one or more body contacts; Wherein the set transistor and the mirror transistor are configured in a current mirror configuration.

3. The circuit according to claim 2, characterized in that During a sufficiently severe electrical stress event in which impact ionization is generated in the clamp transistor, an impact ionization current flows from the second set of one or more body contacts through the first current terminal and the second current terminal of the set transistor to control the current through the mirror transistor from the first power supply voltage rail to the second power supply voltage rail for transferring charge from the first power supply voltage rail to the second power supply voltage rail.

4. The circuit according to claim 1, wherein: The clamping device is the clamping transistor.

5. The circuit according to claim 4, characterized in that The clamp activation circuit includes a latch transistor having a first current terminal coupled to one of the first supply voltage rail or the second supply voltage rail, and a second current transistor coupled to a control terminal of the clamp transistor.

6. The circuit according to claim 5, characterized in that During a sufficiently severe electrical stress event, for a condition in which the clamp transistor is in a conductive state in which charge is transferred between the first and second supply voltage rails, the latch transistor becomes conductive to pull the voltage of the control terminal of the clamp transistor to the voltage of the one of the first supply voltage rail or the second supply voltage rail.

7. The circuit according to claim 1, wherein: The clamping device includes a second clamping transistor including a first current terminal coupled to the first power supply voltage rail, a second current terminal coupled to the second power supply voltage rail, and a control terminal; The clamp activation circuit includes a signal line having one end coupled to the second set of one or more body contacts and a second end coupled to the control terminal of the second clamp transistor.

8. The circuit according to claim 1, wherein: The clamp activation circuit includes at least one inverter configured in a series signal path between the second set of one or more body contacts and a control terminal of the clamp device.

9. The circuit according to claim 8, characterized in that: The clamping device includes a second clamping transistor including a first current terminal coupled to the first power supply voltage rail, a second current terminal coupled to the second power supply voltage rail, and a control terminal; The clamp activation circuit includes two inverters, wherein an output of a second inverter in the series signal path is connected to the control terminal of the second clamp transistor.

10. A circuit, characterized in that: include: An ESD clamping transistor, the ESD clamping transistor comprising: a first current terminal coupled to a first power supply voltage rail; a second current terminal coupled to a second power supply voltage rail, wherein when becoming conductive, the ESD clamp transistor conducts to transfer charge between the first power supply voltage rail and the second power supply voltage rail, wherein during normal operation, the ESD clamp transistor is in a non-conductive state; a first set of one or more body contacts coupled to one of the first supply voltage rail or the second supply voltage rail; a second set of one or more body contacts; an electrostatic discharge (ESD) trigger circuit configured to detect an ESD event affecting the first power supply voltage rail, the ESD trigger circuit asserting an output signal to render the ESD clamp transistor conductive in response to detecting the ESD event; a clamp activation circuit including an input coupled to the second set of one or more body contacts and including an output coupled to a control terminal of a clamp device, the clamp device including a first current terminal coupled to the first supply voltage rail and a second current terminal coupled to the second supply voltage rail, wherein during a sufficiently severe electrical stress event in which impact ionization is generated in the ESD clamp transistor as indicated by the presence of the second set of one or more body contacts, the clamp activation circuit causes the clamp device to conduct to transfer charge between the first supply voltage rail and the second supply voltage rail.

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