Method and device for identifying second-class short circuit state of insulated gate bipolar transistor

Abstract

The invention provides a method and a device for identifying a second-class short circuit state of an insulated gate bipolar transistor (IGBT), and relates to the technical field of IGBT devices. The invention aims to timely and accurately judge whether the insulated gate bipolar transistor is in the second-class short circuit state or not. The method comprises the following steps: acquiring an emitter structure of an insulated gate bipolar transistor in a test circuit; if the emitter structure does not have the auxiliary emitter, acquiring a chip gate voltage, a gate side line parasitic inductance, a gate parasitic inductance, an emitter side line parasitic inductance, a common emitter parasitic inductance, a gate current, a collector current and a current from a gate to a collector in a gate driving loop; on the basis of the Kirchhoff's voltage law, grid voltage is determined through the collected parameter data; and if the grid voltage is within the preset short-circuit voltage range, determining that the insulated gate bipolar transistor has a second-class short circuit.

Description

Technical Field

[0001] The present application relates to the field of IGBT devices, and in particular to a method and device for identifying a type II short-circuit state of an insulated gate bipolar transistor. Background Art

[0002] In flexible direct current transmission scenarios, insulated gate bipolar transistors (IGBTs) are usually used as core switching devices to undertake the key tasks of power conversion and control.

[0003] Currently, to ensure normal circuit operation, desaturation detection is used to determine whether a Class II short circuit has occurred in an IGBT device. A Class II short circuit occurs when the upper-side IGBT or freewheeling diode (FWD) breaks down while the lower-side IGBT is in the on-state. This detection method monitors the voltage between the collector and emitter of the IGBT and determines whether the voltage jumps from the low voltage during "saturated on" to an abnormally high voltage to confirm whether a short circuit has occurred. However, during the IGBT's on-state, the parasitic inductance within the circuit generates an induced voltage due to the rapid rise in current, causing the collector and emitter voltages to increase. This characteristic means that desaturation detection based on voltage monitoring must wait until the IGBT is fully turned on before effective measurement can be performed, making it impossible to promptly capture the occurrence of a Class II short circuit during the IGBT's on-state.

[0004] Therefore, a new method is urgently needed to promptly determine whether an IGBT short circuit occurs. Summary of the Invention

[0005] The embodiments of the present application provide a method and device for identifying a type II short-circuit state of an insulated gate bipolar transistor, the purpose of which is to promptly and accurately determine whether the insulated gate bipolar transistor is in a type II short-circuit state.

[0006] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, the present application provides a method for identifying a type II short-circuit state of an insulated gate bipolar transistor, the method comprising:

[0008] obtaining an emitter structure of an insulated gate bipolar transistor in a test circuit;

[0009] If the emitter structure does not have an auxiliary emitter, then obtain the chip gate voltage, gate side line parasitic inductance, gate parasitic inductance, emitter side line parasitic inductance, common emitter parasitic inductance, gate current, collector current, and gate-to-collector current in the gate drive loop, where the common emitter parasitic inductance is the common parasitic inductance of the gate drive loop and the collector-emitter loop;

[0010] Based on Kirchhoff's voltage law, the gate voltage is determined using the chip gate voltage, gate-side line parasitic inductance, gate parasitic inductance, emitter-side line parasitic inductance, common-emitter parasitic inductance, gate current, collector current in the main loop, and gate-to-collector current in the gate drive circuit;

[0011] If the gate voltage is within the preset short-circuit voltage range, it is determined that a second type short circuit occurs in the insulated gate bipolar transistor.

[0012] In a second aspect, the present application provides a device for identifying a type II short-circuit state of an insulated gate bipolar transistor, the device comprising:

[0013] an acquiring unit, configured to acquire an emitter structure of an insulated gate bipolar transistor in a test circuit;

[0014] The acquisition unit is configured to acquire the chip gate voltage, gate parasitic inductance, common emitter parasitic inductance in the gate drive loop, and collector current in the main loop if the emitter structure does not have an auxiliary emitter, wherein the common emitter parasitic inductance is the common parasitic inductance of the gate drive loop and the collector-emitter loop;

[0015] a voltage determination unit, configured to determine a gate voltage based on Kirchhoff's voltage law and utilizing the chip gate voltage, the gate parasitic inductance, the common emitter parasitic inductance, and the collector current in the gate drive loop of the acquisition unit;

[0016] The judging unit is configured to determine that a second type of short circuit occurs in the insulated gate bipolar transistor if the gate voltage of the voltage determining unit is within a preset short circuit voltage range.

[0017] In a third aspect, the present application also provides a computing device, comprising: at least one processor, and a memory, wherein the memory stores instructions that can be executed by the processor, and the instructions are executed by the processor, so that the processor can execute the above-mentioned method for identifying the second type of short-circuit state of the insulated gate bipolar transistor.

[0018] In a fourth aspect, the present application also provides a readable storage medium, which is used to store a computer program, wherein when the computer program is running, it controls the device where the storage medium is located to execute the above-mentioned method for identifying the second type of short-circuit state of the insulated gate bipolar transistor.

[0019] Compared to the prior art, the present application provides a method and device for identifying a Class II short-circuit state of an insulated gate bipolar transistor. The method obtains the IGBT emitter structure and, in the absence of an auxiliary emitter, comprehensively obtains the chip gate voltage, various parasitic inductances, gate current, collector current, and gate-to-collector current in the gate drive circuit. Using Kirchhoff's voltage law, the collected data is combined to determine the gate voltage, and whether the IGBT is in a Class II short circuit is determined based on whether the gate voltage is within a preset short-circuit voltage range. This method breaks the limitation of relying on collector and emitter voltages to determine a short circuit. By comprehensively analyzing the multi-dimensional parameters of the gate drive circuit, when the gate voltage falls within the preset short-circuit voltage range, it can promptly determine that a short circuit has occurred, achieving real-time monitoring of Class II short circuits during the IGBT conduction process, greatly improving the timeliness of fault diagnosis, and providing strong support for the safe and stable operation of flexible direct current transmission systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the exemplary embodiments of the present application will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0021] Figure 1 A flow chart of a method for identifying a type II short-circuit state of an insulated gate bipolar transistor is schematically shown;

[0022] FIG2( a ) schematically shows a structure of an insulated gate bipolar transistor with an auxiliary emission electrode;

[0023] FIG2( b ) schematically shows a structure of an insulated gate bipolar transistor without an auxiliary emission electrode;

[0024] FIG3( a ) schematically shows a test circuit structure diagram of an insulated gate bipolar transistor without an auxiliary emission electrode;

[0025] FIG3( b ) schematically shows a test circuit structure diagram of an insulated gate bipolar transistor with an auxiliary emission electrode;

[0026] Figure 4 A flow chart schematically illustrates another method for identifying a type II short-circuit state of an insulated gate bipolar transistor;

[0027] Figure 5 A flow chart schematically illustrates a method for identifying the second type of short-circuit state of other insulated gate bipolar transistors;

[0028] Figure 6 Schematically shows a data change diagram of an IGBT normal turn-on process and a type II short-circuit process;

[0029] Figure 7 The structure of a device for identifying the second type of short-circuit state of an insulated gate bipolar transistor is schematically shown;

[0030] Figure 8 The structure of another device for identifying the second type of short-circuit state of an insulated gate bipolar transistor is schematically shown. DETAILED DESCRIPTION

[0031] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0032] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which this application belongs.

[0033] In existing technologies, flexible DC transmission systems generally use insulated gate bipolar transistors (IGBTs) as their core switching devices. Traditional desaturation detection methods monitor collector-emitter voltage changes to detect short-circuit faults. However, the induced voltage generated by parasitic inductance during device conduction can cause an abnormal voltage increase, which can be misinterpreted as a short-circuit fault and cause the protection system to malfunction. For example, under high-voltage and high-current operating conditions, when the current rise rate exceeds 5000A / μs, the voltage spikes generated by the line's parasitic inductance can reach tens of volts, completely masking the actual short-circuit signal.

[0034] In order to solve the above problems, researchers found that there is an essential difference between the voltage change caused by parasitic inductance and the actual short-circuit state. By analyzing the coupling relationship between the gate drive circuit and the main circuit, it was found that the dynamic characteristics of the gate voltage can reflect the nature of the current change. The research team proposed to apply Kirchhoff's voltage law to the drive circuit modeling, and to establish a gate voltage calculation model by quantifying the interaction between parasitic inductance and current change rate. This idea breaks through the traditional limitation of focusing only on the collector-emitter voltage, and instead captures the short-circuit characteristics from the changes in the internal parameters of the drive circuit to accurately determine the occurrence of a Class II short-circuit state in the IGBT. Figure 1 As shown, the details are as follows:

[0035] Step 101: Obtain an emitter structure of an insulated gate bipolar transistor in a test circuit.

[0036] Before formally introducing this application, the embodiments of this application also introduce IGBT, Insulated Gate Bipolar Transistor (IGBT): It is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and a metal oxide semiconductor field effect transistor (MOSFET), and has the advantages of both the high input impedance of MOSFET and the low on-state voltage drop of BJT. IGBT has three main terminals: collector (C), emitter (E), and gate (G), among which there is an IGBT with an auxiliary emitter (E'), as shown in Figure 2 (a) and an IGBT designed without an auxiliary method, as shown in Figure 2 (b). Among them, the IGBT without an auxiliary emitter includes: collector parasitic inductance L s,C 、IGBT chip gate-emitter capacitance C GE 、IGBT chip collector-emitter capacitance C CE , IGBT device gate-collector capacitance C GC , common emitter parasitic inductance L s,E1 , parasitic inductance L between the auxiliary emitter and the device emitter s,E3 , gate parasitic inductance L s,G1 If the IGBT does not have an auxiliary emitter, the internal structure of the IGBT is shown in Figure 2(b), which includes: collector parasitic inductance L s,C 、IGBT chip gate-emitter capacitance C GE 、IGBT chip collector-emitter capacitance C CE , IGBT device gate-collector capacitance C GC , common emitter parasitic inductance L s,E1 , gate parasitic inductance L s,G1 wait.

[0037] In this embodiment, the test circuit for the insulated gate bipolar transistor (IGBT) includes: a FEW (freewheeling diode), an IGBT, a main circuit, and a drive circuit. The main circuit includes DC bus capacitance, freewheeling circuit parasitic inductance (but not FWD package parasitic inductance), and power circuit parasitic inductance excluding IGBT and FWD device parasitic inductance and freewheeling circuit parasitic inductance. The drive circuit includes a drive switch, emitter-side line parasitic inductance, turn-off drive resistor, gate-side line parasitic inductance, turn-on drive resistor, and a drive power supply. Furthermore, during the IGBT measurement process, combining the desaturation detection principle and the influence of parasitic inductance, its operating state can be divided into the following four key stages. The voltage characteristics, influencing factors, and detection feasibility of each stage are as follows: Off-state (initial state): The IGBT is not conducting, no desaturation detection is required, and the circuit is in a normal off-state. Turn-on process: The dynamic process of the IGBT transitioning from the off-state (cut-off) to the saturated on-state. This is the stage when carriers within the IGBT begin to inject and form a conductive channel after a positive drive voltage is applied to the gate. On-saturation stage: After the IGBT is fully turned on, it enters the saturation region, and the collector-emitter voltage drops to the saturation voltage drop. Type II short-circuit fault stage: When a Type II short-circuit occurs: When the lower arm is turned on, the upper arm IGBT or freewheeling diode breaks down, the equivalent impedance between the collector and emitter drops sharply, the current runs out of control, and the collector-emitter voltage jumps sharply from the saturation voltage drop to an abnormally high voltage.

[0038] In this step, the purpose of obtaining the emitter structure of the insulated gate bipolar transistor is to determine whether the IGBT has an auxiliary emitter. There are three specific methods for obtaining the structure. One method is to check whether the IGBT has an auxiliary emitter based on the IGBT model, that is, to consult the IGBT device manual or circuit design drawings to confirm the emitter pin definition (such as whether the auxiliary emitter is marked). For example, welded IGBT modules usually have auxiliary emitters, while TO-packaged or press-fit packaged IGBTs do not have this structure. You can also use a microscope to observe the IGBT chip packaging structure. If there are additional pins independent of the main emitter E, it is determined that "an auxiliary emitter exists"; if there is only a single emitter pin, it is determined that "an auxiliary emitter does not exist." You can also judge by the drive circuit wiring. If there is a terminal on the emitter side that is independently connected to the drive circuit, it is an auxiliary emitter structure. The drive circuit is mainly used to control the opening and closing of the IGBT in the IGBT (insulated gate bipolar transistor) system, and is a key circuit part to ensure the normal operation of the IGBT.

[0039] Step 102: If the emitter structure does not have an auxiliary emitter, obtain the chip gate voltage, gate side line parasitic inductance, gate parasitic inductance, emitter side line parasitic inductance, common emitter parasitic inductance, gate current, collector current, and gate-to-collector current in the gate drive loop. The common emitter parasitic inductance is the common parasitic inductance of the gate drive loop and the collector-emitter loop.

[0040] In this step, the test circuit is as shown in Figure 3(a), the drive circuit is connected to the emitter E and gate G of the IGBT, where one end of the emitter E is connected to the emitter side line parasitic inductance L in the drive circuit. s,E2 , L s,E2 The other end is connected to the turn-on drive voltage U G,on , turn off the driving voltage U G,off One end is connected, which turns on the driving voltage U G,on The other end is connected to the turn-on drive resistor R G,on Connect and shut down the drive voltage U G,off The other end is connected to the off drive resistor R G,off Connect, open the drive resistor R G,on Or turn off the driving resistor R G,off The other end of the connection is connected to the parasitic inductance L of the gate side line through the switch s,G2 Connection to control the operation of the electric drive circuit, in addition, the parasitic inductance L of the gate side line s,G2 The other end is connected to the gate G. The circuit of the main loop is connected to the collector C and emitter E of the IGBT, wherein one end of the emitter E is connected to the DC bus capacitor c (c represents the capacitor symbol), the other end of the DC bus capacitor is connected to one end of the power loop parasitic inductance excluding the parasitic inductance of the IGBT and FWD devices and the parasitic inductance of the freewheeling loop, and the other end of the power loop parasitic inductance excluding the parasitic inductance of the IGBT and FWD devices and the parasitic inductance of the freewheeling loop is respectively connected to one end of the FWD device and one end of the load inductance, wherein the other end of the load inductance is connected to the collector C of the IGBT, the FWD device (parasitic inductance L inside the FWD device) S,F ) and the parasitic inductance L of the freewheeling circuit s,2 (L s,2 The FWD package parasitic inductance L is not included. S,F ), freewheeling circuit parasitic inductance L s,2 The other end is connected to the collector C of the IGBT. When the above circuit is running, there is a gate current i G 、i C is the IGBT collector current, i F is the FWD current and the IGBT chip collector-emitter capacitance side current i CE and the IGBT device gate-collector capacitance side current iGC The directions of the current flows are shown in the figure.

[0041] The meanings of the symbols in Figure 3(a) are as follows: (1) FWD device parameters: i F is the FWD current, u F Indicates FWD device voltage, u chip,F Indicates FWD chip voltage, L s,F Indicates the internal parasitic inductance of the FWD device, u s,F Indicates the voltage on the parasitic inductance inside the FWD device. (2) IGBT device parameters: C is the device collector, G is the device gate, E is the device emitter, i C is the IGBT collector current, u CE Indicates IGBT device voltage, u chip,CE Indicates IGBT chip voltage, C GE Indicates the gate-emitter capacitance of the IGBT chip, C GC Indicates the gate-collector capacitance (Miller capacitance) of the IGBT device, C CE Indicates the collector-emitter capacitance of the IGBT chip. L s,G1 represents the gate parasitic inductance, L s,C represents the collector parasitic inductance, L s,E1 represents the common emitter parasitic inductance, L s,E3 Represents the parasitic inductance between the auxiliary emitter and the device emitter. u s,G1 、u s,C 、u s,E1 Respectively represent the above parasitic inductance (L s,G1 , L s,C , L s,E1 ) voltage on the . (3) Main circuit parameters: c represents the DC bus capacitance, U DC Indicates the DC bus capacitor voltage (under no-load condition), L s,2 Indicates the parasitic inductance of the freewheeling circuit (but not including the parasitic inductance of the FWD package L s,F ), L s,1 It represents the parasitic inductance of the power circuit excluding the parasitic inductance of the IGBT and FWD devices and the parasitic inductance of the freewheeling circuit. (4) Drive circuit parameters: U G,on To turn on the driving voltage, U G,off is the turn-off driving voltage, R G,on To turn on the drive resistor, R G,off is the turn-off drive resistor, L s,G2 is the parasitic inductance of the gate side line, L s,E2 is the parasitic inductance of the emitter side line.

[0042] In this step, after receiving the signal indicating that the IGBT has transitioned from the off state to the on state, the relevant data in step 102 is obtained. The chip gate voltage can be acquired by directly connecting a differential voltage probe with a bandwidth ≥ 100 MHz to the gate and emitter pins of the IGBT chip. Since the internal voltage of the chip cannot be directly measured, in practical applications, it can be inferred by combining an equivalent circuit model with external measurements, or by using an IGBT module with a built-in sensor. The gate-side circuit parasitic inductance and gate parasitic inductance can be obtained by reading the gate loop parasitic inductance parameters from the IGBT drive circuit design document or the device datasheet. For customized circuits, the parasitic inductance of the gate circuit can be measured using a high-frequency impedance analyzer. The common emitter parasitic inductance is the parasitic inductance shared by the gate loop and the collector-emitter loop. It can be obtained through three-dimensional electromagnetic field simulation or actual loop impedance testing. The collector-emitter loop refers to the collector-side portion of the main loop. The parasitic inductance of the emitter-side circuit can be determined by measuring the high-frequency impedance of the emitter circuit of the drive circuit. The gate current and collector current can be measured in the gate circuit and collector main circuit respectively by high-frequency current sensors (such as Rogowski coil, Hall sensor). The current from gate to collector (Miller current) can be measured by Miller capacitor C CG Voltage change rate (du CE / dt) and capacitance value, i GC =C GC ×(du CE / dt), where u CE is the collector-emitter voltage (which can be measured by a voltage sensor).

[0043] Step 103: Based on Kirchhoff's voltage law, the gate voltage of the chip in the gate drive circuit, the parasitic inductance of the gate side line, the gate parasitic inductance, the emitter side line parasitic inductance, the common emitter parasitic inductance, the gate current, the collector current in the main circuit, and the gate-to-collector current are used to determine the gate voltage.

[0044] After acquiring various data from the test circuit during the IGBT conduction process in step 102, due to the presence of gate parasitic inductance, the gate voltage obtained by external measurement differs from the chip gate voltage. At this time, during the turn-on current rise process, the gate parasitic inductance is taken into account and the actual gate voltage can be determined according to Kirchhoff's voltage law. That is, when it is detected that the device is not equipped with an auxiliary emitter, the system synchronously collects the parasitic inductance parameters and current parameters in the drive circuit. By establishing a loop model including the gate-side line inductance, the gate body inductance, the emitter-side line inductance, and the common emitter inductance, and combining the gate current, collector current, and gate-collector current, the Kirchhoff voltage equation is constructed. The real-time collected chip gate voltage and various inductance parameters are substituted into the equation to calculate the actual gate voltage theoretical value.

[0045] Step 104 : If the gate voltage is within a preset short-circuit voltage range, it is determined that a type II short circuit occurs in the insulated gate bipolar transistor.

[0046] In this step, the preset short-circuit voltage range is a threshold interval established according to the physical characteristics of the device. For example, it can be determined by experimentally measuring the difference in gate voltage between normal conduction and short-circuit states, and the data range can also be determined by simulation. A type II short circuit usually refers to a short-circuit fault in an IGBT circuit, in which the upper arm IGBT or freewheeling diode (FWD) breaks down when the lower arm IGBT is in the on state. At this time, the lower arm IGBT is still in the on state, and the DC bus capacitor voltage will be fully applied to the parasitic inductance of the main circuit, causing the main circuit current to rise sharply.

[0047] After determining the gate voltage, the gate voltage is matched with a preset short-circuit voltage range. If the match is consistent, it is determined that a type II short circuit occurs in the insulated gate bipolar transistor. Otherwise, it is determined that a type II short circuit does not occur in the insulated gate bipolar transistor.

[0048] In summary, first, by obtaining the emitter structure, it is determined whether there is an auxiliary emitter, and the multi-dimensional parameters in the gate drive circuit are obtained in a targeted manner, including the chip gate voltage, various parasitic inductance parameters, gate current, collector current, etc. These parameters cover the key factors affecting the gate voltage and lay the foundation for subsequent accurate modeling. Then, based on Kirchhoff's voltage law, these parameters are integrated to determine the gate voltage. The application of this law ensures an accurate description of the voltage relationship in the circuit and can include the induced voltage generated by the parasitic inductance in the calculation, thereby eliminating its interference with the judgment result. Finally, by judging whether the gate voltage is within the preset short-circuit voltage range, it is determined whether the IGBT has a Class II short circuit. This method based on gate voltage avoids the transient interference caused by parasitic inductance in the collector and emitter compared to the traditional method that relies on collector-emitter voltage. In summary, this technical solution fundamentally eliminates the interference of parasitic inductance on the judgment process through the acquisition of multi-dimensional parameters, the application of Kirchhoff's voltage law and the transformation of the judgment basis, avoids misjudgment caused by transient increase of collector-emitter voltage, greatly improves the accuracy and timeliness of IGBT Class II short-circuit state judgment, ensures the reliability of IGBT operating status monitoring in scenarios such as flexible DC transmission, and is of great significance to improving the stability and safety of power electronic systems.

[0049] In order to explain the above embodiment in more detail, the embodiment of the present application also provides another method for identifying the second type of short circuit state of the insulated gate bipolar transistor. When the emitter structure does not have an auxiliary emitter, such as Figure 4 As shown, the embodiment of this application provides the following specific steps:

[0050] Step 401: Obtain relevant parameter data.

[0051] In this step, the relevant parameter data include at least: the chip gate voltage in the gate drive circuit, the parasitic inductance of the gate side line, the gate parasitic inductance, the parasitic inductance of the emitter side line, the common emitter parasitic inductance, the gate current, the collector current in the main circuit, and the current from the gate to the collector. Among them, the gate parasitic inductance refers to the inductance caused by the internal structure of the device in the gate drive circuit, which can be specifically achieved by device packaging parameter extraction or electromagnetic field simulation methods, and is used to characterize the impact of current changes in the gate circuit on the voltage. The parasitic inductance of the gate side line refers to the inductance generated by the connecting line in the gate drive circuit, which can be specifically obtained through measurement or simulation modeling, and is used to reflect the disturbance of the external line on the voltage. The common emitter parasitic inductance refers to the common inductance component that acts on the gate drive circuit and the collector-emitter main circuit at the same time, which can be specifically determined through loop impedance analysis or three-dimensional electromagnetic field calculation, and is used to describe the coupling effect of the main circuit current change on the gate voltage.

[0052] Step 402: Calculate the gate voltage based on the relevant parameter data.

[0053] During the IGBT's on-state, the parasitic inductance in the gate drive circuit generates an induced voltage due to rapid current changes. By establishing a voltage equation that incorporates the parasitic inductance of the gate-side circuit, the gate parasitic inductance, and the emitter-side circuit parasitic inductance, and by superimposing the coupling effect of the collector current changes in the main circuit on the common-emitter parasitic inductance, the actual gate voltage can be accurately calculated.

[0054] The specific calculation formula (1) is as follows:

[0055]

[0056] Among them, U in the above formula (1) GE Indicates the gate voltage, U chip,GE Indicates the chip gate voltage, L s,G1 represents the gate parasitic inductance, L s,G2 Indicates the parasitic inductance of the gate side line, L s,E2 Indicates the parasitic inductance of the emitter side line, L s,E1 represents the common emitter parasitic inductance, i GE represents the current from gate to collector, i C represents the collector current, i G represents the gate current, and t represents the time in seconds.

[0057] The above formula (1) is simplified based on the change rate of the gate current, the change rate of the collector current, and the change rate of the gate-to-collector current as shown in formula (2):

[0058]

[0059] It is worth noting that the process of simplifying formula (1) to formula (2) is as follows:

[0060] For high-power IGBT devices, the turn-on current rise process i C Rate of change (di C / dt) is in the order of thousands of amperes per microsecond (kA / μs). The gate reflux charging process is similar to a first-order circuit, with a large initial current. G The peak value can reach tens of amperes, but i C The rising process is already in the latter half of the gate charging process, i G The rate of change is about a few amperes per microsecond (A / μs). C Ascending process, there are:

[0061]

[0062] Considering that the parasitic inductance inside the IGBT device is in the range of a few nanohenries to tens of nanohenries, the parasitic inductance of the gate loop is within tens of nanohenries. Therefore, the parasitic inductance of the gate loop can be omitted. G / dt multiplication term, in addition i GE is i G The weight, di GE / dt can also be ignored. At this time, formula (1) can be approximated as formula (2):

[0063]

[0064] By sorting out the approximated formula, we can obtain the above formula (2).

[0065] 403. Determine whether a type II short circuit occurs in the insulated gate bipolar transistor based on the gate voltage.

[0066] After the gate voltage is determined according to the formula in step 402 , it is determined whether a type II short circuit occurs in the IGBT by comparing the gate voltage with a preset short circuit voltage range.

[0067] During the IGBT turn-on current rise process, the gate voltage u GE Collector current i C The following control relationships exist:

[0068]

[0069] Where n is the number of parallel IGBT chips, μ n is the electron mobility, α pnpis the transistor transport coefficient, w is the gate channel width, l is the gate channel length, and cox is the gate channel capacitance per unit area. At this point, the change in collector current can be used to determine whether the IGBT has a Class II short circuit. It is worth noting that, according to actual simulation results, the collector current rise rate of the IGBT in the normal on-state is approximately within 2kA / μs. If a Class II short circuit occurs in the IGBT, the collector current rise rate will increase several times. Furthermore, the preset short-circuit voltage can be determined based on the aforementioned control relationship, as follows:

[0070] The method comprises obtaining the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, PNP transistor magnification factor, and threshold voltage of the IGBT; determining a control relationship between the gate voltage and the collector current based on the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, PNP transistor magnification factor, and threshold voltage; obtaining a collector current expression based on the control relationship; calculating the rate of change of the collector current when the insulated gate bipolar transistor is operating normally based on the collector current expression; and determining the preset short-circuit voltage range based on the rate of change of the collector current, common-emitter parasitic inductance, chip gate voltage, and a preset rate of change multiple. The preset rate of change multiple is the ratio of the collector current rate of change when the IGBT experiences a Class II short circuit to the collector current rate of change when the IGBT is operating normally, and the ratio is set based on actual conditions.

[0071] Where: Collector current expression:

[0072]

[0073] For example, when the lower arm IGBT is in the on-state, the upper arm IGBT (or FWD) breaks down. After a type II short circuit occurs, the lower arm IGBT is still in the on-state saturation voltage drop (u CE ≈2~3V), DC capacitor voltage U DC All of them are applied to the parasitic inductance of the main circuit. The parasitic inductance of the main circuit is represented by Ls, which includes the parasitic inductance of power electronic devices, as well as the parasitic inductance of line copper bars and capacitors. The parasitic inductance of the main circuit is generally around 100nH. At this time, the main circuit current rise rate is:

[0074]

[0075] If according to U DC =2000V, Ls=100nH, di C / dt can reach 20kA / μs. The current rise rate in the normal open state is about within 2kA / μs. Therefore, in the second type short circuit state, diC / dt is about 10 times of the normal opening process. In this case, the preset change rate multiple can be 10.

[0076] In order to explain the above embodiment in more detail, the embodiment of the present application also provides another method for identifying the second type of short circuit state of the insulated gate bipolar transistor. When the emitter structure has an auxiliary emitter, such as Figure 5 As shown, the embodiment of this application provides the following specific steps:

[0077] Step 501: Obtain a first parasitic inductance and a rate of change of a collector current, where the first parasitic inductance is a parasitic inductance between an auxiliary emitter and an emitter of an insulated gate bipolar transistor.

[0078] In some specific embodiments, the parameters of the first parasitic inductance can be obtained by using a parasitic parameter extraction tool for the device packaging structure, such as using finite element analysis software to model and calculate the routing path of the auxiliary emitter and the main emitter. The rate of change of the collector current can be captured in real time by a measurement system consisting of a high-frequency current probe and an oscilloscope, and differential operations are performed by a digital signal processor. When there is an auxiliary emitter in the emitter structure, the test circuit is as shown in Figure 3 (b), and when there is no auxiliary emitter in the emitter structure, E and E' are 1 point, and the parasitic inductance on the emitter side is all the common emitter parasitic inductance L. s,E1 , L s,E3 is 0.

[0079] In this step, the test circuit is shown in Figure 3(b), where the drive circuit is connected to the auxiliary emitter E' and gate G of the IGBT, where one end of the auxiliary emitter E' is connected to the emitter side line parasitic inductance L in the drive circuit. s,E2 , L s,E2 The other end is connected to the turn-on drive voltage U G,on , turn off the driving voltage U G,off One end is connected, which turns on the driving voltage U G,on The other end is connected to the turn-on drive resistor R G,on Connect and shut down the drive voltage U G,off The other end is connected to the off drive resistor R G,off Connect, open the drive resistor R G,on Or turn off the driving resistor R G,off The other end of the connection is connected to the parasitic inductance L of the gate side line through the switch s,G2 Connection to control the operation of the electric drive circuit, in addition, the parasitic inductance L of the gate side line s,G2The other end is connected to the gate G. The circuit of the main loop is connected to the collector C and emitter E of the IGBT, wherein one end of the emitter E is connected to the DC bus capacitor c (c represents the capacitor symbol), the other end of the DC bus capacitor is connected to one end of the power loop parasitic inductance excluding the parasitic inductance of the IGBT and FWD devices and the parasitic inductance of the freewheeling loop, and the other end of the power loop parasitic inductance excluding the parasitic inductance of the IGBT and FWD devices and the parasitic inductance of the freewheeling loop is respectively connected to one end of the FWD device and one end of the load inductance, wherein the other end of the load inductance is connected to the collector C of the IGBT, the FWD device (parasitic inductance L inside the FWD device) S,F ) and the parasitic inductance L of the freewheeling circuit s,2 (L s,2 The FWD package parasitic inductance L is not included. S,F ), freewheeling circuit parasitic inductance L s,2 The other end is connected to the collector C of the IGBT. When the above circuit is running, there is a gate current i G 、i C is the IGBT collector current, i F is the FWD current and the IGBT chip collector-emitter capacitance side current i CE and the IGBT device gate-collector capacitance side current i GC The directions of the current flows are shown in the figure.

[0080] The meanings of the symbols in Figure 3(b) are as follows: (1) FWD device parameters: i F is the FWD current, u F Indicates FWD device voltage, u chip,F Indicates FWD chip voltage, L s,F Indicates the internal parasitic inductance of the FWD device, u s,F Indicates the voltage on the parasitic inductance inside the FWD device. (2) IGBT device parameters: C is the device collector, G is the device gate, E is the device emitter, E' is the device auxiliary emitter, i C is the IGBT collector current, u CE Indicates IGBT device voltage, u chip,CE Indicates IGBT chip voltage, C GE Indicates the gate-emitter capacitance of the IGBT chip, C GC Indicates the gate-collector capacitance (Miller capacitance) of the IGBT device, C CE Indicates the collector-emitter capacitance of the IGBT chip. L s,G1 represents the gate parasitic inductance, L s,C represents the collector parasitic inductance, L s,E1 represents the common emitter parasitic inductance, L s,E3Represents the parasitic inductance between the auxiliary emitter and the device emitter, that is, the first inductance. s,G1 、u s,C 、u s,E1 and u s,E3 Respectively represent the above parasitic inductance (L s,G1 , L s,C , L s,E1 and L s,E3 ) voltage on the . (3) Main circuit parameters: c represents the DC bus capacitance, U DC Indicates the DC bus capacitor voltage (under no-load condition), L s,2 Indicates the parasitic inductance of the freewheeling circuit (but not including the parasitic inductance of the FWD package L s,F ), L s,1 It represents the parasitic inductance of the power circuit excluding the parasitic inductance of the IGBT and FWD devices and the parasitic inductance of the freewheeling circuit. (4) Drive circuit parameters: U G,on To turn on the driving voltage, U G,off is the turn-off driving voltage, R G,on To turn on the drive resistor, R G,off is the turn-off drive resistor, L s,G2 is the parasitic inductance of the gate side line, L s,E2 is the parasitic inductance of the emitter side line.

[0081] Step 502: Determine a first voltage based on the first parasitic inductance and the rate of change of the collector current, where the first voltage is the voltage on the first parasitic inductance.

[0082] After the data is acquired in step 501, the first voltage is calculated according to the following formula:

[0083]

[0084] Among them, U S,E3 is the first voltage, L S,E3 The first parasitic inductance, di c / dt is the rate of change of collector current.

[0085] Step 503: If the first voltage is within a first preset voltage range, determine that a second type short circuit occurs in the insulated gate bipolar transistor.

[0086] After obtaining the first voltage, it is determined whether the first voltage is within a first preset voltage range. If it is determined that a type II short circuit occurs in the insulated gate bipolar transistor. The first preset voltage range is determined based on simulation of actual conditions, and its specific data value is not limited here. It can be seen that compared with the prior art, in an insulated gate bipolar transistor with an auxiliary emitter, this solution can directly convert the current mutation caused by the short circuit into a detectable voltage signal by quantifying the parasitic inductance effect between the auxiliary emitter and the main emitter. This detection mechanism avoids the voltage fluctuation interference caused by the parasitic inductance of the main circuit during the conduction process, thereby accurately identifying the short circuit state at any stage of the IGBT conduction.

[0087] In addition, the applicant simulated the operation process of IGBTs with different structures (with or without auxiliary emitters) and obtained Figure 6 ,according to Figure 6 It can be seen that:

[0088] 1) t0~t1 period: i C Rise, u CE There is also a certain degree of increase, but u CE The rise is not due to the IGBT entering the active area, but is caused by the voltage induced on the parasitic inductance of the IGBT package inside.

[0089] ① There is an auxiliary emitter E': Due to L s,E3 >>L s,E1 ≈0, so u GE Opposite C / dt is not sensitive. That is, when the IGBT does not have an auxiliary emitter, it is necessary to determine whether the IGBT is short-circuited according to the method of steps 501-503.

[0090] ② There is no auxiliary emitter E': At this time, it is impossible to collect L s,E3 The voltage on the circuit is used to analyze whether a short circuit has occurred. GE Including L s,E3 The voltage on GE It will also be higher than normal levels. GE The change in can be used to determine whether a short circuit occurs.

[0091] 2) t1~t2 period: i C Continue to rise, u CE A substantial increase. CE The rise of is due to the IGBT entering the active region (entering the desaturation stage). C The reason for the continued rise is u CE A substantial increase in the Miller capacitance C GC Coupling leads to u chip,GEDuring this phase, desaturation protection begins to take effect and lasts until t4.

[0092] 3) t2~t3 period: i C Descend, u CE Overshoot occurs. CE The reason for the overshoot is the total parasitic inductance L of the IGBT external circuit. s0 The voltage induced on the C The reason for the decline is u CE The sharp rise phase has passed and cannot pass the Miller capacitance C GC Coupling pair C GE Further charging. Due to the existence of the gate loop, C GE More charges are released through the gate circuit and the gate voltage drops to normal level.

[0093] 4) t3~t4 period: This period i C There is a slight decrease, which is due to the short-circuit process heating the IGBT chip, resulting in a decrease in carrier mobility.

[0094] 5) t4~t5 period: The short circuit process is completed and the device is shut down during this period.

[0095] Furthermore, as a response to the above Figure 1 、 Figure 4 、 Figure 5 The embodiment of the present application provides a device for identifying the second type of short circuit state of an insulated gate bipolar transistor. This device embodiment corresponds to the aforementioned method embodiment. For ease of reading, this device embodiment will no longer describe the details of the aforementioned method embodiment one by one, but it should be clear that the device in this embodiment can correspond to all the contents of the aforementioned method embodiment. This device can obtain accurate corpus analysis results, specifically as follows Figure 7 As shown, the device includes:

[0096] An acquisition unit 71 is used to acquire an emitter structure of an insulated gate bipolar transistor in a test circuit;

[0097] The acquisition unit 71 is configured to acquire the chip gate voltage, gate parasitic inductance, common emitter parasitic inductance in the gate drive loop, and collector current in the main loop if the emitter structure does not have an auxiliary emitter. The common emitter parasitic inductance is the common parasitic inductance of the gate drive loop and the collector-emitter loop.

[0098] a voltage determination unit 72 for determining a gate voltage based on Kirchhoff's voltage law and utilizing the chip gate voltage in the gate drive circuit of the acquisition unit 71, the gate parasitic inductance, the common emitter parasitic inductance, and the collector current;

[0099] The judging unit 73 is configured to determine that a second type short circuit occurs in the insulated gate bipolar transistor if the gate voltage of the voltage determining unit 72 is within a preset short circuit voltage range.

[0100] Further, such as Figure 8 As shown, the determining unit 72 includes:

[0101]

[0102] Among them, U in the above formula (1) GE Indicates the gate voltage, U chip,GE Indicates the chip gate voltage, L s,G1 represents the gate parasitic inductance, L s,G2 Indicates the parasitic inductance of the gate side line, L s,E2 Indicates the parasitic inductance of the emitter side line, L s,E1 represents the common emitter parasitic inductance, i GE represents the current from gate to collector, i C represents the collector current, i G represents the gate current, and t represents the time in seconds.

[0103] Further, such as Figure 8 As shown, the determining unit 72 includes:

[0104] The conversion module 721 is used to simplify the above formula (1) based on the change rate of the gate current, the change rate of the collector current, and the change rate of the gate-to-collector current as follows:

[0105]

[0106] Further, such as Figure 8 As shown, the apparatus further includes a range determination unit 74, and the range determination unit 74 includes:

[0107] The numerical value acquisition module 741 is used to obtain the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, IGBT internal PNP transistor amplification factor and threshold voltage;

[0108] The numerical value acquisition module 741 is used to obtain the control relationship between the gate voltage and the collector current according to the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, IGBT internal PNP transistor amplification factor and threshold voltage of the numerical value acquisition module;

[0109] A determination module 742 is configured to determine a collector current expression based on the control relationship of the value acquisition module 741;

[0110] The determining module 742 is configured to calculate, based on the collector current expression, a rate of change of the collector current when the insulated gate bipolar transistor operates normally;

[0111] The range determination module 743 is used to determine the preset short-circuit voltage range based on the change rate of the collector current, the common emitter parasitic inductance, the chip gate voltage and the preset change rate variation multiple of the determination module 742.

[0112] Further, such as Figure 8 As shown, the device also includes:

[0113] a data acquisition unit 75 for acquiring, if the emitter structure has an auxiliary emitter, a first parasitic inductance and a rate of change of the collector current, wherein the first parasitic inductance is a parasitic inductance between the auxiliary emitter and the emitter of the insulated gate bipolar transistor;

[0114] a first voltage determining unit 76 configured to determine a first voltage based on the first parasitic inductance of the data acquiring unit 75 and the rate of change of the collector current, wherein the first voltage is a voltage on the first parasitic inductance;

[0115] If the first voltage is within a first preset voltage range, it is determined that a second type short circuit occurs in the insulated gate bipolar transistor.

[0116] Furthermore, an embodiment of the present invention also provides a computing device, the computing device comprising: at least one processor, and a memory, wherein the memory stores instructions that can be executed by the processor, and the instructions are executed by the processor, so that the processor can perform the above-mentioned Figure 1 、 Figure 4 、 Figure 5 A method for identifying the second type of short-circuit state of an insulated gate bipolar transistor described in.

[0117] Furthermore, an embodiment of the present invention further provides a readable storage medium, wherein the readable storage medium is used to store a computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute the above-mentioned Figure 1 、 Figure 4 、 Figure 5 A method for identifying the second type of short-circuit state of an insulated gate bipolar transistor described in.

[0118] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0119] It is understood that the relevant features of the above methods and devices can be referenced to each other. In addition, the terms "first" and "second" in the above embodiments are used to distinguish between the embodiments, and do not represent the advantages and disadvantages of the embodiments.

[0120] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0121] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general-purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing this type of system. In addition, the present invention is not directed to any specific programming language. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of the present invention.

[0122] In addition, the memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0123] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0124] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0125] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0126] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0127] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0128] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0129] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0130] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0131] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The above is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for identifying a type II short-circuit state of an insulated gate bipolar transistor, characterized in that: include: obtaining an emitter structure of an insulated gate bipolar transistor in a test circuit; If the emitter structure does not have an auxiliary emitter, then obtain the chip gate voltage, gate side line parasitic inductance, gate parasitic inductance, emitter side line parasitic inductance, common emitter parasitic inductance, gate current, collector current, and gate-to-collector current in the gate drive loop, where the common emitter parasitic inductance is the common parasitic inductance of the gate drive loop and the collector-emitter loop; Based on Kirchhoff's voltage law, the gate voltage is determined using the chip gate voltage, gate-side line parasitic inductance, gate parasitic inductance, emitter-side line parasitic inductance, common-emitter parasitic inductance, gate current, collector current in the main loop, and gate-to-collector current in the gate drive circuit; If the gate voltage is within the preset short-circuit voltage range, it is determined that a second type short circuit occurs in the insulated gate bipolar transistor.

2. The method according to claim 1, characterized in that The gate voltage is determined based on Kirchhoff's voltage law using the chip gate voltage, gate side line parasitic inductance, gate parasitic inductance, emitter side line parasitic inductance, common emitter parasitic inductance, gate current, collector current in the main loop, and gate-to-collector current in the gate drive loop, including: Among them, U in formula (1) GE Indicates the gate voltage, U chip,GE Indicates the chip gate voltage, L s,G1 represents the gate parasitic inductance, L s,G2 Indicates the parasitic inductance of the gate side line, L s,E2 Indicates the parasitic inductance of the emitter side line, L s,E1 represents the common emitter parasitic inductance, i GE represents the current from gate to collector, i C represents the collector current, i G represents the gate current, and t represents the time in seconds.

3. The method according to claim 2, characterized in that The method further comprises: The simplified formula (1) based on the change rate of gate current, the change rate of collector current, and the change rate of gate-to-collector current is as follows: Among them, U in the formula GE Indicates the gate voltage, U chip,GE Indicates the chip gate voltage, L s,E1 represents the common emitter parasitic inductance, i C represents the collector current, and t represents the time in seconds.

4. The method according to claim 1, wherein The method further comprises: Obtain gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, IGBT internal PNP transistor amplification factor, and threshold voltage; Determining a control relationship between the gate voltage and the collector current based on the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, IGBT internal PNP transistor amplification factor, and threshold voltage; Based on the control relationship, the collector current expression is obtained; Calculate, based on the collector current expression, the rate of change of the collector current when the insulated gate bipolar transistor is operating normally; The preset short-circuit voltage range is determined based on the change rate of the collector current, the common-emitter parasitic inductance, the chip gate voltage, and a preset change rate multiple.

5. The method according to claim 1, wherein The method further comprises: If the emitter structure has an auxiliary emitter, obtaining a first parasitic inductance and a rate of change of a collector current, where the first parasitic inductance is a parasitic inductance between the auxiliary emitter and an emitter of an insulated gate bipolar transistor; determining a first voltage based on the first parasitic inductance and a rate of change of the collector current, wherein the first voltage is a voltage across the first parasitic inductance; If the first voltage is within a first preset voltage range, it is determined that a second type short circuit occurs in the insulated gate bipolar transistor.

6. A device for identifying a type II short-circuit state of an insulated gate bipolar transistor, characterized in that: include: an acquiring unit, configured to acquire an emitter structure of an insulated gate bipolar transistor in a test circuit; The acquisition unit is configured to acquire the chip gate voltage, gate parasitic inductance, common emitter parasitic inductance in the gate drive loop, and collector current in the main loop if the emitter structure does not have an auxiliary emitter, wherein the common emitter parasitic inductance is the common parasitic inductance of the gate drive loop and the collector-emitter loop; a voltage determination unit, configured to determine a gate voltage based on Kirchhoff's voltage law and utilizing the chip gate voltage, the gate parasitic inductance, the common emitter parasitic inductance, and the collector current in the gate drive loop of the acquisition unit; The judging unit is configured to determine that a second type of short circuit occurs in the insulated gate bipolar transistor if the gate voltage of the voltage determining unit is within a preset short circuit voltage range.

7. The device according to claim 6, characterized in that The apparatus further includes a range determination unit, wherein the range determination unit includes: The numerical acquisition module is used to obtain the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, IGBT internal PNP transistor amplification factor and threshold voltage; The numerical value acquisition module is used to obtain the control relationship between the gate voltage and the collector current according to the gate channel width, channel electron mobility, channel capacitance per unit area, gate channel length, IGBT internal PNP transistor amplification factor and threshold voltage of the numerical value acquisition module; A determination module, configured to determine a collector current expression based on the control relationship of the numerical value acquisition module; The determining module is configured to calculate, based on the collector current expression, a rate of change of the collector current when the insulated gate bipolar transistor operates normally; The range determination module is used to determine the preset short-circuit voltage range based on the change rate of the collector current of the determination module, the common emitter parasitic inductance, the chip gate voltage and the preset change rate variation multiple.

8. The device according to claim 6, characterized in that The device further comprises: a data acquisition unit, configured to acquire, if the emitter structure has an auxiliary emitter, a first parasitic inductance and a rate of change of a collector current, wherein the first parasitic inductance is a parasitic inductance between the auxiliary emitter and an emitter of an insulated gate bipolar transistor; a first voltage determining unit, configured to determine a first voltage based on the first parasitic inductance and a rate of change of the collector current, wherein the first voltage is a voltage on the first parasitic inductance; If the first voltage is within a first preset voltage range, it is determined that a second type short circuit occurs in the insulated gate bipolar transistor.

9. A computing device, characterized in that The computing device includes: at least one processor, and a memory, wherein the memory stores instructions that can be executed by the processor, and the instructions are executed by the processor, so that the processor can execute the method for identifying the second type of short circuit state of the insulated gate bipolar transistor as described in any one of claims 1-7.

10. A readable storage medium, characterized in that: The readable storage medium is used to store a computer program, wherein when the computer program is run, it controls the device where the storage medium is located to execute the method for identifying the second type short circuit state of the insulated gate bipolar transistor according to any one of claims 1 to 7.

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