Substrate, preparation method thereof and chip packaging structure

Abstract

The invention relates to a substrate and a preparation method thereof and a chip packaging structure, the substrate comprises a core layer and a rewiring layer arranged on at least one side surface of the core layer, the core layer comprises an inorganic non-metal material layer, and the material thermal expansion coefficient of the inorganic non-metal material layer is 3 ppm / DEG C to 8 ppm / DEG C. The core layer is made of the inorganic non-metal material with a lower thermal expansion coefficient, so that the high-frequency signal loss of the substrate can be reduced, the difference between the effective thermal expansion coefficient of the core layer and the thermal expansion coefficient of the silicon chip can be reduced, the effective thermal expansion performance of the core layer is further matched with the silicon chip, and the service life of the silicon chip is prolonged. When the silicon chip is arranged on the substrate, the silicon chip is connected with the core layer through the rewiring layer, and the core layer and the silicon chip have good thermal expansion coefficient matching performance, so that the thermal stress between the substrate and the silicon chip can be reduced, the reliability is improved, and the risk of warping and layering between the substrate and the silicon chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a substrate and a preparation method thereof, as well as a chip packaging structure. Background Art

[0002] Conventional substrates utilize bismaleimide triazine (BT) and glass fiber (FR-4 / 5) as the core layer, with Ajinomoto build-up film (ABF) serving as the rewiring dielectric layer. Multilayer wiring is achieved through a semi-additive process (SAP) or modified semi-additive process (mSAP). Because the core layer is made of bismaleimide triazine and glass fiber, and the coefficient of thermal expansion (CTE) of glass fiber is approximately 16 ppm / °C, significantly higher than the 3 ppm / °C of silicon chips, the mismatch in CTE can lead to interfacial stress accumulation between the silicon chip and substrate during thermal cycling, reducing reliability. Furthermore, the CTE difference between the core layer and the silicon chip can easily lead to warping and delamination. Summary of the Invention

[0003] The embodiments of the present application provide a substrate and a preparation method thereof, as well as a chip packaging structure, to at least partially solve the above-mentioned technical problems.

[0004] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a substrate is provided, comprising a core layer and a redistribution layer arranged on at least one side surface of the core layer, wherein the core layer comprises an inorganic non-metallic material layer, and the thermal expansion coefficient of the inorganic non-metallic material layer is 3ppm / ℃ to 8ppm / ℃.

[0005] Optionally, the rewiring layer includes a first metal circuit layer, the first metal circuit layer is electrically connected to the core layer, and the first metal circuit layer is a metal electrodeposition layer prepared by a wafer-level rewiring process.

[0006] Optionally, the first metal circuit layer includes multiple metal circuits, the line width of the metal circuits is less than or equal to 5μm; and / or the line spacing of the metal circuits is less than or equal to 5μm; and / or the thickness of the first metal circuit layer is 3μm to 7μm; and / or the surface roughness of the first metal circuit layer is less than or equal to 0.5μm.

[0007] Optionally, the redistribution layer further includes a dielectric layer, the first metal circuit layer includes a first body arranged on the side surface of the dielectric layer, a first opening is provided through the dielectric layer, the first metal circuit layer further includes a first conductive portion arranged in the first opening, and the first conductive portion is connected to the first body.

[0008] Optionally, the number of the first metal circuit layers is less than or equal to 6 layers, and the number of the dielectric layers is less than or equal to 6 layers; and / or the material of the dielectric layer includes at least one of photosensitive polyimide, benzocyclobutene and polybenzoxazole; and / or the dielectric layer is a spin-coated layer; and / or the thickness of the dielectric layer is 5μm to 10μm.

[0009] Optionally, the number of the first metal circuit layers and the number of the dielectric layers are both multiple layers, and the first metal circuit layers and the dielectric layers are alternately arranged, and two adjacent first metal circuit layers are electrically connected through the first conductive part.

[0010] Optionally, the core layer further includes a second metal circuit layer, which is disposed on the inorganic non-metallic material layer and is electrically connected to the first metal circuit layer.

[0011] Optionally, the number of the inorganic non-metallic material layer and the second metal circuit layer are both multiple layers, the inorganic non-metallic material layers and the second metal circuit layers are alternately arranged, and two adjacent layers of the second metal circuit layers are electrically connected; and / or, the second metal circuit layer includes a second body arranged on the side surface of the inorganic non-metallic material layer, a second opening is provided through the inorganic non-metallic material layer, the second metal circuit layer also includes a second conductive portion arranged in the second opening, and the second conductive portion is connected to the second body.

[0012] Optionally, the material of the inorganic non-metallic material layer includes at least one of borosilicate glass, AlN and Al2O3; and / or the thickness of the core layer is 200μm to 600μm; and / or the length of the core layer is 5mm to 80mm, and the width is 5mm to 80mm; and / or the redistribution layer is provided on the opposite surfaces of the core layer; and / or the surface roughness of the core layer is 10nm to 1000nm; and / or the surface energy of the core layer is greater than or equal to 50mN / m; and / or the contact angle of the surface of the core layer to deionized water is less than or equal to 10°.

[0013] According to a second aspect of the present application, a method for preparing a substrate is provided, for preparing the above-mentioned substrate, comprising:

[0014] Providing a core layer, wherein the surface roughness of the core layer is 10 nm to 1000 nm;

[0015] fixing the core layer on a temporary carrier;

[0016] Preparing a plastic sealing layer on the temporary carrier, wherein the plastic sealing layer seals the core layer;

[0017] Removing the temporary carrier plate so that a portion of the core layer is exposed to a side surface of the plastic packaging layer;

[0018] A wafer-level rewiring process is used to prepare a rewiring layer on the surface of the plastic packaging layer on the side where the core layer is exposed, so that the rewiring layer is connected to the core layer;

[0019] The plastic sealing layer is removed to obtain a substrate.

[0020] Optionally, the core layer is surface treated so that the surface energy of the core layer is greater than or equal to 50 mN / m.

[0021] Optionally, the contact angle of the surface of the core layer to deionized water is less than or equal to 10°.

[0022] Optionally, the step of preparing a rewiring layer on a surface of the plastic packaging layer on a side where the core layer is exposed by a wafer-level rewiring process so that the rewiring layer is connected to the core layer comprises:

[0023] Corresponding to the side of the plastic encapsulation layer that exposes the core layer, coating a first photoresist on the plastic encapsulation layer, exposing, developing, and curing the first photoresist to obtain a dielectric layer having a first opening;

[0024] growing a seed layer on the surface of the dielectric layer and in the first opening;

[0025] Coating a second photoresist on the surface of the seed layer, and exposing, developing and curing the second photoresist to obtain a patterned adhesive layer;

[0026] Electroplating metal on the patterned adhesive layer to obtain a patterned first metal circuit layer;

[0027] The patterned adhesive layer and the seed layer corresponding to the patterned adhesive layer are removed to obtain a rewiring layer.

[0028] According to a third aspect of the present application, a chip packaging structure is provided, which includes a silicon chip and the above-mentioned substrate, wherein the silicon chip is arranged on the substrate and connected to the redistribution layer.

[0029] The substrate provided in the embodiment of the present application can be packaged with a silicon chip to form a chip packaging structure. In the substrate, by using an inorganic non-metallic material with a lower thermal expansion coefficient to make the core layer, the inorganic non-metallic material has the characteristics of low dielectric constant and low loss, which can reduce the high-frequency signal loss of the substrate. At the same time, the thermal expansion coefficient of the inorganic non-metallic material is controlled to 3ppm / ℃~8ppm / ℃, reducing the difference between the effective thermal expansion coefficient of the core layer and the thermal expansion coefficient of the silicon chip, thereby making the effective thermal expansion performance of the core layer more compatible with the silicon chip. When the silicon chip is set on the substrate, the silicon chip is connected to the core layer through the redistribution layer. Since the core layer and the silicon chip have good thermal expansion coefficient matching, the thermal stress between the substrate and the silicon chip can be reduced, the reliability is improved, and the risk of warping and delamination between the substrate and the silicon chip is reduced.

[0030] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0032] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0033] Figure 1 is an internal cross-sectional view of a substrate provided in an exemplary embodiment of the present application;

[0034] Figure 2 yes Figure 1 Enlarged view of part A;

[0035] Figures 3 to 9 is a flow chart for preparing a substrate provided in an exemplary embodiment of the present application;

[0036] Figure 10 is an internal cross-sectional view of another substrate provided in an exemplary embodiment of the present application;

[0037] Figures 11 to 18 is a flow chart for preparing a redistribution layer in a substrate provided in an exemplary embodiment of the present application;

[0038] Figure 19 FIG. 4 is an internal cross-sectional view of a chip package structure provided in an exemplary embodiment of the present application.

[0039] Description of reference numerals:

[0040] 10. Substrate;

[0041] 1. core layer; 11. inorganic non-metallic material layer; 12. second metal circuit layer; 121. second body; 122. second conductive portion; 13. second opening;

[0042] 2. Rewiring layer; 21. First metal circuit layer; 211. First body; 212. First conductive portion; 22. Dielectric layer; 220. First initial adhesive layer; 23. First opening;

[0043] 3. Temporary carrier board;

[0044] 4. Temporary bonding layer;

[0045] 5. Plastic sealing layer;

[0046] 6. Seed layer;

[0047] 7. Patterned adhesive layer; 70. Second initial adhesive layer;

[0048] 100. Chip packaging structure; 20. Chip. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0050] First, see Figure 1 、 Figure 2 、 Figure 10 and Figure 12 The present invention provides a substrate 10 in an embodiment. The substrate 10 includes a core layer 1 and a redistribution layer 2 disposed on at least one surface of the core layer 1. The core layer 1 includes an inorganic non-metallic material layer 11. The thermal expansion coefficient of the inorganic non-metallic material layer 11 is 3 ppm / °C to 8 ppm / °C.

[0051] The primary function of substrate 10 is to provide physical support and electrical connections for the chip. Optionally, substrate 10 is a high-frequency substrate, specifically designed to process high-frequency signals to ensure signal stability and efficiency during high-frequency transmission. High-frequency substrates are used in wireless communications, satellite communications, radar systems, automotive collision avoidance systems, and high-end electronic devices.

[0052] The substrate 10 includes a core layer 1 . The core layer 1 , as the main body of the substrate 10 , undertakes the mechanical support function of the entire substrate 10 and is a key part for carrying the chip.

[0053] The substrate 10 also includes a rewiring layer 2, which is used to optimize the pin distribution and signal transmission path of the chip. The rewiring layer 2 is arranged on the surface of the core layer 1, and the rewiring layer 2 can be used to electrically connect to the chip 20 and / or the external circuit. Optionally, the core layer 1 includes a conductive structure, which is electrically connected to the rewiring layer 2, so that the core layer 1 is electrically connected to the chip 20 and / or the external circuit through the rewiring layer 2. It should be noted here that in the substrate 10, the rewiring layer 2 can be provided on only one side surface of the core layer 1, or the rewiring layer 2 can be provided on both opposite sides of the core layer 1. In other words, in the substrate 10, the number of rewiring layers 2 can be one layer or multiple layers. When the number of rewiring layers 2 is multiple layers, the structures between different rewiring layers 2 can be the same or different.

[0054] The core layer 1 includes a perforated inorganic non-metallic material layer 11. The inorganic non-metallic material layer 11 is primarily composed of an inorganic non-metallic material. Inorganic non-metallic materials have good heat resistance, which effectively improves the thermal reliability of the substrate 10. They also possess high mechanical strength, thereby enhancing the support performance of the substrate 10. For example, the inorganic non-metallic material includes at least one of glass and ceramic.

[0055] The thermal expansion coefficient of the inorganic non-metallic material layer 11 is 3 ppm / °C to 8 ppm / °C, that is, the thermal expansion coefficient of the inorganic non-metallic material constituting the inorganic non-metallic material layer 11 is 3 ppm / °C to 8 ppm / °C. As an example, the thermal expansion coefficient of the inorganic non-metallic material layer 11 is 3 ppm / °C, 3.5 ppm / °C, 4 ppm / °C, 4.5 ppm / °C, 5 ppm / °C, 5.5 ppm / °C, 6 ppm / °C, 6.5 ppm / °C, 7 ppm / °C, 7.5 ppm / °C, or 8 ppm / °C.

[0056] The substrate 10 provided in the embodiment of the present application can be packaged with the silicon chip 20 to form a chip package structure 100. In the substrate 10, the inorganic non-metallic material layer 11 of the core layer 1 is made of an inorganic non-metallic material with a lower thermal expansion coefficient. The inorganic non-metallic material has the characteristics of low dielectric constant and low loss, which can reduce the high-frequency signal loss of the substrate 10. At the same time, the thermal expansion coefficient of the inorganic non-metallic material is controlled to 3ppm / °C to 8ppm / °C, reducing the difference between the effective thermal expansion coefficient of the core layer 1 and the thermal expansion coefficient of the silicon chip 20, thereby making the thermal expansion performance of the core layer 1 more compatible with the silicon chip 20. When the silicon chip 20 is placed on the substrate 10, the silicon chip 20 is connected to the core layer 1 through the redistribution layer 2. Due to the good thermal expansion coefficient matching between the core layer 1 and the silicon chip 20, the thermal stress between the substrate 10 and the silicon chip 20 can be reduced, thereby improving reliability and reducing the risk of warping and delamination between the substrate 10 and the silicon chip 20.

[0057] In some embodiments, see Figure 2 The rewiring layer 2 includes a first metal circuit layer 21, which is electrically connected to the core layer 1, and the first metal circuit layer 21 is a metal electrodeposition layer prepared by a wafer-level rewiring process.

[0058] The rewiring layer 2 includes a first metal circuit layer 21. The core layer 1 is electrically connected to the first metal circuit layer 21. The first metal circuit layer 21 is composed of a plurality of metal circuits, which can constitute a signal transmission path. It should be noted that the number of first metal circuit layers 21 in the rewiring layer 2 can be a single layer or multiple layers. More specifically, the first metal circuit layer 21 is a metal electrodeposition layer prepared using a wafer-level rewiring process. The wafer-level rewiring process specifically includes growing a seed layer, coating a photoresist on the seed layer, forming a desired circuit pattern by exposure and development, electrochemically depositing a metal layer on the seed layer, and then removing the photoresist and removing the unprotected metal portion through an etching process to obtain a metal circuit.

[0059] The wafer-level rewiring process has the advantage of high precision. With such a setting, on the one hand, the line width of the metal circuit in the first metal circuit layer 21 can be made smaller, and on the other hand, the line spacing between different metal circuits can be made smaller, thereby increasing the number of metal circuits in the first metal circuit layer 21, that is, achieving high-density wiring. In this way, not only can the metal circuits in the first metal circuit layer 21 achieve high-density interconnection and improve power supply or signal integrity, but the number of layers of the first metal circuit layer 21 in the substrate 10 can also be reduced, that is, the number of wiring layers can be reduced.

[0060] In summary, substrate 10 includes a core layer 1 and a rewiring layer 2, wherein rewiring layer 2 includes a first metal wiring layer 21. This first metal wiring layer 21 is a metal electrodeposition layer produced using a wafer-level rewiring process. This not only enables high-density wiring, improving power or signal integrity, but also reduces the number of wiring layers. Furthermore, thanks to the wafer-level rewiring process, the metal electrodeposition layer typically also has a low surface roughness, which reduces the surface roughness of the wiring, thereby reducing signal transmission loss, especially effectively reducing high-frequency loss.

[0061] In some embodiments, the first metal circuit layer 21 is a copper layer, and the first metal circuit layer 21 includes a plurality of metal circuits, and the metal circuits are copper wires. Copper has good electrical conductivity, which helps to improve the current carrying capacity of the first metal circuit layer 21.

[0062] In some embodiments, the first metal circuit layer 21 includes multiple metal circuits, each having a line width of less than or equal to 5 μm. Compared to the 20 μm line width in conventional technology, the line width of the first metal circuit layer 21 in the substrate 10 provided in the embodiments of the present application is significantly reduced, thereby effectively increasing the wiring density of the first metal circuit layer 21. As an example, the line width of the metal circuit is 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm.

[0063] In some embodiments, the first metal circuit layer 21 includes multiple metal circuits, and the line pitch of the metal circuits is less than or equal to 5μm. The line pitch of the metal circuit refers to the spacing between two adjacent metal circuits. Compared to the line pitch of 20μm in conventional technology, the line pitch of the first metal circuit layer 21 in the substrate 10 provided in the embodiment of the present application is significantly reduced, thereby effectively increasing the wiring density of the first metal circuit layer 21. As an example, the line pitch of the metal circuit is 1μm, 2μm, 3μm, 4μm, or 5μm.

[0064] In some embodiments, the surface roughness Rz of the first metal circuit layer 21 is less than or equal to 0.5 μm. The surface roughness of the metal circuit layer (e.g., copper layer) prepared by the traditional electroplating process is 0.7 μm to 2.0 μm. Compared with the traditional electroplating process, the surface roughness of the first metal circuit layer 21 in the substrate 10 provided in the embodiment of the present application is significantly reduced, which is beneficial to reducing signal transmission loss. Optionally, the surface roughness Rz of the first metal circuit layer 21 is generally consistent with the surface roughness of the metal circuit. As an example, the surface roughness Rz of the first metal circuit layer 21 is 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm.

[0065] In some embodiments, the thickness of the first metal circuit layer 21 is 3 μm to 7 μm. Typically, the thickness of the first metal circuit layer 21 is equal to the thickness of the metal circuit. As an example, the thickness of the first metal circuit layer 21 is 3 μm, 4 μm, 5 μm, 6 μm, or 7 μm.

[0066] In some embodiments, the inorganic non-metallic material layer 11 includes at least one of borosilicate glass, AlN, and Al2O3. The inorganic non-metallic materials borosilicate glass, AlN, and Al2O3 all have relatively low thermal expansion coefficients, thereby improving the anti-thermal expansion effect of the inorganic non-metallic material layer 11.

[0067] In some embodiments, the thickness of the core layer 1 is 200 μm to 600 μm. For example, the thickness of the core layer 1 is 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm or 600 μm.

[0068] In some embodiments, the length of the core layer 1 is 5 mm to 80 mm. As an example, the length of the core layer 1 is 5 mm, 10 mm, 20 mm, 30 mm, 40 mm, 50 mm, 60 mm, 70 mm or 80 mm.

[0069] In some embodiments, the width of the core layer 1 is 5 mm to 80 mm. As an example, the width of the core layer 1 is 5 mm, 10 mm, 20 mm, 30 mm, 40 mm, 50 mm, 60 mm, 70 mm or 80 mm.

[0070] In some embodiments, the surface roughness of the core layer 1 is 10 nm to 1000 nm. For example, the surface roughness of the core layer 1 is 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm or 1000 nm.

[0071] In some embodiments, the surface energy of the core layer 1 is greater than or equal to 50 mN / m. For example, the surface energy of the core layer 1 is 50 mN / m, 60 mN / m, 80 mN / m, or 100 mN / m.

[0072] In some embodiments, the contact angle of the surface of the core layer 1 to deionized water is less than or equal to 10°. As an example, the contact angle of the surface of the core layer 1 to deionized water is 1°, 5°, 6°, 7°, 8°, 9° or 10°.

[0073] In some embodiments, see Figure 2The core layer 1 also includes a second metal circuit layer 12, which is arranged on the inorganic non-metallic material layer 11, and the second metal circuit layer 12 is electrically connected to the first metal circuit layer 21. In the above technical solution, the second metal circuit layer 12 of the core layer 1 is electrically connected to the first metal circuit layer 21 of the redistribution layer 2, thereby realizing electrical connection between the core layer 1 and the redistribution layer 2. Optionally, the second metal circuit layer 12 is arranged on at least one side surface of the inorganic non-metallic material layer 11, and the second metal circuit layer 12 may be provided on one side surface of the inorganic non-metallic material layer 11, or the second metal circuit layer 12 may be provided on both opposite sides of the inorganic non-metallic material layer 11. As an example, the core layer 1 includes one inorganic non-metallic material layer 11 and two second metal circuit layers 12, and the two second metal circuit layers 12 are respectively provided on the opposite sides of the inorganic non-metallic material layer 11, thereby forming a sandwich structure.

[0074] In some embodiments, see Figure 2 The number of inorganic non-metallic material layers 11 and second metal circuit layers 12 are both multiple layers, and the second metal circuit layers 12 and the inorganic non-metallic material layers 11 are alternately arranged, and two adjacent layers of second metal circuit layers 12 are electrically connected. The number of inorganic non-metallic material layers 11 is at least two, and the number of second metal circuit layers 12 is at least two. Between two adjacent layers of second metal circuit layers 12 is an inorganic non-metallic material layer 11, and between two adjacent layers of inorganic non-metallic material layers 11 is a second metal circuit layer 12. However, the number of inorganic non-metallic material layers 11 and the number of second metal circuit layers 12 can be equal or unequal. Optionally, the inorganic non-metallic material layer 11 is a ceramic layer, and the core layer 1 is a co-fired ceramic layer. When the core layer 1 is a co-fired ceramic layer, the co-fired ceramic layer includes alternating second metal circuit layers 12 and ceramic layers. When preparing the co-fired ceramic layer, several second metal circuit layers 12 and ceramic layers can be alternately stacked together and then formed into a whole through a co-firing process.

[0075] In some embodiments, see Figure 2, the second metal circuit layer 12 includes a second body 121 and a second conductive part 122. The second body 121 is arranged on the side surface of the inorganic non-metallic material layer 11. A second opening 13 is provided through the inorganic non-metallic material layer 11, the second conductive part 122 is provided in the second opening 13, and the second conductive part 122 is connected to the second body 121. In this case, when the second bodies 121 are provided on both opposite side surfaces of the inorganic non-metallic material layer 11, that is, the two adjacent layers of the second body 121 are separated by the inorganic non-metallic material layer 11, the two adjacent layers of the second body 121 can be electrically connected through the second conductive part 122. It should be noted here that when the number of inorganic non-metallic material layers 11 is multiple layers, the second openings 13 on different inorganic non-metallic material layers 11 can be set to correspond to each other in position, or can be set to be staggered in position. As an example, the second conductive part 122 is a copper column.

[0076] In some embodiments, the first metal circuit layer 21 is electrically connected to the core layer 1 , and the first metal circuit layer 21 may be connected to the second conductive portion 122 , or the first metal circuit layer 21 may be connected to the second body 121 .

[0077] In some embodiments, see Figure 2 , the rewiring layer 2 also includes a dielectric layer 22, and the first metal circuit layer 21 is arranged on the dielectric layer 22. Specifically, the first metal circuit layer 21 includes a first body 211 and a first conductive part 212, and the first body 211 is arranged on the side surface of the dielectric layer 22. A first opening 23 is provided through the dielectric layer 22, and the first conductive part 212 is provided in the first opening 23, and the first conductive part 212 is connected to the first body 211. In this case, when the first bodies 211 are provided on both opposite sides of the dielectric layer 22, that is, the two adjacent layers of the first bodies 211 are separated by the dielectric layer 22, the two adjacent layers of the first bodies 211 can be electrically connected through the first conductive part 212. It should be noted here that when the number of dielectric layers 22 is multiple layers, the first openings 23 on different dielectric layers 22 can be set to correspond to each other in position, or can be set to be staggered in position. As an example, the first conductive part 212 is a copper column.

[0078] In some embodiments, the first metal circuit layer 21 is electrically connected to the core layer 1 , and the first body 211 may be directly connected to the core layer 1 , or the first body 211 may be connected to the core layer 1 through the first conductive portion 212 .

[0079] In some embodiments, see Figure 2The number of first metal circuit layers 21 and dielectric layers 22 is multiple, and the first metal circuit layers 21 and dielectric layers 22 are alternately arranged. Adjacent first metal circuit layers 21 are electrically connected, for example, via first conductive portions 212. There are at least two first metal circuit layers 21 and at least two dielectric layers 22. A dielectric layer 22 is disposed between two adjacent first metal circuit layers 21, and a first metal circuit layer 21 is disposed between two adjacent dielectric layers 22. However, the number of dielectric layers 22 and the number of first metal circuit layers 21 may be equal or unequal.

[0080] In some embodiments, see Figure 2 , the number of first metal wiring layers 21 is less than or equal to 6 layers, and the number of dielectric layers 22 is less than or equal to 6 layers. Because the first metal wiring layer 21 is a metal electrodeposition layer prepared using a wafer-level rewiring process, the wiring density of the first metal wiring layer 21 is improved. Therefore, the number of first metal wiring layers 21 can be reduced, and the number of synchronous dielectric layers 22 is also reduced. As an example, the number of first metal wiring layers 21 is 1 layer, 2 layers, 3 layers, 4 layers, 5 layers, or 6 layers; the number of dielectric layers 22 is 1 layer, 2 layers, 3 layers, 4 layers, 5 layers, or 6 layers. As an example, the number of wiring layers of the rewiring layer 2 is 6P6M.

[0081] In some embodiments, the material of dielectric layer 22 includes at least one of photosensitive polyimide (PSPI), benzocyclobutene (BCB), and polybenzoxazole (PBO). PSPI, BCB, and PBO are all low-dielectric, low-dissipation factor materials, which can improve power or signal integrity.

[0082] In some embodiments, the dielectric layer 22 is a spin-coated layer. A spin-coated layer refers to a material layer prepared by a spin coating process. This can simplify the preparation process of the dielectric layer 22 and reduce the production cost of the substrate 10.

[0083] In some embodiments, the thickness of the dielectric layer 22 is 5 μm to 10 μm. For example, the thickness of the dielectric layer 22 is 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0084] In some embodiments, see Figure 10, a rewiring layer 2 is provided on the opposite surfaces of the core layer 1. The rewiring layers 2 on the opposite sides of the core layer 1 can be electrically connected through the core layer 1. As an example, the core layer 1 includes an inorganic non-metallic material layer 11 and a second metal circuit layer 12, the inorganic non-metallic material layer 11 is a ceramic layer, and the rewiring layers 2 on the opposite sides of the core layer 1 can be electrically connected through the second metal circuit layer 12. As another example, the core layer 1 includes an inorganic non-metallic material layer 11, the inorganic non-metallic material layer 11 is a glass layer, and the glass layer is provided with through holes (not shown), and conductive pillars are provided in the through holes, and the rewiring layers 2 on the opposite sides of the core layer 1 can be electrically connected through the conductive pillars. In other words, the conductive structure of the core layer 1 includes at least one of a metal circuit (such as the second metal circuit layer 12) and a conductive pillar. Of course, in other cases, the inorganic non-metallic material layer 11 is a glass layer, and the glass layer may not be provided with through holes.

[0085] In some embodiments, the substrate 10 further includes solder balls (not shown), which are disposed on a surface of the redistribution layer 2 away from the core layer 1. The solder balls are typically tiny metal balls made of a solder alloy, such as Sn. 96.5 Ag3Cu or Sn 99.3 Ag 0.7 The setting of solder balls helps to improve the stability and reliability of signal transmission.

[0086] In a second aspect, the present invention also provides a method for preparing a substrate 10. The method for preparing the substrate 10 can be used to prepare the above-mentioned substrate 10. Figures 3 to 9 , the preparation method of the substrate 10 includes:

[0087] S1: If Figure 3 As shown, a core layer 1 is provided. The core layer 1 is made of low CTE glass (such as borosilicate glass) or co-fired ceramic (such as AlN, Al2O3), and the thickness of the core layer 1 is controlled to be 200μm to 600μm. The size of the core layer 1 is 5mm*5mm to 80mm*80mm.

[0088] S2: If Figure 4 As shown, the wafer is reconstructed. Specifically, the core layer 1 is fixed on the temporary carrier 3. Optionally, the core layer 1 is attached to the temporary carrier 3 at a certain distance (for example, a distance ≥ 0.1 mm), wherein the temporary carrier 3 and the core layer 1 are bonded by a temporary bonding layer 4. The temporary bonding layer 4 is a bonding material or a thermal peeling film. The temporary carrier 3 can be a stainless steel metal sheet, a glass carrier or a silicon carrier, etc.

[0089] S3: If Figure 5As shown, molding. Specifically, a molding layer 5 is prepared on a temporary carrier 3, and the molding layer 5 molds the core layer 1. It can be understood that the thickness of the molding layer 5 is greater than or equal to the thickness of the core layer 1, for example, the thickness of the molding layer 5 is 0.5 mm to 3.0 mm. Optionally, the molding layer 5 can be obtained by molding a molding compound (liquid molding compound or granular molding compound, etc.) through a molding process. As an example, the molding compound includes at least one of epoxy resin, polyimide, polyurethane and silicone.

[0090] S4: As Figure 6 As shown, debonding, i.e., removing the temporary carrier 3, is performed. Debonding is performed based on the material type of the temporary bonding layer 4 so that a portion of the core layer 1 is exposed to one side surface of the plastic encapsulation layer 5. As an example, the temporary bonding layer 4 is a bonding material and can be debonded by ultraviolet laser, mechanical means, or heating. The temporary bonding layer 4 is a thermal release film and can be debonded by heating.

[0091] S5: If Figure 7 As shown, a rewiring layer 2 is produced. Specifically, a wafer-level rewiring (RDL) process is used to prepare a rewiring layer 2 on the surface of one side of the plastic layer 5 that exposes the core layer 1, so that the rewiring layer 2 is connected to the core layer 1. A wafer-level rewiring process is used to deposit copper wires to obtain a first metal circuit layer 21, wherein the minimum line width / line spacing is ≤5μm, the surface roughness Rz is ≤0.05μm, and the thickness of the copper wire can be 3μm, 5μm or 7μm. A spin coating process is used to prepare a dielectric material into a dielectric layer 22, and the dielectric layer 22 is stacked with the first metal circuit layer 21 and together constitutes the rewiring layer 2. The dielectric material used to make the dielectric layer 22 can be a material such as PSPI or PBO. The maximum number of wiring layers of the rewiring layer 2 is 6P6M, where P represents the dielectric layer 22, that is, the dielectric layer, and M represents the metal layer, that is, the first metal circuit layer 21.

[0092] S6: Remove the plastic layer 5 to obtain the substrate 10. Figure 8 As shown, the back of the plastic encapsulation layer 5 is thinned. Specifically, the back of the plastic encapsulation layer 5 is ground and thinned so that the core layer 1 is exposed on the back of the plastic encapsulation layer 5. Here, the back of the plastic encapsulation layer 5 refers to the side surface of the plastic encapsulation layer 5 away from the redistribution layer 2. Figure 9 As shown, the substrate 10 is diced to obtain a single substrate 10. Specifically, the plastic encapsulation layer 5 is removed and the dielectric layer 22 is cut off by dicing, thereby obtaining a single substrate 10, which includes a core layer 1 and a redistribution layer 2.

[0093] Because the inorganic non-metallic material layer 11 in the core layer 1 of substrate 10 is made of inorganic non-metallic materials, during the preparation process of substrate 10, when the plastic encapsulation layer 5 is formed to encapsulate the core layer 1, the plastic encapsulation layer 5 and the core layer 1 are difficult to effectively bond with each other. This, in turn, affects the quality of the rewiring layer 2 when it is subsequently formed on the plastic encapsulation layer 5 using a wafer-level rewiring process. To address this issue, researchers performed surface treatment on the core layer 1. When the surface roughness of the core layer 1 was controlled within the range of 10nm to 1000nm, they found that the plastic encapsulation layer 5 and the core layer 1 could effectively bond together, thereby improving the quality of the rewiring layer 2. As an example, the surface roughness of the core layer 1 is 10nm, 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm. As a general rule of thumb, a greater surface roughness of the encapsulated object improves the bonding strength between the encapsulated object and the encapsulation material layer. However, in the embodiment of the present application, the excessive surface roughness of the core layer 1 is not conducive to the bonding of the plastic encapsulation layer 5 and the core layer 1. By performing surface treatment on the core layer 1 to flatten the surface of the core layer 1, the bonding effect of the plastic encapsulation layer 5 and the core layer 1 can be improved.

[0094] In some embodiments, after providing the core layer 1, the core layer 1 is further subjected to surface treatment so that the surface energy of the core layer 1 is greater than or equal to 50 mN / m. Combined with the surface flattening of the core layer 1, the bonding effect between the molding layer 5 and the core layer 1 can be further improved by increasing the surface energy of the core layer 1. It is speculated that this may be because after the surface energy of the core layer 1 is increased, the liquid molding material can be better spread on the surface of the core layer 1 during the molding process, reducing the generation of contact dead angles, thereby improving the bonding effect between the molding layer 5 and the core layer 1. As an example, the surface energy of the core layer 1 is 50 mN / m, 60 mN / m, 80 mN / m or 100 mN / m.

[0095] In some embodiments, the contact angle of the surface of the core layer 1 with deionized water is less than or equal to 10°. As the surface energy of the core layer 1 increases, the surface of the core layer 1 becomes hydrophilic, and deionized water easily spreads on the surface of the core layer 1, forming a smaller contact angle. Of course, the contact angle of the surface of the core layer 1 with deionized water can also be adjusted by changing the microscopic morphology of the surface of the core layer 1. As an example, the contact angle of the surface of the core layer 1 with deionized water is 1°, 5°, 6°, 7°, 8°, 9°, or 10°.

[0096] In some embodiments, surface treatment of the core layer 1 includes: chemically cleaning the surface of the core layer 1 with a saponifier solution; placing the cleaned core layer 1 in a plasma treatment chamber and cleaning it with nitrogen gas, etc.; applying radio frequency to perform plasma bombardment treatment on the surface of the core layer 1.

[0097] In some embodiments, see Figures 11 to 18 , step S5 specifically includes:

[0098] S51, such as Figures 11 to 13 As shown: corresponding to the side of the core layer 1 exposed by the plastic encapsulation layer 5, a first photoresist is coated on the plastic encapsulation layer 5, and the first photoresist is exposed, developed and cured to obtain a dielectric layer 22 with a first opening 23. Here, the first photoresist is used to prepare the dielectric layer 22, and the first photoresist can be selected according to the material of the final dielectric layer 22. As an example, the incoming material is a structure in which the core layer 1 is plastic encapsulated in the plastic encapsulation layer 5, and the incoming material is cleaned and dried; a coating machine is used to coat (for example, spin coating) a first photoresist (called a first initial glue layer 220) on the plastic encapsulation layer 5; an exposure machine and a mask are combined to expose the first photoresist, and the pattern of the mask is the same as or complementary to the pattern of the dielectric layer 22; a developing device is used to develop the first photoresist, and a portion of the first photoresist is removed, thereby obtaining a first opening 23; an oxygen-free curing furnace is used to cure the first photoresist to obtain the dielectric layer 22. This method of preparing the dielectric layer 22 by selecting a first photoresist and preparing the first opening 23 by combining the exposure and development process can not only improve the production accuracy of the first opening 23, but more importantly, it can effectively reduce the generation of impurities, thereby improving the current capacity of the first metal circuit layer 21 finally prepared, and is conducive to reducing the line width of the metal circuit in the first metal circuit layer 21.

[0099] In the related art, laser etching is used to etch the first opening 23 on the dielectric layer 22. This method will result in the generation of a large amount of etching debris. These debris are difficult to remove and remain on the surface of the dielectric layer 22. When the first metal circuit layer 21 is further produced on the surface of the dielectric layer 22, these debris will be mixed into the first metal circuit layer 21, thereby reducing the material purity of the first metal circuit layer 21, and further causing the current flow capacity of the first metal circuit layer 21 to be weakened. In order to ensure the current flow capacity of the first metal circuit layer 21, the line width of the metal circuit in the first metal circuit layer 21 must be increased.

[0100] S52, such as Figure 14As shown, a seed layer 6 is grown on the surface of dielectric layer 22 and within first opening 23. Because plastic encapsulation layer 5 is non-conductive, seed layer 6 is formed to ensure that first metal circuit layer 21 can be subsequently formed by electroplating. Seed layer 6 is a conductive metal layer, such as a copper layer, titanium layer, or nickel layer. As an example, seed layer 6 is formed by sputtering, covering the surface of dielectric layer 22 and the bottom and sidewall surfaces of first opening 23.

[0101] S53, such as Figure 15 and Figure 16 As shown: a second photoresist is coated on the surface of the seed layer 6, and the second photoresist is exposed, developed and cured to obtain a patterned adhesive layer 7 with a hollow area, and the seed layer 6 is exposed from the hollow area to the outside of the patterned adhesive layer 7. The second photoresist and the first photoresist can be the same material or different materials. As an example, a coating machine is used to coat the second photoresist (called the second initial adhesive layer 70) on the surface of the seed layer 6; an exposure machine and a mask plate are used to expose the second photoresist, and the pattern of the mask plate is the same as or complementary to the pattern of the patterned adhesive layer 7; a developing device is used to develop the second photoresist, remove part of the second photoresist, and use an oxygen-free curing furnace tube to cure the second photoresist to obtain a patterned adhesive layer 7 with a hollow area. Usually, the pattern of the patterned adhesive layer 7 is different from the pattern of the dielectric layer 22.

[0102] S54, such as Figure 17 As shown: metal is electroplated on the patterned adhesive layer 7 to obtain a patterned first metal circuit layer 21. During the electroplating process, the metal grows on the seed layer 6 corresponding to the hollow area of ​​the patterned adhesive layer 7, that is, the metal is deposited in the hollow area. Since the patterned adhesive layer 7 is non-conductive, metal will not be deposited on the surface of the patterned adhesive layer 7, thereby obtaining a patterned first metal circuit layer 21. Since the hollow area on the patterned adhesive layer 7 is formed by photolithography, the dimensional accuracy of the hollow area is high, and the size of the hollow area can also be made very small, thereby making the line width and line spacing of the metal circuits in the first metal circuit layer 21 very small, thereby achieving high-density wiring. In addition, the use of electroplating to prepare the first metal circuit layer 21 can make the overall material density of the first metal circuit layer 21 higher, which is also beneficial to improving the current carrying capacity of the first metal circuit layer 21.

[0103] S55, such as Figure 18 As shown, the patterned adhesive layer 7 and the seed layer 6 corresponding to the patterned adhesive layer 7 are removed to obtain the redistribution layer 2. It can be seen that the final redistribution layer 2 does not contain the patterned adhesive layer 7, which is only used to assist in the formation of the first metal circuit layer 21.

[0104] In some embodiments, the dielectric layer 22 and the first metal circuit layer 21 in the redistribution layer 2 are respectively multiple layers, and steps S51 to S55 can be repeated multiple times during the preparation process.

[0105] In some embodiments, the method for preparing the substrate 10 further includes:

[0106] S61: Before dicing, a rewiring layer 2 is formed on the back of the plastic layer 5. The steps for forming the rewiring layer 2 can refer to step S5 and will not be described in detail here. In the single substrate 10 thus prepared, the rewiring layer 2 is provided on both opposite sides of the core layer 1. Figure 10 If the method for preparing the substrate 10 does not include step S61, then in the single substrate 10 prepared, only one side of the core layer 1 is provided with the redistribution layer 2, as shown in FIG. Figure 1 shown.

[0107] Thirdly, see Figure 19 An embodiment of the present application provides a chip packaging structure 100 , including a silicon chip 20 and the above-mentioned substrate 10 , wherein the silicon chip 20 is disposed on the substrate 10 and connected to the redistribution layer 2 .

[0108] The chip packaging structure 100 includes the substrate 10 , and thus the chip packaging structure 100 has all the beneficial effects of the substrate 10 , which will not be described in detail herein.

[0109] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0110] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0112] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A substrate, characterized in that It comprises a core layer and a redistribution layer arranged on at least one side surface of the core layer, wherein the core layer comprises an inorganic non-metallic material layer, and the thermal expansion coefficient of the inorganic non-metallic material layer is 3ppm / °C to 8ppm / °C.

2. The substrate according to claim 1, wherein The rewiring layer includes a first metal circuit layer, the first metal circuit layer is electrically connected to the core layer, and the first metal circuit layer is a metal electrodeposition layer prepared by a wafer-level rewiring process.

3. The substrate according to claim 2, wherein The first metal circuit layer includes multiple metal circuits, the line width of the metal circuits is less than or equal to 5μm; and / or the line spacing of the metal circuits is less than or equal to 5μm; and / or the thickness of the first metal circuit layer is 3μm to 7μm; and / or the surface roughness of the first metal circuit layer is less than or equal to 0.5μm.

4. The substrate according to claim 2, wherein The redistribution layer also includes a dielectric layer, the first metal circuit layer includes a first body arranged on the side surface of the dielectric layer, a first opening is provided through the dielectric layer, the first metal circuit layer also includes a first conductive portion arranged in the first opening, and the first conductive portion is connected to the first body.

5. The substrate according to claim 4, wherein The number of the first metal circuit layers is less than or equal to 6 layers, and the number of the dielectric layers is less than or equal to 6 layers; and / or the material of the dielectric layer includes at least one of photosensitive polyimide, benzocyclobutene and polybenzoxazole; and / or the dielectric layer is a spin-coated layer; and / or the thickness of the dielectric layer is 5μm to 10μm.

6. The substrate according to claim 4, wherein The number of the first metal circuit layers and the number of the dielectric layers are both multiple layers, and the first metal circuit layers and the dielectric layers are alternately arranged, and two adjacent first metal circuit layers are electrically connected.

7. The substrate according to claim 2, wherein The core layer further includes a second metal circuit layer, which is disposed on the inorganic non-metallic material layer and is electrically connected to the first metal circuit layer.

8. The substrate according to claim 7, wherein The number of the inorganic non-metallic material layer and the second metal circuit layer are both multiple layers, the inorganic non-metallic material layer and the second metal circuit layer are alternately arranged, and the two adjacent layers of the second metal circuit layer are electrically connected; and / or, the second metal circuit layer includes a second body arranged on the side surface of the inorganic non-metallic material layer, a second opening is penetrated through the inorganic non-metallic material layer, the second metal circuit layer also includes a second conductive part, the second conductive part is arranged in the second opening, and the second conductive part is connected to the second body.

9. The substrate according to any one of claims 1 to 8, characterized in that The material of the inorganic non-metallic material layer includes at least one of borosilicate glass, AlN and Al2O3; and / or the thickness of the core layer is 200μm to 600μm; and / or the length of the core layer is 5mm to 80mm, and the width is 5mm to 80mm; and / or the redistribution layer is provided on the opposite surfaces of the core layer; and / or the surface roughness of the core layer is 10nm to 1000nm; and / or the surface energy of the core layer is greater than or equal to 50mN / m; and / or the contact angle of the surface of the core layer to deionized water is less than or equal to 10°.

10. A method for preparing a substrate, for preparing the substrate according to any one of claims 1 to 9, characterized in that: include: Providing a core layer, wherein the surface roughness of the core layer is 10 nm to 1000 nm; fixing the core layer on a temporary carrier; Preparing a plastic sealing layer on the temporary carrier, wherein the plastic sealing layer seals the core layer; Removing the temporary carrier plate so that a portion of the core layer is exposed to a side surface of the plastic packaging layer; A wafer-level rewiring process is used to prepare a rewiring layer on the surface of the plastic packaging layer on the side where the core layer is exposed, so that the rewiring layer is connected to the core layer; The plastic sealing layer is removed to obtain a substrate.

11. The method for preparing a substrate according to claim 10, wherein: The core layer is surface-treated so that the surface energy of the core layer is greater than or equal to 50 mN / m.

12. The method for preparing a substrate according to claim 10 or 11, characterized in that: The contact angle of the surface of the core layer to deionized water is less than or equal to 10°.

13. The method for preparing a substrate according to claim 10, wherein: The step of using a wafer-level rewiring process to prepare a rewiring layer on a surface of the plastic packaging layer on a side where the core layer is exposed, so that the rewiring layer is connected to the core layer, comprises: Corresponding to the side of the plastic encapsulation layer that exposes the core layer, coating a first photoresist on the plastic encapsulation layer, exposing, developing, and curing the first photoresist to obtain a dielectric layer having a first opening; growing a seed layer on the surface of the dielectric layer and in the first opening; Coating a second photoresist on the surface of the seed layer, and exposing, developing and curing the second photoresist to obtain a patterned adhesive layer; Electroplating metal on the patterned adhesive layer to obtain a patterned first metal circuit layer; The patterned adhesive layer and the seed layer corresponding to the patterned adhesive layer are removed to obtain a rewiring layer.

14. A chip packaging structure, characterized in that: The invention comprises a silicon chip and a substrate according to any one of claims 1 to 9 or a substrate prepared by the method for preparing a substrate according to any one of claims 10 to 13, wherein the silicon chip is arranged on the substrate and connected to the redistribution layer.

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