Semiconductor device, semiconductor wafer, preparation method and storage system
By using a high-K dielectric layer as the intermediate bonding layer in the semiconductor wafer and enhancing the interface peel strength, the problem of the buried oxide layer of the SOI wafer being unable to simultaneously meet the device performance and bonding process during the feature size miniaturization process is solved, achieving a balance between device performance improvement and process control.
Patent Information
- Application Number
- CN202410236160.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-09-05
AI Technical Summary
During the feature size miniaturization process of existing SOI wafers, the buried oxide layer cannot meet both device performance requirements and bonding process requirements.
A high-K dielectric layer is used as the intermediate bonding layer. A high-K dielectric layer is set between semiconductor substrates to enhance the interface peeling strength, and a connecting layer is set at a specific position to improve the interface strength to form a semiconductor wafer.
As the characteristic size of semiconductor wafers is miniaturized, the controllability of the bonding process is improved while meeting the device performance and process requirements.
Smart Images
Figure CN120603322A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and specifically to a semiconductor device, a semiconductor wafer and its preparation method, and a storage system. Background Art
[0002] Currently, SOI (Silicon-On-Insulator) wafers are increasingly being researched and applied due to their advantages, such as low power consumption and improved latch-up resistance. SOI wafers typically consist of a top semiconductor base layer, a middle buried oxide layer, and a bottom substrate. However, several challenges remain to be addressed during the SOI wafer fabrication process. Summary of the Invention
[0003] The present application provides a semiconductor wafer, a semiconductor device, and a storage system, aiming to solve the problem that as the feature size of the existing SOI wafer continues to shrink, its buried oxide layer cannot simultaneously meet the device performance requirements and bonding process requirements.
[0004] The present application provides a semiconductor wafer, comprising:
[0005] a first semiconductor substrate;
[0006] a second semiconductor substrate, disposed opposite to the first semiconductor substrate;
[0007] The high-K dielectric layer is disposed between the first semiconductor substrate and the second semiconductor substrate.
[0008] In some embodiments, the K value of the high-K dielectric layer is greater than or equal to 3.9.
[0009] In some embodiments, the material of the high-K dielectric layer includes one or more of hafnium oxide, aluminum oxide, lanthanum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
[0010] In some embodiments, a first connecting layer is further provided between the first semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the first connecting layer is greater than the interface peeling strength of the first semiconductor substrate; and / or,
[0011] A second connection layer is further provided between the second semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the second connection layer is greater than the interface peeling strength of the second semiconductor substrate.
[0012] In some embodiments, the material of the first connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride; and / or the material of the second connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride.
[0013] In some embodiments, a device layer is provided on a side of the first semiconductor substrate facing away from the high-K dielectric layer; and the second semiconductor substrate is a back gate layer.
[0014] The present invention also provides a method for preparing a semiconductor wafer, the method comprising:
[0015] providing a first semiconductor substrate and a second semiconductor substrate;
[0016] forming a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate;
[0017] Disposing the first semiconductor substrate and the second semiconductor substrate opposite to each other, so that the high-K dielectric layer is located between the first semiconductor substrate and the second semiconductor substrate;
[0018] The first semiconductor substrate is bonded to the second semiconductor substrate through the high-K dielectric layer.
[0019] In some embodiments, forming a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate includes:
[0020] forming a first connection layer on a side surface of the first semiconductor substrate, wherein the interface peeling strength of the first connection layer is greater than the interface peeling strength of the first semiconductor substrate;
[0021] The high-K dielectric layer is formed on a side of the first connecting layer facing away from the first semiconductor substrate.
[0022] In some embodiments, forming a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate further comprises:
[0023] A second connection layer is formed on a side surface of the second semiconductor substrate, and the interface peeling strength of the second connection layer is greater than the interface peeling strength of the second semiconductor substrate.
[0024] In some embodiments, forming a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate further comprises:
[0025] The high-K dielectric layer is formed on a side of the second connecting layer facing away from the second semiconductor substrate.
[0026] In some embodiments, the material of the first connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride; and / or the material of the second connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride.
[0027] In some embodiments, the K value of the high-K dielectric layer is greater than or equal to 3.9.
[0028] In some embodiments, the material of the high-K dielectric layer includes one or more of hafnium oxide, aluminum oxide, lanthanum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
[0029] In some embodiments, the method further comprises:
[0030] removing a portion of material on a side of the first semiconductor substrate facing away from the high-K dielectric layer to reduce the thickness of the first semiconductor substrate; or
[0031] A portion of the material of the second semiconductor substrate on a side away from the high-K dielectric layer is removed to reduce the thickness of the second semiconductor substrate.
[0032] An embodiment of the present application further provides a semiconductor device, comprising:
[0033] a first semiconductor substrate;
[0034] a high-K dielectric layer, disposed on a side surface of the first semiconductor substrate;
[0035] The transistor is disposed on a side of the high-K dielectric layer away from the first semiconductor substrate.
[0036] In some embodiments, a first connection layer is disposed between the first semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the first connection layer is greater than the interface peeling strength of the first semiconductor substrate.
[0037] In some embodiments, the transistor includes a second semiconductor substrate, a gate, and a gate dielectric layer. The second semiconductor substrate is arranged on the side of the high-K dielectric layer facing away from the first semiconductor substrate. The second semiconductor substrate includes a channel region, and a source region and a drain region connected to both sides of the channel region. The gate dielectric layer is arranged on the surface of the channel region, and the gate is located on the side of the gate dielectric layer facing away from the channel region.
[0038] In some embodiments, a second connection layer is disposed between the second semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the second connection layer is greater than the interface peeling strength of the second semiconductor substrate.
[0039] In some embodiments, the K value of the high-K dielectric layer is greater than or equal to 3.9.
[0040] An embodiment of the present application further provides a storage system, the storage system comprising a memory and a controller, the controller being coupled to the memory and configured to control the memory to store data;
[0041] Wherein, the memory includes the semiconductor device as described above, and the semiconductor device includes:
[0042] a first semiconductor substrate;
[0043] a high-K dielectric layer, disposed on a side surface of the first semiconductor substrate;
[0044] The transistor is disposed on a side of the high-K dielectric layer away from the first semiconductor substrate.
[0045] In some embodiments, a first connection layer is disposed between the first semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the first connection layer is greater than the interface peeling strength of the first semiconductor substrate.
[0046] Beneficial effects of the present application: Compared with the existing semiconductor wafer that uses a buried oxide layer as an intermediate bonding layer between the first semiconductor substrate and the second semiconductor substrate, the semiconductor wafer provided by the embodiment of the present application uses the first semiconductor substrate and the second semiconductor substrate as an intermediate bonding layer through a high-K dielectric layer. Compared with the buried oxide layer, the high-K dielectric layer has a higher physical thickness under the same equivalent oxygen thickness, and is easier to control the bonding process. Therefore, it can meet the performance improvement needs of the device after the characteristic size of the semiconductor wafer is miniaturized, and can also meet the bonding process requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0048] Figure 1 1 is a schematic structural diagram of an embodiment of a semiconductor wafer provided in an embodiment of the present application;
[0049] Figure 2 A schematic flow chart of an embodiment of a method for preparing a semiconductor wafer provided in an embodiment of the present application;
[0050] Figure 3 A schematic structural diagram of a semiconductor wafer fabrication method according to an embodiment of the present application after providing a first semiconductor substrate and a second semiconductor substrate;
[0051] Figure 4 A schematic diagram of a structure after forming a first connection layer on a first surface of a first semiconductor substrate and forming a second connection layer on a second surface of a second semiconductor substrate in one embodiment of a semiconductor wafer preparation method provided in an embodiment of the present application;
[0052] Figure 5 A schematic structural diagram of an embodiment of a semiconductor wafer preparation method provided in an embodiment of the present application after a high-K dielectric layer is formed on the second connection layer;
[0053] Figure 6 A schematic diagram of a structure after a first semiconductor substrate is bonded to a second semiconductor substrate via a high-K dielectric layer in one embodiment of a semiconductor wafer preparation method provided in an embodiment of the present application;
[0054] Figure 7 A schematic diagram of a structure after removing a portion of material on a side of a first semiconductor substrate facing away from a high-K dielectric layer to reduce the thickness of the first semiconductor substrate in one embodiment of a semiconductor wafer preparation method provided in an embodiment of the present application;
[0055] Figure 8 A schematic structural diagram of an embodiment of a semiconductor device provided in an embodiment of the present application;
[0056] Figure 9 A schematic structural diagram of another embodiment of a semiconductor device provided in an embodiment of the present application;
[0057] Figure 10 A schematic diagram of the structure of an embodiment of a storage system provided in an embodiment of the present application;
[0058] Figure 11 A schematic structural diagram of an embodiment of an electronic device provided in an embodiment of the present application.
[0059] Semiconductor wafer 10; first semiconductor substrate 11; first surface 12; first connection layer 13; third surface 14; second semiconductor substrate 21; second surface 22; second connection layer 23; high-K dielectric layer 31; device layer 41; semiconductor device 30; gate 32; gate dielectric layer 33; channel region 34; source region 35; drain region 36; protective layer 37; transistor 38. DETAILED DESCRIPTION
[0060] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.
[0061] SOI (Silicon-On-Insulator) wafers utilize a buried oxide layer between the top semiconductor substrate layer and the bottom substrate layer as a bonding interface, achieving dielectric isolation between integrated circuit components and eliminating the parasitic latch-up effect found in bulk silicon CMOS circuits. Integrated circuits fabricated using SOI wafers also offer advantages such as low parasitic capacitance, high integration density, high speed, simple processing, minimal short-channel effects, and suitability for low-voltage, low-power circuits. As SOI wafer feature sizes continue to shrink, the buried oxide layer thickness decreases to facilitate control of threshold voltage (Vt) and meet increasing device performance requirements, impacting the bonding process window.
[0062] In order to solve the above problems and enable the semiconductor wafer to simultaneously meet the device performance requirements and bonding process requirements after the feature size is miniaturized, an embodiment of the present application provides a semiconductor wafer.
[0063] Figure 1 This is a schematic structural diagram of an embodiment of a semiconductor wafer provided in an embodiment of the present application. Figure 1 As shown, the semiconductor wafer 10 includes a first semiconductor substrate 11, a second semiconductor substrate 21, and a high-K dielectric layer 31. The second semiconductor substrate 21 is arranged opposite to the first semiconductor substrate 11, and the high-K dielectric layer 31 is arranged between the first semiconductor substrate 11 and the second semiconductor substrate 21. The materials of the first semiconductor substrate 11 and the second semiconductor substrate 21 can be silicon or other semiconductor materials. The materials of the first semiconductor substrate 11 and the second semiconductor substrate 21 can be the same or different. The high-K dielectric layer 31 is a dielectric layer formed of a material with a high dielectric constant (also known as a Hi-k material).
[0064] Compared with the existing semiconductor wafer 10 that uses the buried oxide layer as the intermediate bonding layer between the first semiconductor substrate 11 and the second semiconductor substrate 21, the semiconductor wafer 10 provided in the embodiment of the present application uses the first semiconductor substrate 11 and the second semiconductor substrate 21 as the intermediate bonding layer through the high-K dielectric layer 31. The high-K dielectric layer 31 has a higher physical thickness than the buried oxide layer under the same equivalent oxygen thickness, and is easier to control the bonding process. Therefore, it can meet the device performance improvement requirements after the characteristic size of the semiconductor wafer 10 is miniaturized, and can also meet the bonding process requirements.
[0065] In some embodiments, the K value of the high-K dielectric layer 31 can be greater than or equal to 3.9. The K value of the high-K dielectric layer 31 can be 4, 4.1, 4.2, etc., and can be determined based on factors such as the material and thickness requirements of the high-K dielectric layer 31. Specifically, the material of the high-K dielectric layer 31 can include one or more materials with a K value greater than or equal to 3.9, such as hafnium oxide (Hf2O3), aluminum oxide (Al2O3), lanthanum oxide (La2O3), silicon nitride, silicon oxynitride, and silicon oxide.
[0066] In some embodiments, as Figure 1 As shown, a first connection layer 13 may be further provided between the first semiconductor substrate 11 and the high-K dielectric layer 31. The interface peeling strength of the first connection layer 13 is greater than the interface peeling strength of the first semiconductor substrate 11. Thus, the interface strength between the first semiconductor substrate 11 and the high-K dielectric layer 31 can be improved.
[0067] The material of the first connection layer 13 may include at least one of an oxide insulating material, silicon oxynitride (SiON), or titanium nitride (TiN). Specifically, the first semiconductor substrate 11 includes a first surface 12, which is disposed opposite the high-K dielectric layer 31. The first surface 12 of the first semiconductor substrate 11 may be oxidized to form the first connection layer 13.
[0068] Similarly, a second connection layer 23 may be provided between the second semiconductor substrate 21 and the high-K dielectric layer 31. The interface peeling strength of the second connection layer 23 is greater than the interface peeling strength of the second semiconductor substrate 21. Thus, the interface strength between the second semiconductor substrate 21 and the high-K dielectric layer 31 can be improved.
[0069] The second connection layer 23 is made of at least one of an oxide insulating material, silicon oxynitride (SiON), or titanium nitride (TiN). Specifically, the second semiconductor substrate 21 includes a second surface 22, which is disposed opposite the high-K dielectric layer 31. The second surface 22 of the second semiconductor substrate 21 can be oxidized to form the second connection layer 23.
[0070] It should be noted that the semiconductor wafer 10 can include both the first connection layer 13 and the second connection layer 23, or it can include only one of the first connection layer 13 and the second connection layer 23. Of course, the former can ensure that the interface strength between the first semiconductor substrate 11 and the second semiconductor substrate 21 and the high-K dielectric layer 31 is relatively high. In addition, the first semiconductor substrate 11 of the semiconductor wafer 10 can be directly bonded to the high-K dielectric layer 31, or the second semiconductor substrate 21 of the semiconductor wafer 10 can be directly bonded to the high-K dielectric layer 31.
[0071] In some embodiments, a device layer 41 may be provided on a side of the first semiconductor substrate 11 facing away from the high-K dielectric layer 31. Correspondingly, the second semiconductor substrate 21 serves as a back gate layer for applying a reverse voltage. Specifically, the first semiconductor substrate 11 includes a third surface 14 opposite the first surface 12, on which the device layer 41 is provided. The device layer 41 may include a plurality of transistors 38 or other circuit structures arranged in an array.
[0072] In order to better prepare the semiconductor wafer 10 provided in the embodiment of the present application, the embodiment of the present application also provides a semiconductor wafer preparation method. Figure 2 As shown, the semiconductor wafer preparation method may include steps S110 to S140, which are described in detail as follows:
[0073] S110 , providing a first semiconductor substrate 11 and a second semiconductor substrate 21 .
[0074] like Figure 3 As shown, the first semiconductor substrate 11 and the second semiconductor substrate 21 can be wafers made of semiconductor materials. The first semiconductor substrate 11 includes a first surface 12, which is located on one side of the thickness direction of the first semiconductor substrate 11. The second semiconductor substrate 21 includes a second surface 22, which is located on one side of the thickness direction of the second semiconductor substrate 21.
[0075] S120 , forming a high-K dielectric layer 31 on a side surface of at least one of the first semiconductor substrate 11 and the second semiconductor substrate 21 .
[0076] The K value of the high-K dielectric layer 31 is greater than or equal to 3.9. The K value of the high-K dielectric layer 31 can be 4, 4.1, 4.2, etc., and can be determined based on factors such as the material and thickness requirements of the high-K dielectric layer 31. Specifically, the material of the high-K dielectric layer 31 can include one or more materials with a K value greater than or equal to 3.9, such as hafnium oxide (Hf2O3), aluminum oxide (Al2O3), lanthanum oxide (La2O3), silicon nitride, silicon oxynitride, and silicon oxide.
[0077] In some embodiments, a high-K dielectric layer 31 may be formed on a side surface of at least one of the first semiconductor substrate 11 and the second semiconductor substrate 21 by deposition.
[0078] It should be noted that the high-K dielectric layer 31 can be directly or indirectly formed on the first surface 12 of the first semiconductor substrate 11 and the second surface 22 of the second semiconductor substrate 21, respectively. The high-K dielectric layer 31 can also be directly or indirectly formed only on the first surface 12 of the first semiconductor substrate 11, or the high-K dielectric layer 31 can be directly or indirectly formed only on the second surface 22 of the second semiconductor substrate 21.
[0079] In some embodiments, the step of forming the high-K dielectric layer 31 on the side surface of at least one of the first semiconductor substrate 11 and the second semiconductor substrate 21 may include step S121 and step S122, as detailed below:
[0080] S121 , forming a first connection layer 13 on a side surface of the first semiconductor substrate 11 , wherein the interface peeling strength of the first connection layer 13 is greater than the interface peeling strength of the first semiconductor substrate 11 .
[0081] Among them, such as Figure 4 As shown, a first connection layer 13 can be formed on the first surface 12 of the first semiconductor substrate 11. Specifically, the first surface 12 of the first semiconductor substrate 11 can be oxidized to form the first connection layer 13. The material of the first connection layer 13 can include at least one of an oxide insulating material, silicon oxynitride (SiON), or titanium nitride (TiN).
[0082] S122 , forming a high-K dielectric layer 31 on a side of the first connection layer 13 facing away from the first semiconductor substrate 11 .
[0083] By adding the first connection layer 13 between the first semiconductor substrate 11 and the high-K dielectric layer 31 and the interface peeling strength of the first connection layer 13 is greater than the interface peeling strength of the first semiconductor substrate 11, the interface strength between the first semiconductor substrate 11 and the high-K dielectric layer 31 can be improved.
[0084] In some embodiments, the step of forming a high-K dielectric layer 31 on the side of at least one of the first semiconductor substrate 11 and the second semiconductor substrate 21 may also include: forming a second connecting layer 23 on the side of the second semiconductor substrate 21, and the interface peeling strength of the second connecting layer 23 is greater than the interface peeling strength of the second semiconductor substrate 21.
[0085] like Figure 4As shown, by forming a second connection layer 23 having an interface peeling strength greater than that of the second semiconductor substrate 21 on the side of the second semiconductor substrate 21, when the side of the second connection layer 23 facing away from the second semiconductor substrate 21 is directly bonded to the high-K dielectric layer 31 provided on the first semiconductor substrate 11, the interface strength between the second semiconductor substrate 21 and the high-K dielectric layer 31 can be improved.
[0086] The second connection layer 23 may be formed on the second surface 22 of the second semiconductor substrate 21. Specifically, the second surface 22 of the second semiconductor substrate 21 may be oxidized to form the second connection layer 23. The material of the second connection layer 23 may include at least one of an oxide insulating material, silicon oxynitride (SiON), or titanium nitride (TiN).
[0087] In other embodiments, the step of forming the high-K dielectric layer 31 on the side of at least one of the first semiconductor substrate 11 and the second semiconductor substrate 21 may further include: forming the high-K dielectric layer 31 on the side of the second connection layer 23 facing away from the second semiconductor substrate 21. Thus, when the first semiconductor substrate 11 is not provided with the first connection layer 13, the high-K dielectric layer 31 provided on the second connection layer 23 can be used to bond with the first surface 12 of the first semiconductor substrate 11. When the first semiconductor substrate 11 is provided with the first connection layer 13, as shown in FIG. Figure 5 As shown, the high-K dielectric layer 31 provided on the second connection layer 23 can be used to bond to the side of the first connection layer 13 facing away from the first semiconductor substrate 11. When the first semiconductor substrate 11 is also provided with a high-K dielectric layer 31, the high-K dielectric layer 31 provided on the first semiconductor substrate 11 can be used to bond to the high-K dielectric layer 31 provided on the second semiconductor substrate 21.
[0088] S130 , disposing the first semiconductor substrate 11 and the second semiconductor substrate 21 opposite to each other, so that the high-K dielectric layer 31 is first located between the semiconductor substrate 11 and the second semiconductor substrate 21 .
[0089] like Figure 5 As shown, the side of the second semiconductor substrate 21 provided with the high-K dielectric layer 31 can be oriented toward the first surface 12 of the first semiconductor substrate 11, or the side of the first semiconductor substrate 11 provided with the high-K dielectric layer 31 can be oriented toward the second surface 22 of the second semiconductor substrate 21, so that the high-K dielectric layer 31 is located between the first semiconductor substrate 11 and the second semiconductor substrate 21.
[0090] S140 , bonding the first semiconductor substrate 11 to the second semiconductor substrate 21 through the high-K dielectric layer 31 .
[0091] Among them, such as Figure 6As shown, the surface of the high-K dielectric layer 31 facing away from the second semiconductor substrate 21 can be bonded to the surface of the first connection layer 13 facing away from the first semiconductor substrate 11, and the two bonded surfaces can be heated or processed in other ways to bond the high-K dielectric layer 31 to the first connection layer 13.
[0092] The semiconductor wafer preparation method provided in the embodiment of the present application is achieved by bonding the first semiconductor substrate 11 and the second semiconductor substrate 21 through a high-K dielectric layer 31 as an intermediate bonding layer. The high-K dielectric layer 31 has a higher physical thickness than the buried oxide layer under the same equivalent oxygen thickness, and is easier to control the bonding process. Therefore, it can meet the device performance improvement requirements after the characteristic size of the semiconductor wafer 10 is miniaturized, and can also meet the bonding process requirements.
[0093] In some embodiments, the semiconductor wafer preparation method may further include: Figure 7 As shown, a portion of the material on the side of the first semiconductor substrate 11 facing away from the high-K dielectric layer 31 is removed to reduce the thickness of the first semiconductor substrate 11. This allows a device layer 41 to be provided on the side of the first semiconductor substrate 11 facing away from the high-K dielectric layer 31. The device layer 41 may include a plurality of transistors 38 arranged in an array or other circuit structures. Correspondingly, the second semiconductor substrate 21 serves as a back gate layer for applying a reverse voltage.
[0094] Alternatively, the semiconductor wafer preparation method may also include removing a portion of the material on the side of the second semiconductor substrate 21 facing away from the high-K dielectric layer 31 to reduce the thickness of the second semiconductor substrate 21. This allows the device layer 41 to be provided on the side of the second semiconductor substrate 21 facing away from the high-K dielectric layer 31. Correspondingly, the first semiconductor substrate 11 serves as a back gate layer for applying a reverse voltage.
[0095] Part of the material on the side of the first semiconductor substrate 11 or the second semiconductor substrate 21 away from the high-K dielectric layer 31 can be removed by grinding / etching, or by smart shearing.
[0096] The present application also provides a semiconductor device. Figure 8 As shown, the semiconductor device 30 includes a first semiconductor substrate 11 , a high-K dielectric layer 31 and a transistor 38 , wherein the high-K dielectric layer 31 is disposed on a side of the first semiconductor substrate 11 , and the transistor 38 is disposed on a side of the high-K dielectric layer 31 away from the first semiconductor substrate 11 .
[0097] Since the high-K dielectric layer 31 serves as an intermediate bonding layer between the transistor 38 of the semiconductor device 30 and the first semiconductor substrate 11, the high-K dielectric layer 31 has a higher physical thickness than the buried oxide layer under the same equivalent oxygen thickness, and is easier to control for the bonding process. Therefore, after the characteristic size of the semiconductor device 30 is miniaturized, it can meet the performance improvement requirements of the transistor 38 while also meeting the bonding process requirements.
[0098] The K value of the high-K dielectric layer 31 is greater than or equal to 3.9. The K value of the high-K dielectric layer 31 can be 4, 4.1, 4.2, etc., and can be determined based on factors such as the material and thickness requirements of the high-K dielectric layer 31. Specifically, the material of the high-K dielectric layer 31 can include one or more materials with a K value greater than or equal to 3.9, such as hafnium oxide (Hf2O3), aluminum oxide (Al2O3), lanthanum oxide (La2O3), silicon nitride, silicon oxynitride, and silicon oxide.
[0099] In some embodiments, the transistor 38 includes a second semiconductor substrate 21, a gate 32, and a gate dielectric layer 33. The second semiconductor substrate 21 is disposed on a side of the high-K dielectric layer 31 facing away from the first semiconductor substrate 11. The second semiconductor substrate 21 includes a channel region 34, as well as a source region 35 and a drain region 36 connected to both sides of the channel region 34. The gate dielectric layer 33 is disposed on the surface of the channel region 34, and the gate 32 is located on a side of the gate dielectric layer 33 facing away from the channel region 34.
[0100] Among them, such as Figure 8 As shown, transistor 38 has a planar transistor structure. A gate dielectric layer 33 is provided on the surface of the channel region 34 on the side facing away from the high-k dielectric layer 31. Gate 32 is located on the side of gate dielectric layer 33 facing away from the channel region 34. Protective layers 37 are also provided on both sides of gate 32 along the distribution direction of source region 35 and drain region 36 to protect the side surfaces of gate 32.
[0101] Or, as Figure 9 As shown, transistor 38 is a fin field-effect transistor (Fin FET) structure. A gate dielectric layer 33 is disposed on the surface of the channel region 34 facing away from the high-k dielectric layer 31, as well as on two opposite sides of the channel region 34. A gate 32 is located on the side of the gate dielectric layer 33 facing away from the channel region 34 and is bonded to the surface of the high-k dielectric layer 31 facing away from the second semiconductor substrate 21.
[0102] In some embodiments, a first connection layer 13 may be provided between the first semiconductor substrate 11 and the high-K dielectric layer 31. The interfacial peeling strength of the first connection layer 13 is greater than the interfacial peeling strength of the first semiconductor substrate 11. This can improve the interfacial strength between the first semiconductor substrate 11 and the high-K dielectric layer 31.
[0103] The material of the first connection layer 13 may include at least one of an oxide insulating material, silicon oxynitride (SiON), or titanium nitride (TiN). Specifically, the first semiconductor substrate 11 includes a first surface 12, which is disposed opposite the high-K dielectric layer 31. The first surface 12 of the first semiconductor substrate 11 may be oxidized to form the first connection layer 13.
[0104] Similarly, a second connection layer 23 may be provided between the second semiconductor substrate 21 and the high-K dielectric layer 31. The interface peeling strength of the second connection layer 23 is greater than the interface peeling strength of the second semiconductor substrate 21. Thus, the interface strength between the second semiconductor substrate 21 and the high-K dielectric layer 31 can be improved.
[0105] The second connection layer 23 is made of at least one of an oxide insulating material, silicon oxynitride (SiON), or titanium nitride (TiN). Specifically, the second semiconductor substrate 21 includes a second surface 22, which is disposed opposite the high-K dielectric layer 31. The second surface 22 of the second semiconductor substrate 21 can be oxidized to form the second connection layer 23.
[0106] An embodiment of the present application also provides a memory, which includes a semiconductor device. The specific structure of the semiconductor device refers to the above embodiment. Since this memory adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.
[0107] See also Figure 10 The present invention also provides a storage system. The storage system 2 includes a controller 3 and a memory 4. The controller 3 is coupled to the memory 4 and is used to control the memory 4 to store data. The memory 4 includes the semiconductor device 30 in any of the above embodiments.
[0108] The semiconductor device 30 may be an array wafer memory device, or a device combined with a CMOS (Complementary Metal Oxide Semiconductor) peripheral circuit.
[0109] Specifically, the semiconductor device 30 can be stacked with the peripheral circuit or staggered with the peripheral circuit, which is not limited in this application. The peripheral circuit is electrically connected to the semiconductor device 30 to transmit signals to the semiconductor device 30. The peripheral circuit can be used for logical operations and to control and detect the switching state of each storage unit in the semiconductor device 30 through metal wiring to achieve data storage and reading.
[0110] Specifically, the memory 4 may be a DRAM memory.
[0111] Specifically, the controller 3 can control the memory 4 through the channel CH, and the memory 4 can perform operations based on the control of the controller 3 in response to a request from the host 6. The memory 4 can receive a command CMD and an address ADDR from the controller 3 through the channel CH and access an area selected from the memory cell array in response to the address. In other words, the memory 4 can perform an internal operation corresponding to the command on the area selected by the address.
[0112] In some embodiments, the storage system 2 can be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.
[0113] Specifically, the storage system 2 can be used in terminal products such as computers, televisions, set-top boxes, and vehicles.
[0114] See also Figure 11 The present application also provides an electronic device. The electronic device 5 includes a central processing unit 7 and the storage system 2 provided in the present application. Specifically, the electronic device 5 can be any device capable of storing data, such as a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device, or a mobile power bank.
[0115] The central processing unit 7 is used to exchange information and data with the storage system 2.
[0116] An electronic device provided in an embodiment of the present application has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided in an embodiment of the present application.
[0117] The above is a detailed introduction to the semiconductor wafer, semiconductor device and storage system provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A semiconductor wafer, characterized in that: The semiconductor wafer comprises: a first semiconductor substrate; a second semiconductor substrate, disposed opposite to the first semiconductor substrate; The high-K dielectric layer is disposed between the first semiconductor substrate and the second semiconductor substrate.
2. The semiconductor wafer according to claim 1, wherein The K value of the high-K dielectric layer is greater than or equal to 3.
9.
3. The semiconductor wafer according to claim 2, wherein: The material of the high-K dielectric layer includes one or more of hafnium oxide, aluminum oxide, lanthanum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
4. The semiconductor wafer according to claim 1, wherein A first connecting layer is further provided between the first semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the first connecting layer is greater than the interface peeling strength of the first semiconductor substrate; and / or, A second connection layer is further provided between the second semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the second connection layer is greater than the interface peeling strength of the second semiconductor substrate.
5. The semiconductor wafer according to claim 4, wherein The material of the first connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride; and / or the material of the second connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride.
6. The semiconductor wafer according to claim 1, wherein A device layer is provided on a side of the first semiconductor substrate facing away from the high-K dielectric layer; and the second semiconductor substrate is a back gate layer.
7. A method for preparing a semiconductor wafer, characterized in that: The method comprises: providing a first semiconductor substrate and a second semiconductor substrate; forming a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate; Disposing the first semiconductor substrate and the second semiconductor substrate opposite to each other so that the high-K dielectric layer is located between the first semiconductor substrate and the second semiconductor substrate; The first semiconductor substrate is bonded to the second semiconductor substrate through the high-K dielectric layer.
8. The method for preparing a semiconductor wafer according to claim 7, wherein: The step of forming a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate comprises: forming a first connection layer on a side surface of the first semiconductor substrate, wherein the interface peeling strength of the first connection layer is greater than the interface peeling strength of the first semiconductor substrate; The high-K dielectric layer is formed on a side of the first connecting layer facing away from the first semiconductor substrate.
9. The method for preparing a semiconductor wafer according to claim 8, wherein: The forming of a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate further comprises: A second connection layer is formed on a side surface of the second semiconductor substrate, and the interface peeling strength of the second connection layer is greater than the interface peeling strength of the second semiconductor substrate.
10. The method for preparing a semiconductor wafer according to claim 9, wherein: The forming of a high-K dielectric layer on a side surface of at least one of the first semiconductor substrate and the second semiconductor substrate further comprises: The high-K dielectric layer is formed on a side of the second connecting layer facing away from the second semiconductor substrate.
11. The method for preparing a semiconductor wafer according to claim 9, wherein: The material of the first connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride; and / or the material of the second connection layer includes at least one of an oxide insulating material, silicon oxynitride, or titanium nitride.
12. The method for preparing a semiconductor wafer according to claim 7, wherein: The K value of the high-K dielectric layer is greater than or equal to 3.
9.
13. The method for preparing a semiconductor wafer according to claim 12, wherein: The material of the high-K dielectric layer includes one or more of hafnium oxide, aluminum oxide, lanthanum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
14. The method for preparing a semiconductor wafer according to claim 7, wherein: The method further comprises: removing a portion of material on a side of the first semiconductor substrate facing away from the high-K dielectric layer to reduce the thickness of the first semiconductor substrate; or A portion of the material of the second semiconductor substrate on a side away from the high-K dielectric layer is removed to reduce the thickness of the second semiconductor substrate.
15. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor substrate; a high-K dielectric layer, disposed on a side surface of the first semiconductor substrate; The transistor is disposed on a side of the high-K dielectric layer away from the first semiconductor substrate.
16. The semiconductor device according to claim 15, wherein A first connection layer is provided between the first semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the first connection layer is greater than the interface peeling strength of the first semiconductor substrate.
17. The semiconductor device according to claim 15, wherein The transistor includes a second semiconductor substrate, a gate and a gate dielectric layer. The second semiconductor substrate is arranged on the side of the high-K dielectric layer away from the first semiconductor substrate. The second semiconductor substrate includes a channel region, and a source region and a drain region connected to both sides of the channel region. The gate dielectric layer is arranged on the surface of the channel region, and the gate is located on the side of the gate dielectric layer away from the channel region.
18. The semiconductor device according to claim 17, wherein A second connection layer is provided between the second semiconductor substrate and the high-K dielectric layer, and the interface peeling strength of the second connection layer is greater than the interface peeling strength of the second semiconductor substrate.
19. The semiconductor device according to claim 15, wherein The K value of the high-K dielectric layer is greater than or equal to 3.
9.
20. A storage system, characterized in that: The storage system includes a memory and a controller, wherein the controller is coupled to the memory and configured to control the memory to store data; Wherein, the memory comprises the semiconductor device according to any one of claims 15 to 19.