Dielectric isolation method in bipolar circuit chip preparation

Abstract

The invention discloses a dielectric isolation method in preparation of a bipolar circuit chip. The dielectric isolation method is characterized by comprising the following steps: S1, preparing a wafer; s2, forming a first oxide layer on the wafer silicon wafer; s3, preparing a first tank body; s4, etching the first groove body downwards in advance; s5, preparing a second tank body; s6, preparing a second oxide layer; s7, depositing a polycrystalline silicon layer on the second oxide layer; and 8, polishing the upper surface of the second oxide layer to flatten the surface of the second oxide layer. The method is simple and clear in step and convenient to implement, the leakage current and transconductance are not greatly degraded while the breakdown voltage is optimized and guaranteed to be improved, and the defect of transverse diffusion of the PN isolation junction under the large line width process condition is overcome.

Description

Technical Field

[0001] The present invention relates to the field of IC integrated circuit manufacturing process, and in particular to a dielectric isolation method in the preparation of a bipolar circuit chip. Background Art

[0002] In semiconductor technology, PN junctions are generally used for isolation. However, the breakdown voltage of a PN junction depends on the resistivity of the substrate. To increase the breakdown voltage and reduce isolation parasitic capacitance, wafers with high substrate resistivity are selected. However, if the resistivity is too high, the epitaxial layer will move toward the substrate during long-term isolation diffusion, prolonging the isolation time. Moreover, PN junction isolation has a capacitive effect, causing parasitic capacitance, resulting in capacitive coupling between the collector and substrate of the transistor, as well as between the collector region and the isolation island. Therefore, PN junction isolation is not applicable in high-frequency amplifiers and high-speed digital circuits. Summary of the Invention

[0003] The present invention aims to overcome the deficiencies in the prior art and provides a dielectric isolation method for preparing a bipolar circuit chip.

[0004] This application provides the following technical solutions: A dielectric isolation method for preparing a bipolar circuit chip, characterized in that it includes the following steps: S1, preparing a wafer; S2, pre-oxidizing the surface of the silicon wafer to form a silicon dioxide oxide layer, and depositing a TEOS dielectric layer on the oxide layer; S3, etching a first groove on the TEOS dielectric layer using positive photoresist exposure; S4, after photoresist removal and cleaning, continuing to etch the first groove downward through the oxide layer and extending into the silicon wafer layer to a certain depth; S5, further using positive photoresist exposure to etch a second groove on the silicon wafer on one side of the first groove; S6, etching the oxide layer and the TEOS dielectric layer using BOE, and then performing secondary oxidation on the exposed silicon wafer layer surface and the first and second grooves to form a second oxide layer; S7, depositing a polysilicon layer on the second oxide layer; S8. Polishing the upper surface of the second oxide layer using chemical mechanical polishing (CMP) to planarize the surface.

[0005] On the basis of the above technical solutions, the following further technical solutions can be provided: The wafer in S1 is a six-inch single-throw N <100> Silicon wafer.

[0006] The opening width of the first groove in S3 is 0.5-1 μm, the depth is less than or equal to ≤2.8 μm, and the etching is performed by dry etching.

[0007] The depth of the second groove body in step S5 is greater than the depth of the first groove body in step S3, and the opening width of the second groove body is less than 2 μm and the depth is greater than 6 μm.

[0008] Advantages of the invention: The present invention has simple steps and is easy to implement. By combining the isolation trench formed by two deep and shallow trenches with an oxide insulating layer and a polysilicon filling layer, the present invention optimizes and ensures that the breakdown voltage is improved while the leakage current and transconductance do not suffer significant degradation. The shortcomings of the lateral diffusion of the PN isolation junction under large line width process conditions are simplified, breaking through the complexity of the SOI full-dielectric isolation trench process and ensuring the flatness of the silicon surface morphology. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a schematic diagram after completing step S3; Figure 2 It is a schematic diagram after completing step S4; Figure 3 This is a schematic diagram after completing step S5; Figure 4 This is a schematic diagram after completing step S6; Figure 5 This is a schematic diagram after completing step S7; Figure 6 This is a schematic diagram after completing step S8. DETAILED DESCRIPTION

[0010] like Figure 1-6 As shown, a dielectric isolation method for preparing a bipolar circuit chip is characterized in that it includes the following steps: S1, preparing a wafer, the wafer is a six-inch single-throw N <100> Silicon wafer 1.

[0011] S2 . Pre-oxidize the surface of the silicon wafer 1 to form a silicon dioxide oxide layer 2 , and deposit a TEOS dielectric layer 3 on the oxide layer 2 .

[0012] S3. A first groove 4 is etched on the TEOS dielectric layer using a positive photoresist exposure method. The opening width of the first groove 4 is 0.5 μm, the thickness of the photoresist layer 7 is 1 μm, and the etching adopts a dry etching process.

[0013] S4. After the degumming and cleaning, the first groove body 4 is further etched downward to pass through the oxide layer and extend into the silicon wafer 1 to a certain depth. The etching depth is 0.8 μm±0.1 μm, so that the depth of the entire first groove body 4 is 2.5 μm.

[0014] S5. A positive photoresist exposure is performed again to etch a second groove 5 on the silicon wafer on the side of the first groove 4. The opening of the second groove 5 has a width of 1.2 μm and a depth of 8 μm. The resist layer 7 is 1.5 μm thick. Dry etching is used. During the photoresist application, the first groove 4 is filled with photoresist. The depth of the second groove 5 is greater than the depth of the first groove 4 in step S3.

[0015] S6, using BOE to etch away the oxide layer 2 and the TEOS dielectric layer 3, and then performing secondary oxidation on the exposed surface of the silicon wafer 1 and the surfaces of the first and second tanks to form a second oxide layer 6; S7, depositing a polysilicon layer 8 on the second oxide layer 6; S8. Polish the upper surface of the second oxide layer 6 to make its surface flat.

Claims

1. A dielectric isolation method for preparing a bipolar circuit chip, characterized by: It includes the following steps: S1, prepare a wafer; S2, pre-oxidize the surface of the silicon wafer to form a silicon dioxide oxide layer, and deposit a TEOS dielectric layer on the oxide layer; S3, using positive photoresist to etch a first groove on the TEOS dielectric layer; S4, after de-resist cleaning, continue to etch the first groove downward through the oxide layer and extend into the silicon wafer to a certain depth; S5, using positive photoresist to etch a second groove on the silicon wafer on one side of the first groove; S6, using BOE to etch away the oxide layer and TEOS dielectric layer, and then performing a secondary oxidation on the exposed silicon wafer surface and the first and second grooves to form a second oxide layer; S7, depositing a polysilicon layer on the second oxide layer; S8. Polishing the upper surface of the second oxide layer to make its surface flat.

2. The dielectric isolation method for preparing a bipolar circuit chip according to claim 1, characterized in that: The wafer in S1 is a six-inch single-throw N <100> Silicon wafer.

3. The dielectric isolation method for preparing a bipolar circuit chip according to claim 1, characterized in that: The opening width of the first groove in S3 is 0.5-1 μm, the depth is less than or equal to ≤2.8 μm, and the etching is performed by dry etching.

4. The dielectric isolation method for preparing a bipolar circuit chip according to claim 1, characterized in that: The depth of the second groove body in step S5 is greater than the depth of the first groove body in step S3.

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