Pulse charging and discharging circuit, system and method

Abstract

The embodiment of the invention discloses a pulse charging and discharging circuit, system and method, the pulse charging and discharging circuit comprises a power supply, an energy storage circuit, a charging and discharging circuit and a load which are cascaded in sequence, the energy storage circuit comprises a plurality of synchronous BUCK modules, and each synchronous BUCK module comprises a step-down branch composed of two MOS discrete devices and an energy storage inductor; the charging and discharging circuit comprises two brake choppers which are connected in parallel. By adopting the embodiment of the invention, the problems of low efficiency, poor heat dissipation capability, poor reliability and the like of a traditional high-power pulse current source which is controlled in a linear mode can be solved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a pulse charging and discharging circuit, system and method. Background Art

[0002] With the development of science and technology, lasers are being used more and more widely in various fields, such as ranging, guidance, radar, or communications. In order to improve the convenience of use, the pulse drive power supply of airborne lasers needs to be small in size, light in weight, and highly efficient. According to the power requirements of semiconductor lasers, high-quality pulse current waveforms have high requirements for rise and fall times in terms of dynamics. At the same time, in terms of stability, current ripple, overshoot, and reverse current are required to meet high standards. Traditional high-power pulse current sources use linear mode control, which has problems such as low efficiency, poor heat dissipation capacity, and poor reliability, making them difficult to use as efficient laser power supplies.

[0003] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0004] The embodiments of the present application provide a pulse charge and discharge circuit, system, and method, which can solve the problems of low efficiency, poor heat dissipation, and poor reliability of traditional high-power pulse current sources using linear mode control.

[0005] A first aspect of an embodiment of the present application provides a pulse charge and discharge circuit, which includes a power supply, an energy storage circuit, a charge and discharge circuit, and a load connected in cascade sequence. The energy storage circuit includes multiple synchronous BUCK modules, each of which includes a step-down branch consisting of two MOS discrete devices and an energy storage inductor; the charge and discharge circuit includes two parallel brake choppers.

[0006] Optionally, the drain of one of the MOS discrete devices in each synchronous BUCK module is connected to the positive electrode of the power supply, the source of one of the MOS discrete devices in each synchronous BUCK module is connected to the drain of another MOS discrete device in each synchronous BUCK module and one end of the energy storage inductor in each synchronous BUCK module, and the source of another MOS discrete device in each synchronous BUCK module is connected to the negative electrode of the power supply; the other ends of multiple energy storage inductors of multiple synchronous BUCK modules are connected.

[0007] Optionally, the multiple synchronous BUCK modules are connected to the energy storage circuit through a standardized interface in a modular plug-and-play manner.

[0008] Optionally, each brake chopper includes an IGBT module and a diode, wherein the positive pole of the diode included in one brake chopper is connected to the collector of the IGBT module included in one brake chopper and the positive pole of the power supply, the emitter of the IGBT module included in one brake chopper is connected to the emitter of the IGBT module included in another brake chopper and the negative pole of the diode included in another brake chopper, the negative pole of the diode included in one brake chopper is connected to the collector of the IGBT module included in another brake chopper through the load, and the positive pole of the diode included in the other brake chopper is connected to the negative pole of the power supply.

[0009] Optionally, when the IGBT module included in one brake chopper is in the on state and the IGBT module included in the other brake chopper is in the off state, and when one MOS discrete device is in the off state and the other MOS discrete device is in the on state, the power supply, the IGBT module included in one brake chopper, the energy storage inductor, and the other MOS discrete device constitute an energy storage circuit to charge the energy storage inductor.

[0010] Optionally, when the IGBT module included in one brake chopper is in the off state and the IGBT module included in the other brake chopper is in the on state, and when one MOS discrete device is in the off state and the other MOS discrete device is in the on state, the power supply, the diode included in one brake chopper, the load, the IGBT module included in the other brake chopper, the energy storage inductor, and the other MOS discrete device constitute a discharge circuit to discharge to the outside through the load.

[0011] Optionally, when the IGBT module included in one brake chopper and the IGBT module included in the other brake chopper are both in the off state, and one MOS discrete device is in the on state and the other MOS discrete device is in the off state, the energy storage inductor, one of the MOS discrete devices, the power supply, and the diode included in the other brake chopper constitute an energy feedback loop to feed back the energy stored in the energy storage inductor to the power supply.

[0012] A second aspect of the present application provides a pulse charge and discharge system, the pulse charge and discharge system comprising the pulse charge and discharge circuit and the control circuit according to the first aspect, the control circuit comprising a main control unit, an interleaved parallel synchronization control circuit and a charge and discharge timing control circuit; The main control unit is configured to receive user demand instructions and output them to the staggered parallel synchronization control circuit and the charge and discharge timing control circuit; The staggered parallel synchronous control circuit is configured to receive the user demand instruction and output a corresponding pulse width modulation signal to the energy storage circuit; The charge and discharge timing control circuit is configured to receive the user demand instruction and output a corresponding voltage signal to the charge and discharge circuit; The energy storage circuit and the charge-discharge circuit are configured to perform charge-discharge or energy feedback according to the pulse width modulation signal and the voltage signal.

[0013] Optionally, the pulse charge and discharge system further includes a protection circuit, which is electrically connected to the energy storage circuit and the charge and discharge circuit, and is used to provide overcurrent and high temperature protection to the energy storage circuit and the charge and discharge circuit; The protection circuit is configured to control the multiple synchronous BUCK modules to operate in reduced phases by adopting a fault-tolerant control strategy when an abnormality is detected, and the multiple synchronous BUCK modules include redundant synchronous BUCK modules.

[0014] A third aspect of the present application provides a pulse charge and discharge method, the method comprising: The main control unit receives user demand instructions and outputs them to the staggered parallel synchronization control circuit and the charge and discharge timing control circuit; The staggered parallel synchronous control circuit receives the user demand instruction and outputs a corresponding pulse width modulation signal to the energy storage circuit; The charge and discharge timing control circuit receives the user demand instruction and outputs a corresponding voltage signal to the charge and discharge circuit; The energy storage circuit and the charge-discharge circuit perform charge-discharge or energy feedback according to the pulse width modulation signal and the voltage signal.

[0015] The energy storage circuit of the pulse charge and discharge circuit provided by the present application includes a plurality of synchronous BUCK modules, each synchronous BUCK module includes a step-down branch composed of two MOS discrete devices and an energy storage inductor, which can reduce the ripple of the output pulse current, reduce the current and voltage stress of the device, and improve the power level and heat dissipation capacity of the power supply, thereby increasing the reliability of the power supply; at the same time, the modular design makes the output more flexible, the scalability is strong, and the fault is easy to replace; further, the use of two MOS discrete devices to form a BUCK module can reduce losses. The charge and discharge circuit of the pulse charge and discharge circuit provided by the present application includes two parallel brake choppers, which can reduce the influence of the backflow of the current on the charge and discharge.

[0016] The pulse charge and discharge system and method provided in this application belong to the same inventive concept and therefore have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of the structure of a pulse charge and discharge circuit provided by an embodiment of the present application is shown; Figure 2 A schematic diagram showing the structure of the energy storage process of a pulse charge and discharge circuit provided by one embodiment of the present application is shown; Figure 3 A schematic diagram showing the structure of the discharge process of a pulse charge and discharge circuit provided by one embodiment of the present application is shown; Figure 4 A schematic diagram showing the structure of the energy feedback process of the pulse charge and discharge circuit provided by one embodiment of the present application is shown; Figure 5 A schematic structural diagram of a pulse charge and discharge system provided in one embodiment of the present application is shown; Figure 6 A timing diagram of drive signals of various components in a pulse charge and discharge system provided by one embodiment of the present application is shown; Figure 7 A schematic diagram showing current changes of multiple BUCK modules and loads in various stages provided by an embodiment of the present application is shown; Figure 8 A flow chart of a pulse charge and discharge method provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] Please refer to Figure 1 , which shows a schematic diagram of the structure of a pulse charge and discharge circuit provided by one embodiment of the present application. The pulse charge and discharge circuit includes a power supply, an energy storage circuit, a charge and discharge circuit, and a load, which are connected in cascade. The energy storage circuit includes multiple synchronous buck modules, each of which includes a step-down branch consisting of two MOS discrete devices and an energy storage inductor. The charge and discharge circuit includes two parallel brake choppers.

[0021] The load may be composed of a semiconductor laser pump and a freewheeling diode.

[0022] It's important to note that the number of synchronous buck modules can be dynamically adjusted based on actual power requirements. It can be two, three, or even more groups, with no specific restrictions. Furthermore, the multiple synchronous buck modules can be divided into two groups: one for energy storage and the other for redundancy. Interleaving multiple synchronous buck modules in parallel effectively reduces output current ripple and minimizes device current and voltage stress. The redundant structure improves fault tolerance. When fault-tolerant control is employed, phase reduction can be implemented in the event of a fault (e.g., abnormal voltage, current, or temperature detection).

[0023] At the same time, the multiple synchronous BUCK modules can be connected to the energy storage circuit through a standardized interface in a modular plug-and-play manner, so that the BUCK module can be easily added or replaced with modules to achieve system function expansion.

[0024] The energy storage circuit of the pulse charge and discharge circuit provided by the present application includes a plurality of synchronous BUCK modules, each synchronous BUCK module includes a step-down branch composed of two MOS discrete devices and an energy storage inductor, which can reduce the ripple of the output pulse current, reduce the current and voltage stress of the device, and improve the power level and heat dissipation capacity of the power supply, thereby increasing the reliability of the power supply; at the same time, the modular design makes the output more flexible, the scalability is strong, and the fault is easy to replace; further, the use of two MOS discrete devices to form a BUCK module can reduce losses. The charge and discharge circuit of the pulse charge and discharge circuit provided by the present application includes two parallel brake choppers, which can reduce the influence of the backflow of the current on the charge and discharge.

[0025] Please continue to refer to Figure 1 Specifically, in this embodiment, the drain of one MOS discrete device S1 in each synchronous buck module is connected to the positive electrode of the power supply, the source of one MOS discrete device S1 in each synchronous buck module is connected to the drain of another MOS discrete device S2 in each synchronous buck module and one end of the energy storage inductor L in each synchronous buck module, and the source of another MOS discrete device S2 in each synchronous buck module is connected to the negative electrode of the power supply; the other ends of multiple energy storage inductors L in multiple synchronous buck modules are connected.

[0026] Preferably, in this embodiment, the MOS discrete devices all use third-generation semiconductor SiC devices, which can obtain a higher switching frequency and further reduce the ripple of the circuit output current pulse.

[0027] Please continue to refer to Figure 1Specifically, in this embodiment, each brake chopper P includes an IGBT module Q and a diode D, wherein the anode of the diode D1 included in one brake chopper P1 is connected to the collector of the IGBT module Q1 included in one brake chopper P1 and the positive electrode of the power supply, the emitter of the IGBT module Q1 included in one brake chopper P1 is connected to the emitter of the IGBT module Q2 included in another brake chopper P2 and the cathode of the diode D2 included in another brake chopper P2, the cathode of the diode D1 included in one brake chopper P1 is connected to the collector of the IGBT module Q2 included in another brake chopper P2 through the load, and the anode of the diode D2 included in another brake chopper P2 is connected to the negative electrode of the power supply.

[0028] Please refer to Figure 2-Figure 4 , which respectively show the structural schematic diagrams of the energy storage process, discharge process and feedback process of the pulse charge and discharge circuit provided by an embodiment of the present application.

[0029] like Figure 2 As shown, when the IGBT module Q1 included in one brake chopper P1 is in the on state and the IGBT module Q2 included in the other brake chopper P2 is in the off state, and when one MOS discrete device S1 is in the off state and the other MOS discrete device S2 is in the on state, the power supply, the IGBT module Q1 included in one brake chopper P1, the energy storage inductor, and the other MOS discrete device Q2 form an energy storage circuit to charge the energy storage inductor. The direction of current flow is as follows: Figure 2 As shown by the blue arrow in the figure.

[0030] like Figure 3 As shown, when the IGBT module Q1 included in one brake chopper P1 is in the off state and the IGBT module Q2 included in the other brake chopper P2 is in the on state, and when one MOS discrete device S1 is in the off state and the other MOS discrete device S2 is in the on state, the power supply, the diode D1 included in one brake chopper P1, the load, the IGBT module Q2 included in the other brake chopper P2, the energy storage inductor, and the other MOS discrete device Q2 form a discharge circuit to discharge to the outside through the load. The direction of current flow is as follows: Figure 3 As shown by the red arrow in .

[0031] like Figure 4As shown, when the IGBT module Q1 included in one brake chopper P1 and the IGBT module Q2 included in the other brake chopper P2 are both in the off state, and one MOS discrete device S1 is in the on state and the other MOS discrete device S2 is in the off state, the energy storage inductor, one MOS discrete device Q1, the power supply, and the diode D2 included in the other brake chopper P2 form an energy feedback loop to feed back the energy stored in the energy storage inductor to the power supply. The direction of current flow is as shown in FIG. Figure 4 As shown by the yellow arrow in the figure.

[0032] As can be seen from the previous description, in this embodiment, the energy storage circuit is formed by multiple groups of interleaved parallel BUCK circuits, each group of interleaved parallel BUCK circuits can output a maximum pulse current of 100A. The interleaved parallel technology of this application can effectively reduce the output current ripple.

[0033] In this embodiment, the IGBT module can facilitate the input of control signals, reduce the control difficulty, shorten the control time, ensure the synchronization of control, and avoid the turn-on delay problem caused by multiple IGBT discrete devices in parallel. In this embodiment, since the MOS discrete device is a low-power, high-frequency device and the IGBT module is a high-power, low-frequency device, this hybrid device structure can meet the needs of high-frequency and high-power scenarios, and facilitate PCB layout and heat dissipation. In addition, the use of hybrid devices can be applied to operation under different working conditions, which improves the scope of application and stability of the device. At high frequencies, the loss of SiC-MOSFET is small, and the Si-IGBT power module can operate stably under high current and high power.

[0034] Please refer to Figure 5 , which shows a schematic structural diagram of a pulse charge and discharge system provided by one embodiment of the present application. The pulse charge and discharge system includes the pulse charge and discharge circuit and the control circuit described in the first aspect, wherein the control circuit includes a main control unit, an interleaved parallel synchronization control circuit, and a charge and discharge timing control circuit; The main control unit is configured to receive user demand instructions and output them to the staggered parallel synchronization control circuit and the charge and discharge timing control circuit; The staggered parallel synchronous control circuit is configured to receive the user demand instruction and output a corresponding pulse width modulation signal to the energy storage circuit; The charge and discharge timing control circuit is configured to receive the user demand instruction and output a corresponding voltage signal to the charge and discharge circuit; The energy storage circuit and the charge-discharge circuit are configured to perform charge-discharge or energy feedback according to the pulse width modulation signal and the voltage signal.

[0035] The user demand instruction includes the load output current ripple signal size, load frequency, pulse width, and power. In this embodiment, the main control unit outputs the load output current ripple signal size in the user demand instruction to the staggered parallel synchronization control circuit, and the main control unit outputs the laser load frequency, pulse width, and power in the user demand instruction to the charge and discharge timing control circuit.

[0036] Those skilled in the art will appreciate that, in this embodiment, the main control unit, the interleaved parallel synchronous control circuit, and the charge and discharge timing control circuit only need to be electronic devices that can process data and generate corresponding digital signals. The main control unit, the interleaved parallel synchronous control circuit, and the charge and discharge timing control circuit are preferably implemented using a DSP (Digital Signal Processing) chip.

[0037] The control system in this application is composed of the main control unit, the interleaved parallel synchronous control circuit, and the charge-discharge timing control circuit. The distributed system has strong processing capabilities and high reliability. It uses multiple DSP embedded subsystems to form a distributed system, and the concurrency of the distributed system is used to achieve parallel processing of multiple DSPs, which can meet the requirements of multiple control tasks and real-time performance. In this embodiment, the main control unit, the interleaved parallel synchronous control circuit, and the charge-discharge timing control circuit can all be implemented using TMS320F2812. The specific implementation methods of the main control unit, the interleaved parallel synchronous control circuit, and the charge-discharge timing control circuit are not limited here.

[0038] In other embodiments, the main control unit, the staggered parallel synchronous control circuit and the charge and discharge timing control circuit can also be implemented by other devices with similar functions, such as MCU (Microcontroller Unit), MPU (Microprocessor Unit), FPGA (Field Programmable Gate Array) and other chips with data processing functions.

[0039] Exemplarily, the staggered parallel synchronous control circuit is configured to receive user demand instructions, and then convert the user instructions into digital signals to control the generation of pulse width modulation PWM signals, and the generated PWM signals are applied to the MOS discrete devices in the energy storage circuit; at the same time, the charge and discharge timing control circuit is configured to receive user demand instructions, and then convert the user instructions into digital signals and control the generation of voltage signals, and the generated voltage signals are applied to the IGBT module of the charge and discharge circuit.

[0040] Please refer to Figure 6 , Figure 6From top to bottom, the timing diagram of the control signals received by the IGBT module Q1 included in one brake chopper P1, the IGBT module Q2 included in another brake chopper P2, one MOS discrete device S1 in the staggered parallel BUCK circuit, and the other MOS discrete device S2 is shown in the figure. Figure 6 The working process of the pulse charge and discharge system proposed in this embodiment is briefly described below: In the first stage (i.e., the energy storage stage), when the IGBT module Q1 is turned on and Q2 is turned off through the control signal, staggered PWM drive signals are applied to the MOS discrete device S2 in multiple groups of staggered parallel buck circuits. S1 applies a PWM drive signal opposite to that of S2. The first stage can be understood as the process of the power supply charging the inductor L in multiple groups of staggered parallel synchronous buck circuits. For details, please refer to Figure 2 .

[0041] In the second stage (i.e., the discharge stage), when the IGBT module Q2 is turned on and Q1 is turned off by the control signal, staggered PWM drive signals are applied to the MOS discrete device S2 in the N groups of staggered parallel buck circuits, and S1 is applied with a PWM drive signal opposite to that of S2. The second stage can be understood as the discharge process of the inductor L in multiple groups of staggered parallel buck circuits. For details, please refer to Figure 3 .

[0042] In the third stage (i.e., the energy feedback stage), when the IGBT modules Q1 and Q2 are both in the off state through the control signal, a normally-on PWM signal is applied to the gate of the MOS discrete device S1 in the N groups of interleaved parallel buck circuits. The current stored in the inductor L in the multiple groups of interleaved parallel buck circuits flows back to the power supply through the diode D2 included in another brake chopper P2. The feedback energy saves resources to a certain extent. For details, please refer to Figure 4 .

[0043] Figure 7 A schematic diagram shows the current changes of multiple buck modules and loads in various stages according to one embodiment of the present application. It can be seen that during the energy storage phase, the current in each buck module increases, and no current flows through the load; during the discharge phase, the current in each buck module remains constant, and the load discharges with a constant current; during the energy regeneration phase, the current in each buck module decreases, and no current flows through the load.

[0044] Furthermore, considering that excessive current or high temperature may damage the circuit and load in actual applications, the system may also include a protection circuit electrically connected to the energy storage circuit and the charge-discharge circuit to provide overcurrent and high-temperature protection for the energy storage circuit and the charge-discharge circuit. Upon detecting an anomaly, the protection circuit is configured to employ a fault-tolerant control strategy to control the multiple synchronous buck modules, including redundant synchronous buck modules, to operate in reduced phase.

[0045] In this embodiment, the protection circuit can be further divided into an overvoltage protection circuit, an overcurrent protection circuit, and an overtemperature protection circuit. The overtemperature protection circuit is used to detect the temperature inside the MOS discrete device and the load, and automatically cut off the power supply when the temperature exceeds the set threshold to prevent the load from being damaged due to overheating. Devices with negative temperature coefficients, such as thermistors or transistors, can be used to detect temperature changes. When the temperature rises, the resistance or voltage of these devices will change, thereby triggering the protection mechanism. For example, a CMOS-based overtemperature protection circuit can be designed to shut down the system when the temperature reaches 138°C to protect the circuit, and resume normal operation when the temperature drops to 126°C. In addition, the overtemperature protection circuit may also include a hysteresis function to prevent the protection mechanism from being frequently turned on and off near the critical temperature, thereby reducing device losses.

[0046] Overcurrent protection automatically shuts off the power supply's output when the output current exceeds a certain limit, preventing damage to the power supply and load. Overcurrent protection can include short-circuit protection and overload protection. Short-circuit protection can utilize electromagnetic current trips or fuses. Overload protection utilizes thermal relays or time-delay electromagnetic current relays, which are commonly used as overload protection components. Overcurrent protection can be implemented in a variety of ways, including using comparators, current sensors, or specialized power MOSFETs to detect and limit current.

[0047] When overcurrent, overvoltage, or overtemperature occurs in the synchronous buck module, the fault-tolerant operation module can be activated to cut off the buck module in the faulty phase and operate in reduced phase.

[0048] Please refer to Figure 8 , which shows a flow chart of a pulse charge and discharge method provided by an embodiment of the present application. The method may include the following steps: Step 801: The main control unit receives a user demand instruction and outputs it to the staggered parallel synchronization control circuit and the charge and discharge timing control circuit; Step 802: The interleaved parallel synchronous control circuit receives the user demand instruction and outputs a corresponding pulse width modulation signal to the energy storage circuit; Step 803: The charge and discharge timing control circuit receives the user demand instruction and outputs a corresponding voltage signal to the charge and discharge circuit; Step 804: The energy storage circuit and the charge-discharge circuit perform charge-discharge or energy feedback according to the pulse width modulation signal and the voltage signal.

[0049] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of the present invention.

[0050] It can be understood that in the various implementation methods of this application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation method of this application.

[0051] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0052] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those commonly understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise.

[0053] It is understood that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or software instructions. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0054] It will be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0055] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0056] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0057] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0058] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0059] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0060] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various implementation methods of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0061] The above are only specific embodiments of the present application, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A pulse charge and discharge circuit, characterized in that: The pulse charge and discharge circuit includes a power supply, an energy storage circuit, a charge and discharge circuit, and a load connected in cascade sequence. The energy storage circuit includes multiple synchronous buck modules, each of which includes a step-down branch consisting of two MOS discrete devices and an energy storage inductor. The charge and discharge circuit includes two parallel-connected brake choppers.

2. The pulse charge and discharge circuit according to claim 1, characterized in that: The drain of one MOS discrete device in each synchronous buck module is connected to the positive electrode of the power supply, the source of one MOS discrete device in each synchronous buck module is connected to the drain of another MOS discrete device in each synchronous buck module and one end of the energy storage inductor in each synchronous buck module, and the source of another MOS discrete device in each synchronous buck module is connected to the negative electrode of the power supply; the other ends of multiple energy storage inductors of multiple synchronous buck modules are connected.

3. The pulse charge and discharge circuit according to claim 1, characterized in that: The multiple synchronous BUCK modules adopt a modular plug-and-play method and are connected to the energy storage circuit through a standardized interface.

4. The pulse charge and discharge circuit according to claim 2, characterized in that: Each brake chopper includes an IGBT module and a diode, wherein the anode of the diode included in one brake chopper is connected to the collector of the IGBT module included in one brake chopper and the positive electrode of the power supply, the emitter of the IGBT module included in one brake chopper is connected to the emitter of the IGBT module included in another brake chopper and the cathode of the diode included in the other brake chopper, the cathode of the diode included in one brake chopper is connected to the collector of the IGBT module included in the other brake chopper through the load, and the anode of the diode included in the other brake chopper is connected to the negative electrode of the power supply.

5. The pulse charge and discharge circuit according to claim 4, characterized in that: When the IGBT module included in one of the brake choppers is in the on state and the IGBT module included in the other brake chopper is in the off state, and when one of the MOS discrete devices is in the off state and the other MOS discrete device is in the on state, the power supply, the IGBT module included in one of the brake choppers, the energy storage inductor, and the other MOS discrete device form an energy storage circuit to charge the energy storage inductor.

6. The pulse charge and discharge circuit according to claim 4, characterized in that: When the IGBT module included in one of the brake choppers is in the off state and the IGBT module included in the other brake chopper is in the on state, and when one of the MOS discrete devices is in the off state and the other MOS discrete device is in the on state, the power supply, the diode included in one of the brake choppers, the load, the IGBT module included in the other brake chopper, the energy storage inductor, and the other MOS discrete device form a discharge circuit to discharge to the outside through the load.

7. The pulse charge and discharge circuit according to claim 4, characterized in that: When the IGBT modules included in one brake chopper and the IGBT module included in the other brake chopper are both in the off state, and one MOS discrete device is in the on state and the other MOS discrete device is in the off state, the energy storage inductor, one of the MOS discrete devices, the power supply, and the diode included in the other brake chopper form an energy feedback loop to feed back the energy stored in the energy storage inductor to the power supply.

8. A pulse charge and discharge system, characterized in that: The pulse charge and discharge system comprises the pulse charge and discharge circuit and the control circuit according to claim 3, wherein the control circuit comprises a main control unit, an interleaved parallel synchronization control circuit and a charge and discharge timing control circuit; The main control unit is configured to receive user demand instructions and output them to the staggered parallel synchronization control circuit and the charge and discharge timing control circuit; The staggered parallel synchronous control circuit is configured to receive the user demand instruction and output a corresponding pulse width modulation signal to the energy storage circuit; The charge and discharge timing control circuit is configured to receive the user demand instruction and output a corresponding voltage signal to the charge and discharge circuit; The energy storage circuit and the charge-discharge circuit are configured to perform charge-discharge or energy feedback according to the pulse width modulation signal and the voltage signal.

9. The pulse charge and discharge system according to claim 8, characterized in that: The pulse charge and discharge system further includes a protection circuit, which is electrically connected to the energy storage circuit and the charge and discharge circuit, and is used to provide overcurrent and high temperature protection to the energy storage circuit and the charge and discharge circuit; The protection circuit is configured to control the multiple synchronous BUCK modules to operate in reduced phases by adopting a fault-tolerant control strategy when an abnormality is detected, and the multiple synchronous BUCK modules include redundant synchronous BUCK modules.

10. A pulse charge and discharge method, characterized in that: The method comprises: The main control unit receives user demand instructions and outputs them to the staggered parallel synchronization control circuit and the charge and discharge timing control circuit; The staggered parallel synchronous control circuit receives the user demand instruction and outputs a corresponding pulse width modulation signal to the energy storage circuit; The charge and discharge timing control circuit receives the user demand instruction and outputs a corresponding voltage signal to the charge and discharge circuit; The energy storage circuit and the charge-discharge circuit perform charge-discharge or energy feedback according to the pulse width modulation signal and the voltage signal.

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