Grid voltage bootstrapped switch circuit with compensation and ADC

Abstract

The invention discloses a grid voltage bootstrapped switch circuit with compensation and an ADC, and belongs to the technical field of integrated circuits. The circuit comprises a compensation charge pump circuit and a grid voltage bootstrapped switch circuit. A charge pump branch power supply end in the grid voltage bootstrap switch circuit is connected to an output compensation voltage end of the compensation charge pump circuit; when the input clock signal CLK1 is low and the input clock signal CLK2 is high in level, the power supply end of the charge pump branch is switched off, and the capacitor in the charge pump circuit is compensated for charging; when the level of the CLK1 is high and the level of the CLK2 is low, the power supply end of the charge pump branch is switched on, a bootstrap capacitor in the grid voltage bootstrap switch circuit is charged, and the Vboost provides compensation voltage. The compensation charge pump circuit provides higher power supply voltage for the grid voltage bootstrap switch, grid voltage drop of the sampling switch tube caused by parasitic capacitance at the positive end of the bootstrap capacitor can be compensated back, input parasitic capacitance is reduced, on-resistance of the sampling switch tube is reduced, and sampling linearity is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a gate voltage bootstrap switch circuit with compensation and an ADC. Background Art

[0002] With the rapid development of semiconductor technology, high-speed, high-precision ADCs have been widely used in the communications field, with pipeline ADCs being one of them. Switching circuits are widely used in these applications. As the requirements for speed and accuracy continue to increase, switching circuits are required to have low on-resistance, high precision, and high speed.

[0003] Due to the distortion of the sampling signal caused by the nonlinear conduction of the MOS switch, it is necessary to use bootstrap switching technology to achieve high-precision sampling in high sampling accuracy.

[0004] Conventional gate voltage bootstrap switches such as Figure 1 As shown in the figure, the source of the sampling switch tube MN7 is connected to the input signal Vin, and the gate is connected to the positive terminal of the bootstrap capacitor C3 through the MP1 tube. The basic idea of ​​the gate voltage bootstrap switch is to charge the bootstrap capacitor C3 in the holding phase, and connect the bootstrap capacitor across the gate and source of the sampling switch tube in the sampling phase to ensure that the gate-source voltage remains stable.

[0005] However, due to parasitic issues in conventional bootstrap switching circuits, the gate voltage of the sampling switch tube can be lower than expected. To achieve high linearity in gate voltage bootstrap switching, compensation for the clock feedthrough effect generated by the sampling switch tube MN7 or the substrate bias effect of the sampling switch tube MN7 is generally adopted to improve the linearity of the sampling switch tube. However, this does not address the reduced gate voltage of the sampling switch tube MN7 caused by the parasitic capacitance at the positive terminal of the bootstrap capacitor C3 during the sampling phase. Since the on-resistance is proportional to the gate-source voltage, the reduced gate voltage increases the on-resistance of the sampling switch tube MN7, thereby reducing the sampling linearity of the sampling switch tube. Summary of the Invention

[0006] The present invention aims to provide a gate voltage bootstrap switch circuit and ADC with compensation. By introducing a compensation charge pump circuit to compensate the gate voltage of the sampling switch tube, the gate voltage drop of the sampling switch tube caused by parasitic capacitance in the traditional gate voltage bootstrap switch can be compensated, thereby greatly reducing the on-resistance of the sampling switch and improving the linearity of the sampling switch.

[0007] In one aspect, the present invention provides a gate voltage bootstrap switch circuit with compensation, comprising a compensation charge pump circuit and a gate voltage bootstrap switch circuit;

[0008] The compensation charge pump circuit includes an NMOS transistor MN8, an NMOS transistor MN9, a PMOS transistor MP4, a PMOS transistor MP5, a capacitor C4, and a capacitor C5; the source of the NMOS transistor MN8 and the source of the NMOS transistor MN9 are connected to the input compensation bias voltage terminal VB; the gate of the NMOS transistor MN8 is connected to the gate of the PMOS transistor MP4, the drain of the NMOS transistor MN9, the drain of the PMOS transistor MP5, the positive end of the capacitor C5, and the power supply VDD; the drain of the NMOS transistor MN8 is connected to the drain of the PMOS transistor MP4, the gate of the NMOS transistor MN9, the gate of the PMOS transistor MP5, the positive end of the capacitor C4, and the power supply VDD; the negative end of the capacitor C4 is connected to the input clock signal terminal CLK2, and the negative end of the capacitor C5 is connected to the input clock signal terminal CLK1; the source of the PMOS transistor MP4 and the source of the PMOS transistor MP5 are connected to the output compensation voltage terminal V boost connect;

[0009] The power supply terminal of the charge pump branch in the gate voltage bootstrap switch circuit is connected to the output compensation voltage terminal V of the compensation charge pump circuit boost superior;

[0010] When the input clock signal terminal CLK1 is low and the input clock signal terminal CLK2 is high, the charge pump branch power supply terminal in the gate voltage bootstrap switch circuit is turned off. At this time, the capacitor C4 raises the drain voltage of the NMOS tube MN8 to V DD +VB turns on NMOS transistor MN9 to charge capacitor C5;

[0011] When the input clock signal terminal CLK1 is at a high level and the input clock signal terminal CLK2 is at a low level, the charge pump branch power supply terminal in the gate voltage bootstrap switch circuit is turned on, and the bootstrap capacitor in the gate voltage bootstrap switch circuit is charged. The output terminal V boost Provides a voltage higher than the supply voltage V DD Compensation voltage V DD +ΔV, where ΔV is the compensated voltage.

[0012] Furthermore, the signal clock phases of the input clock signal terminal CLK1 and the input clock signal terminal CLK2 are opposite.

[0013] Furthermore, the output terminal V boost Provided higher than the supply voltage V DD The compensation voltage is , satisfying the following formula:

[0014] (1-3)

[0015] Among them, V BThe fixed adjustable voltage signal provided by the input compensation bias voltage terminal VB, C3 is the capacitance of the bootstrap capacitor in the gate voltage bootstrap switch circuit, C5 is the capacitance of the capacitor C5, C p is the parasitic capacitance of the charge pump branch power supply terminal in the gate voltage bootstrap circuit, V DD is the power supply voltage.

[0016] Furthermore, the gate voltage bootstrap switch circuit includes NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, PMOS transistors MP1, MP2, MP3, capacitors C1, C2, C3, transmission gates TG1, and TG2; NMOS transistor MN7 is a sampling switch transistor, and the drain of NMOS transistor MN7 is the output signal terminal Vout of the gate voltage bootstrap switch circuit; the gate voltage bootstrap switch circuit input signal terminal Vin is They are respectively connected to the source of NMOS transistor MN7, one end of transmission gate TG1, and one end of transmission gate TG2, wherein the other end of transmission gate TG1 is connected to the drain of NMOS transistor MN6 and the negative end of capacitor C3; the other end of transmission gate TG2 is connected to the drain of PMOS transistor MP2 and the gate of PMOS transistor MP1; the gate of NMOS transistor MN6 is connected to the input clock signal terminal CLK1, and the source is grounded; transmission gates TG1 and TG2 both use the signals of input clock signal terminals CLK1 and input clock signal terminals CLK2 as gate control signals; the positive end of capacitor C3 is connected to the positive end of NMOS transistor MN6 The source of the NMOS transistor MN3 and the source of the PMOS transistor MP1 are defined as the node X; the drain of the NMOS transistor MN3, the drain of the NMOS transistor MN1, the drain of the NMOS transistor MN2, and the source of the PMOS transistor MP2 are connected to the power supply VDD; the gate of the NMOS transistor MN3 is connected to the source of the NMOS transistor MN2, the gate of the NMOS transistor MN1, and the positive terminal of the capacitor C2; the gate of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1 and the positive terminal of the capacitor C1; the input clock signal terminal CLK1 is connected to the negative terminal of the capacitor C2 after passing through the inverter, and the input clock signal terminal C LK2 is connected to the negative terminal of capacitor C1 after passing through an inverter; the drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN4 and the gate of NMOS transistor MN7; the gate of PMOS transistor MP2 is connected to the input clock signal terminal CLK2; the gate of NMOS transistor MN4 is connected to the source of PMOS transistor MP3 and power supply VDD, the source of NMOS transistor MN4 is connected to the drain of PMOS transistor MP3 and the drain of NMOS transistor MN5, the gate of PMOS transistor MP3 and the gate of NMOS transistor MN5 are connected to the input clock signal terminal CLK1, and the source of NMOS transistor MN5 is grounded.

[0017] Furthermore, the voltage Vx at the node X when the sampling switch MN7 is turned on is expressed as follows:

[0018] (1-4)

[0019] Among them, V in It is the input signal voltage of the gate voltage bootstrap switch circuit.

[0020] On the other hand, the present invention further provides an ADC comprising the above-mentioned gate voltage bootstrap switch circuit with compensation.

[0021] The beneficial effects of the gate voltage bootstrap switch circuit with compensation and the ADC of the present invention are as follows:

[0022] The present invention's compensated gate voltage bootstrap switch circuit and ADC utilize a compensating charge pump circuit to provide a higher power supply voltage to the charge pump branch in the gate voltage bootstrap switch circuit. This compensates for the gate voltage drop caused by parasitic capacitance in conventional gate voltage bootstrap switches, significantly reducing the on-resistance of the sampling switch and improving its linearity. The charge pump branch in the gate voltage bootstrap switch circuit eliminates the need for a larger capacitor to increase the gate voltage of the sampling switch, thereby reducing input parasitic capacitance and enabling applications in high-speed, high-precision ADCs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of a traditional gate voltage bootstrap switch circuit.

[0024] Figure 2 4 is a schematic diagram of a compensation charge pump circuit according to an embodiment of the present invention.

[0025] Figure 3 2 is a schematic diagram of clock phases according to an embodiment of the present invention.

[0026] Figure 4 1 is a circuit diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be described in further detail below with reference to the embodiments and accompanying drawings.

[0028] One embodiment of the present invention provides a gate voltage bootstrap switch circuit with compensation. This circuit incorporates a compensating charge pump circuit to compensate for the gate voltage drop of the sampling switch caused by parasitic capacitance at the positive terminal of the bootstrap capacitor in conventional gate voltage bootstrap switches. This significantly reduces the on-resistance of the sampling switch and improves its sampling linearity.

[0029] like Figure 1As shown, a conventional gate-voltage bootstrap switch circuit includes NMOS transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, PMOS transistors MP1, MP2, MP3, capacitors C1, C2, C3, transmission gates TG1, and TG2. NMOS transistor MN7 is a sampling switch transistor, and its drain serves as the gate-voltage bootstrap switch circuit output signal terminal Vout. The gate-voltage bootstrap switch circuit input signal terminal Vin is connected to the source of NMOS transistor MN7, one end of transmission gate TG1, and one end of transmission gate TG2, respectively. The other end of transmission gate TG1 is connected to the drain of NMOS transistor MN6 and the negative end of capacitor C3. The other end of transmission gate TG2 is connected to the drain of PMOS transistor MP2 and the gate of PMOS transistor MP1. The gate of NMOS transistor MN6 is connected to the input clock signal terminal CLK1, and its source is grounded. The signal clock phases of the input clock signal terminal CLK1 and the input clock signal terminal CLK2 are opposite, such as Figure 2 As shown. Both transmission gates TG1 and TG2 use the signals from input clock signal terminals CLK1 and CLK2 as gate control signals. The positive terminal of capacitor C3 is connected to the source of NMOS transistor MN3 and the source of PMOS transistor MP1, defining the source of NMOS transistor MN3 as node X. The drain of NMOS transistor MN3, the drain of NMOS transistor MN1, the drain of NMOS transistor MN2, and the source of PMOS transistor MP2 are connected to power supply VDD. The gate of NMOS transistor MN3 is connected to the source of NMOS transistor MN2, the gate of NMOS transistor MN1, and the positive terminal of capacitor C2. The gate of NMOS transistor MN2 is connected to the source of NMOS transistor MN1 and the positive terminal of capacitor C1. The input clock signal terminal CLK1 is connected to the negative terminal of capacitor C2 after an inverter, and the input clock signal terminal CLK2 is connected to the negative terminal of capacitor C1 after an inverter. The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN4 and the gate of NMOS transistor MN7. The gate of the PMOS transistor MP2 is connected to the input clock signal terminal CLK2. The gate of the NMOS transistor MN4 is connected to the source of the PMOS transistor MP3 and the power supply VDD. The source of the NMOS transistor MN4 is connected to the drain of the PMOS transistor MP3 and the drain of the NMOS transistor MN5. The gates of the PMOS transistor MP3 and the NMOS transistor MN5 are connected to the input clock signal terminal CLK1. The source of the NMOS transistor MN5 is grounded.

[0030] The parasitic capacitance of node X is Cp, which mainly comes from the gate capacitance Cg of the sampling switch tube MN7. It can be deduced that when the input clock signal terminal CLK1 is at a high level, the voltage Vx of node X when the sampling switch tube MN7 is turned on is as follows:

[0031] (1-1)

[0032] Among them, V DD is the power supply voltage, V in is the voltage at the input signal terminal of the gate voltage bootstrap switch circuit, C3 is the capacitance of the bootstrap capacitor C3, and Cp is the parasitic capacitance of node X.

[0033] The gate voltage bootstrap switch circuit with compensation in this embodiment uses a compensation charge pump circuit to provide a stable voltage V when the input clock signal terminal CLK1 is at a high level. boost .like Figure 3 As shown, the compensation charge pump circuit includes an NMOS transistor MN8, an NMOS transistor MN9, a PMOS transistor MP4, a PMOS transistor MP5, a capacitor C4, and a capacitor C5. The source of the NMOS transistor MN8 and the source of the NMOS transistor MN9 are connected to the input compensation bias voltage terminal VB. The gate of the NMOS transistor MN8 is connected to the gate of the PMOS transistor MP4, the drain of the NMOS transistor MN9, the drain of the PMOS transistor MP5, the positive terminal of the capacitor C5, and the power supply VDD. The drain of the NMOS transistor MN8 is connected to the drain of the PMOS transistor MP4, the gate of the NMOS transistor MN9, the gate of the PMOS transistor MP5, the positive terminal of the capacitor C4, and the power supply VDD. The negative terminal of the capacitor C4 is connected to the input clock signal terminal CLK2, and the negative terminal of the capacitor C5 is connected to the input clock signal terminal CLK1. The source of the PMOS transistor MP4 and the source of the PMOS transistor MP5 are connected to the output compensation voltage terminal V boost Output compensation voltage terminal V boost The voltage is as follows:

[0034] (1-2)

[0035] Where V B A fixed adjustable voltage signal is provided to the input compensation bias voltage terminal VB.

[0036] When the input clock signal terminal CLK1 is at a low level and the input clock signal terminal CLK2 is at a high level, the NMOS tube MN3 is turned off. At this time, the capacitor C4 is only used to raise the drain voltage of the NMOS tube MN8 to V DD +VB turns on the NMOS transistor MN9 to charge the capacitor C5.

[0037] like Figure 4 As shown, the charge pump branch power supply terminal (i.e., the drain of NMOS tube MN3) in the gate voltage bootstrap switch circuit is connected to Figure 3 The output compensation voltage terminal V of the compensation charge pump circuit shown boost On, provide a voltage higher than the power supply V DD The voltage V DD+ΔV, where ΔV is the compensation voltage. The compensation voltage ΔV of the charge pump circuit can be adjusted by inputting the compensation bias voltage terminal VB. According to the law of charge conservation, after being connected to the drain of the NMOS tube MN3, V boost The designed value cannot be reached, but is determined by the values ​​of capacitor C5, capacitor C3, and parasitic capacitance Cp of node X.

[0038] When the input clock signal terminal CLK1 is at a high level and the input clock signal terminal CLK2 is at a low level, the NMOS tube MN3 is turned on, and the capacitor C3 is charged at this time to compensate the charge pump circuit output terminal V boost The available compensation voltage is , satisfying the following formula:

[0039] (1-3)

[0040] Among them, V B The fixed adjustable voltage signal provided by the input compensation bias voltage terminal VB, C3 is the capacitance value of capacitor C3, C5 is the capacitance value of capacitor C5, C p is the parasitic capacitance of node X, V DD is the power supply voltage.

[0041] Then the voltage Vx of node X when the sampling switch tube MN7 is turned on is:

[0042] (1-4)

[0043] Among them, V in It is the input signal voltage of the gate voltage bootstrap switch circuit.

[0044] From equations (1-3) and (1-4), we can know that by reasonably setting the input compensation bias voltage terminal VB voltage V B By adjusting the value of capacitor C5, the compensation charge pump circuit of the present invention can provide a stable voltage V when the input clock signal terminal CLK1 is high and the input clock signal terminal CLK2 is low. boost , effectively compensating for the influence of the parasitic capacitance Cp of the NMOS tube MN3; increasing the gate voltage of the sampling switch tube MN7 during sampling, greatly reducing its on-resistance, and improving the performance of the sampling switch tube.

[0045] The gate voltage bootstrap switch circuit with compensation of the present invention provides a higher power supply voltage for the charge pump branch in the gate voltage bootstrap switch circuit by using a compensating charge pump circuit, thereby compensating for the gate voltage drop caused by parasitic capacitance in the traditional gate voltage bootstrap switch, greatly reducing the on-resistance of the sampling switch tube and improving the linearity of the sampling switch tube. The charge pump branch in the gate voltage bootstrap switch circuit does not require a larger capacitor to increase the gate voltage of the sampling switch tube, thereby reducing the input parasitic capacitance.

[0046] The ADC may include the gate voltage bootstrap switch circuit with compensation of the present invention to achieve high-speed and high-precision sampling.

[0047] Although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention are also within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the content defined in the claims of this application.

Claims

1. A gate voltage bootstrap switch circuit with compensation, characterized in that: Including compensation charge pump circuit and gate voltage bootstrap switch circuit; The compensation charge pump circuit includes an NMOS transistor MN8, an NMOS transistor MN9, a PMOS transistor MP4, a PMOS transistor MP5, a capacitor C4, and a capacitor C5; the source of the NMOS transistor MN8 and the source of the NMOS transistor MN9 are connected to the input compensation bias voltage terminal VB; the gate of the NMOS transistor MN8 is connected to the gate of the PMOS transistor MP4, the drain of the NMOS transistor MN9, the drain of the PMOS transistor MP5, the positive end of the capacitor C5, and the power supply VDD; the drain of the NMOS transistor MN8 is connected to the drain of the PMOS transistor MP4, the gate of the NMOS transistor MN9, the gate of the PMOS transistor MP5, the positive end of the capacitor C4, and the power supply VDD; the negative end of the capacitor C4 is connected to the input clock signal terminal CLK2, and the negative end of the capacitor C5 is connected to the input clock signal terminal CLK1; the source of the PMOS transistor MP4 and the source of the PMOS transistor MP5 are connected to the output compensation voltage terminal V boost connect; The power supply terminal of the charge pump branch in the gate voltage bootstrap switch circuit is connected to the output compensation voltage terminal V of the compensation charge pump circuit boost superior; When the input clock signal terminal CLK1 is low and the input clock signal terminal CLK2 is high, the charge pump branch power supply terminal in the gate voltage bootstrap switch circuit is turned off. At this time, the capacitor C4 raises the drain voltage of the NMOS tube MN8 to V DD +VB turns on NMOS transistor MN9 to charge capacitor C5; When the input clock signal terminal CLK1 is at a high level and the input clock signal terminal CLK2 is at a low level, the charge pump branch power supply terminal in the gate voltage bootstrap switch circuit is turned on, and the bootstrap capacitor in the gate voltage bootstrap switch circuit is charged. The output terminal V boost Provides a voltage higher than the supply voltage V DD Compensation voltage V DD +ΔV, where ΔV is the compensated voltage.

2. The gate voltage bootstrap switch circuit with compensation according to claim 1, characterized in that: The signal clock phases of the input clock signal terminal CLK1 and the input clock signal terminal CLK2 are opposite.

3. The gate voltage bootstrap switch circuit with compensation according to claim 2, characterized in that: The output terminal V of the compensation charge pump circuit boost Provided higher than the supply voltage V DD The compensation voltage is , satisfying the following formula: （1-3） Among them, V B The fixed adjustable voltage signal provided by the input compensation bias voltage terminal VB, C3 is the capacitance of the bootstrap capacitor in the gate voltage bootstrap switch circuit, C5 is the capacitance of the capacitor C5, C p is the parasitic capacitance of the charge pump branch power supply terminal in the gate voltage bootstrap circuit, V DD is the power supply voltage.

4. The gate voltage bootstrap switch circuit with compensation according to claim 3, characterized in that: The gate voltage bootstrap switch circuit includes NMOS transistors MN1, NMOS transistors MN2, NMOS transistors MN3, NMOS transistors MN4, NMOS transistors MN5, NMOS transistors MN6, NMOS transistors MN7, PMOS transistors MP1, PMOS transistors MP2, PMOS transistors MP3, capacitors C1, capacitors C2, capacitors C3, transmission gates TG1 and TG2; NMOS transistor MN7 is a sampling switch transistor, and the drain of NMOS transistor MN7 is the output signal terminal Vout of the gate voltage bootstrap switch circuit; the input signal terminal Vin of the gate voltage bootstrap switch circuit is connected to NMOS transistors MN1, MN2, MN3, NMOS transistors MN4, MN5, NMOS transistors MN6, NMOS transistors MN7, PMOS transistors MP1, PMOS transistors MP2, PMOS transistors MP3, capacitors C1, ... The source of the MOS transistor MN7, one end of the transmission gate TG1, and one end of the transmission gate TG2 are connected, wherein the other end of the transmission gate TG1 is connected to the drain of the NMOS transistor MN6 and the negative end of the capacitor C3; the other end of the transmission gate TG2 is connected to the drain of the PMOS transistor MP2 and the gate of the PMOS transistor MP1; the gate of the NMOS transistor MN6 is connected to the input clock signal terminal CLK1, and the source is grounded; the transmission gates TG1 and TG2 both use the signals of the input clock signal terminals CLK1 and CLK2 as gate control signals; the positive end of the capacitor C3 is connected to the positive end of the NMOS transistor MN3 The source of the PMOS transistor MP1 is defined as the source of the NMOS transistor MN3 as the node X; the drain of the NMOS transistor MN3, the drain of the NMOS transistor MN1, the drain of the NMOS transistor MN2, and the source of the PMOS transistor MP2 are connected to the power supply VDD; the gate of the NMOS transistor MN3 is connected to the source of the NMOS transistor MN2, the gate of the NMOS transistor MN1, and the positive terminal of the capacitor C2; the gate of the NMOS transistor MN2 is connected to the source of the NMOS transistor MN1 and the positive terminal of the capacitor C1; the input clock signal terminal CLK1 is connected to the negative terminal of the capacitor C2 after passing through the inverter, and the input clock signal terminal CL K2 is connected to the negative terminal of capacitor C1 after passing through an inverter; the drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN4 and the gate of NMOS transistor MN7; the gate of PMOS transistor MP2 is connected to the input clock signal terminal CLK2; the gate of NMOS transistor MN4 is connected to the source of PMOS transistor MP3 and power supply VDD, the source of NMOS transistor MN4 is connected to the drain of PMOS transistor MP3 and the drain of NMOS transistor MN5, the gate of PMOS transistor MP3 and the gate of NMOS transistor MN5 are connected to the input clock signal terminal CLK1, and the source of NMOS transistor MN5 is grounded.

5. The gate voltage bootstrap switch circuit with compensation according to claim 4, characterized in that: The voltage Vx of node X when the sampling switch MN7 is turned on is expressed as follows: （1-4） Among them, V in It is the input signal voltage of the gate voltage bootstrap switch circuit.

6. An ADC, characterized in that It comprises the gate voltage bootstrap switch circuit with compensation as described in any one of claims 1-5.

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