Stacked gate dielectric p-GaN enhanced HEMT device and preparation method thereof

Abstract

The invention discloses a laminated gate dielectric p-GaN enhanced HEMT (High Electron Mobility Transistor) device and a preparation method thereof. According to the device, an AlN layer is grown in a metal organic chemical vapor deposition mode to serve as a gate dielectric layer, a silicide / metal oxide lamination layer is adopted as a contact passivation layer and a gate dielectric of the device to suppress current collapse, and the breakdown characteristic of the device is improved. The forbidden bandwidth of AlN is large (about 6.0 ev), a polarization effect is generated when the AlN is in contact with the metal oxide thin film, the AlN serves as a gate medium of the p-GaN HEMT device, the influence of threshold voltage drift of the device can be improved while gate electric leakage can be effectively restrained, and the overall performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a stacked gate dielectric p-GaN enhanced HEMT device and a preparation method thereof. Background Art

[0002] GaN high electron mobility transistors (HEMTs) offer advantages such as high power and ultra-high frequency, and currently hold broad application prospects in areas such as high-voltage switching and wireless 5G communications. One of the key limitations currently limiting GaN HEMT devices is the formation of enhancement-mode devices. Conventional GaN HEMTs are depletion-mode devices, requiring a negative gate bias to turn them off. For circuit safety and cost reduction, enhancement-mode devices with sufficiently high threshold voltages are required for high-power applications. Among the main approaches currently used to fabricate enhancement-mode GaN HEMTs, the most common method is to use a p-type GaN cap layer to deplete the two-dimensional electron gas (2DEG) beneath the channel. However, conventional Schottky-gate p-GaN HEMTs still suffer from issues such as small gate voltage swing, high gate leakage current, and low threshold voltage. Furthermore, process challenges must be overcome, such as the increased defect state density and decreased 2DEG concentration caused by etching the p-GaN layer above the barrier layer outside the gate region.

[0003] Traditional AlGaN / GaN HEMT devices generally use plasma-enhanced chemical vapor deposition (PECVD) to grow a layer of SiO2 / SiNx or a stack of the two dielectrics as a passivation layer to reduce the large number of defects and dangling bonds on the barrier layer surface. However, the PECVD method of depositing dielectrics cannot significantly reduce the interface state density. The interface trap states between AlGaN / GaN and SiO2 / SiNx can capture or release electrons, causing reliability issues such as device current collapse (Geng K, Chen D, Zhou Q, et al, Electronics, 2018, 416.).

[0004] Applying a metal oxide / SiO2 stack as a surface passivation layer in p-GaN gate enhancement-mode HEMT devices effectively reduces interface state density and improves device reliability. However, using it directly as a contact passivation layer or gate dielectric can cause a negative shift in the HEMT threshold voltage (Lin YC, Lin TW, Wu CH, et al., 2016, IEEE, 115-118). This is detrimental to enhancement-mode device applications. Therefore, a p-GaN device structure that balances high device reliability with high threshold voltage is needed. A three-layer gate dielectric structure of silicide / metal oxide / AlN combines the advantages of reducing gate leakage and increasing the threshold voltage of p-GaN gate devices. Metal oxide deposited via atomic layer deposition (ALD) offers minimal damage and precise control of film thickness at the atomic level. AlN films grown via metal-organic chemical vapor deposition (MOCVD) are dense and have low defect density. However, when the two films come into contact, the lattice constant difference creates a strong polarization effect, requiring a higher gate bias to offset the polarization field, thereby increasing the device threshold voltage. Furthermore, the dense AlN film can effectively protect the p-GaN gate during the deposition of the silicide film and metal oxide film, preventing it from being affected by impurities such as H and O, thereby improving device reliability. The topmost silicide film serves to increase the drain current. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention aims to provide a p-GaN enhanced-mode HEMT device with a stacked gate dielectric and a method for preparing the same. In addition to growing a layer of AlN as the gate dielectric layer via metal organic chemical vapor deposition, the device also utilizes a silicide / metal oxide stack as the device's contact passivation layer and gate dielectric to suppress current collapse and improve the device's breakdown characteristics. AlN has a large bandgap (~6.0 eV) and produces a polarization effect when in contact with a metal oxide film. Using it as the gate dielectric of a p-GaN HEMT device effectively suppresses gate leakage while minimizing the impact of device threshold voltage drift, thereby enhancing overall device performance.

[0006] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0007] A stacked gate dielectric p-GaN enhanced HEMT device includes a substrate layer, a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially from bottom to top;

[0008] The barrier layer has a source electrode, a p-GaN layer, and a drain electrode arranged on its upper surface from one end to the other, an AlN layer arranged on the p-GaN layer, a gate electrode arranged on the AlN layer, and a first dielectric layer and a second dielectric layer arranged between the AlN layer and the gate electrode;

[0009] The first dielectric layer covers all upper surfaces of the barrier layer except the contact surfaces with the source electrode, the p-GaN layer and the drain electrode, all surfaces of the p-GaN layer except the contact surfaces with the barrier layer and the AlN layer, and all surfaces of the AlN layer except the contact surface with the p-GaN layer;

[0010] The second dielectric layer covers the entire upper surface of the first dielectric layer;

[0011] All upper surfaces of the second dielectric layer except the contact surface with the gate electrode are covered with a third dielectric layer.

[0012] Furthermore, the thickness of the AlN layer from bottom to top is 1 to 10 nm;

[0013] The first dielectric layer is a metal oxide film, wherein the metal oxide is at least one of NiO, ZrO2, Ta2O5, TiO2, HfO2, Al2O3 or Ga2O3, and the first dielectric layer serves as both a gate dielectric and an underlying passivation layer. The thickness of the first dielectric layer from bottom to top is 1 to 10 nm;

[0014] The second dielectric layer is a silicide film, the silicide is at least one of SiO2 or Si3N4, the upper surface of the second dielectric layer is connected to the gate electrode, and the thickness of the second dielectric layer from bottom to top is 5 to 20 nm;

[0015] The third dielectric layer is a SiO2 thin film, and the thickness of the third dielectric layer from bottom to top is 50 to 200 nm.

[0016] Furthermore, the material of the substrate layer is any one of silicon, sapphire, silicon carbide, gallium nitride, and diamond self-supporting substrate;

[0017] The material of the nucleation layer is AlN superlattice; the material of the buffer layer is GaN or AlGaN;

[0018] The material of the channel layer is GaN or GaAs; the material of the barrier layer is any one of AlGaN, InAlN, AlN or InGaN;

[0019] The thicknesses of the substrate layer, nucleation layer, buffer layer, channel layer, barrier layer and p-GaN layer from bottom to top are 0.5-2 mm, 0.2-1 μm, 0.5-2.5 μm, 100-300 nm, 10-30 nm and 70-120 nm respectively.

[0020] A method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device comprises the following steps:

[0021] S1. Epitaxial growth: epitaxially grow a nucleation layer, a buffer layer, a channel layer, a barrier layer, a p-GaN layer, and an AlN layer on the substrate layer in sequence by metal organic chemical vapor deposition;

[0022] S2. Mesa isolation etching: The device mesa is patterned by photolithography, and the channel layer, barrier layer, p-GaN layer and AlN layer are etched for mesa isolation using ICP / RIE etching technology. The etching depth exceeds the sum of the thickness of the barrier layer and the channel layer.

[0023] S3. P-GaN etching outside the gate area: A patterned p-GaN gate area is obtained through photolithography. The p-GaN layer and AlN layer outside the gate area are completely removed using ICP / RIE etching technology, leaving only the p-GaN layer and AlN layer below the gate.

[0024] S4. Preparation of source and drain electrodes: obtaining patterned source and drain electrode regions by photolithography, and preparing source and drain electrodes on the upper surface of the barrier layer;

[0025] S5, preparing the first dielectric layer: depositing the first dielectric layer on the wafer surface;

[0026] S6, preparing the second dielectric layer: depositing a metal oxide thin film constituting the second dielectric layer on the surface of the wafer;

[0027] S7, second dielectric layer through hole: a patterned source-drain electrode through hole pattern is obtained by photolithography process, and the source-drain electrode through hole is formed by ICP / RIE etching technology;

[0028] S8, first dielectric layer through hole: obtain a patterned source and drain electrode through hole pattern by photolithography process, and form the source and drain electrode through hole by ICP / RIE etching technology;

[0029] S9, gate electrode preparation: obtain patterned gate and pad areas through photolithography process, deposit gate electrode and pad metal stack, and then perform metal stripping;

[0030] S10, preparation of the third dielectric layer: depositing a SiO2 thin film constituting the third dielectric layer on the surface of the wafer;

[0031] S11. Electrode through-hole: A graphic electrode pad through-hole pattern is obtained through a photolithography process, and an ICP / RIE etching technology is used to form an electrode pad through-hole to expose the source electrode, gate electrode, and drain electrode.

[0032] Furthermore, in the mesa isolation, p-GaN etching outside the gate region and electrode through-hole etching in steps S2, S3, S7, S8 and S11, the gas used is at least one of chlorine-based, fluorine-based, Ar, N2 or O2.

[0033] Furthermore, in step S4, the source electrode and the drain electrode are Ti / Al / Ni / Au or Ti / Al / Ti / Au stacks; after the source electrode and the drain electrode are peeled off, they are thermally annealed in a nitrogen atmosphere at a high temperature above 800°C for 15 to 60 seconds to form an ohmic alloy.

[0034] Furthermore, in step S5, the metal oxide film constituting the first dielectric layer is formed by magnetron sputtering deposition, with a sputtering power of 100-150 W, a chamber pressure of 5-10 mTorr, a sputtering temperature of 80-300° C., and a sputtering rate of 0.1-0.5 nm / min.

[0035] Furthermore, in step S6, the silicide film constituting the second dielectric layer is formed by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition, and the deposition temperature is 300-450°C.

[0036] Furthermore, in step S9, the gate electrode and pad metal are Ni / Au or Ni / TiN stacked layers.

[0037] Furthermore, in step S9, the SiO2 thin film constituting the third dielectric layer is formed by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition, and the deposition temperature is 300-450°C.

[0038] Compared with the prior art, the present invention has the following beneficial effects and technical advantages:

[0039] (1) A dense AlN layer is grown by metal organic chemical vapor deposition. Compared with traditional SiO2 passivation, it can effectively reduce the interface state density, inhibit current collapse, improve the device saturation current density and breakdown characteristics, and protect the active area of ​​the device.

[0040] (2) Silicide / metal oxide / AlN is used as the gate dielectric of the p-GaN gate enhancement mode MIS-HEMT. The polarization effect generated by the stacking interface improves the threshold voltage of the device, thereby improving the gate control capability of the device and effectively reducing the gate leakage.

[0041] (3) Al2O3 is used as the gate dielectric and the underlying passivation layer to wrap the entire p-GaN gate, optimizing the peak electric field introduced by the p-GaN sidewall and further improving the device breakdown characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 Flowchart of a method for preparing a stacked-gate dielectric p-GaN enhancement-mode HEMT device according to an embodiment of the present invention;

[0043] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 Schematic diagram of the formation process of a stacked-gate dielectric p-GaN enhancement-mode HEMT device according to an embodiment of the present invention;

[0044] Figure 9 Schematic diagram of transfer characteristics of a stacked gate dielectric p-GaN enhancement mode HEMT device, a p-GaN gate MIS-HEMT device containing a SiO2 gate dielectric, and a p-GaN gate MIS-HEMT device with an Al2O3 gate dielectric, provided in an embodiment of the present invention;

[0045] Figure 10 Schematic diagram of gate leakage current of a p-GaN enhancement-mode HEMT device with a stacked gate dielectric, a p-GaN gate MIS-HEMT device with a SiO2 gate dielectric, and a p-GaN gate MIS-HEMT device with an Al2O3 gate dielectric, provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The present invention is further described in detail below with reference to the accompanying drawings and examples. However, the present invention can also be implemented or applied in other different specific ways. It should be pointed out that as long as various changes and modifications are based on the limitations and spirit of the claims attached to the present invention, they are all within the scope of protection.

[0047] In one embodiment, a method for preparing a stacked gate dielectric p-GaN enhanced mode HEMT device is as follows: Figure 1 As shown, the following steps are included:

[0048] S1. Epitaxial growth: by metal organic chemical vapor deposition MOCVD, such as Figure 2 As shown, an AlN nucleation layer 02, an AlGaN buffer layer 03, a GaN channel layer 04, an AlGaN barrier layer 05, a p-GaN layer 06, and an AlN layer 07 are epitaxially grown on a silicon substrate layer 01. The epitaxial layer is immersed in a solution of H2SO4:H2O2=3:1 (volume ratio) for 10 minutes to remove the surface oxide layer, and then ultrasonically cleaned with acetone and isopropyl alcohol for 10 minutes to remove organic matter on the epitaxial layer.

[0049] S2. Mesa isolation etching: A patterned device mesa is obtained by photolithography, and the GaN channel layer 04, AlGaN barrier layer 05, p-GaN layer 06 and AlN layer 07 are subjected to mesa isolation etching using ICP / RIE etching technology. The etching depth exceeds the sum of the thicknesses of the GaN channel layer 04 and the AlGaN barrier layer 05.

[0050] S3. Etching of p-GaN outside the gate region: A patterned p-GaN gate region is obtained by photolithography, and the p-GaN layer 06 and the AlN layer 07 except the gate region are completely removed by ICP / RIE etching technology, leaving only the p-GaN layer 06 and the AlN layer 07 below the gate. In one embodiment, the etching gas is first Cl2 / BCl3, with flow rates of 60 / 10 sccm, ICP / RF powers of 300 / 500 W, and an intracavity pressure of 5 mTorr, and then Cl2 / Ar / O2 is used, with flow rates of 40 / 10 / 5 sccm, ICP / RF powers of 200 / 50 W, and an intracavity pressure of 1 mTorr. The p-GaN etching rate is 4-5 nm / min. After the etching is completed, Figure 3 As shown;

[0051] S4, source and drain electrode preparation: obtain patterned source electrode 08 and drain electrode 09 regions through photolithography process, and prepare source electrode 08 and drain electrode 09 on the upper surface of barrier layer 05, such as Figure 4 As shown, in one embodiment, the thickness of the first metal layer Ti is 20 nm, the thickness of the second metal layer Al is 100 nm, the thickness of the third metal layer Ni is 10 nm, and the thickness of the fourth metal layer Au is 100 nm. After the metal electrodes are peeled off, they are thermally annealed at 830° C. for 1 min in an N2 atmosphere;

[0052] S5. Preparation of the first dielectric layer: A first dielectric layer 11 with a thickness of 10 nm is deposited on the surface of the wafer by magnetron sputtering. In one embodiment, the first dielectric layer 11 is Al2O3, the sputtering power is 150 W, the pressure in the chamber is 6 mTorr, the sputtering temperature is 100 ° C, and the sputtering rate is 0.05 nm / min. After the deposition is completed, Figure 5 As shown;

[0053] S6, preparation of the second dielectric layer: using PECVD to deposit a metal oxide film constituting the second dielectric layer 12 on the wafer surface. In one embodiment, the metal oxide film of the second dielectric layer 12 is SiO2, the deposition temperature is 300°C, the deposition thickness is 10nm, and after the deposition is completed, Figure 5 As shown;

[0054] S7, second dielectric layer through hole: a patterned source-drain electrode through hole pattern is obtained by photolithography, and the source-drain electrode through holes are formed by ICP / RIE etching technology to expose the source electrode 07, the gate electrode 08, and the drain electrode 09. In one embodiment, the etching gas is CHF3 / O2 with a flow rate of 50 / 10 sccm, the ICP / RF power is 400 / 60 W, and the chamber pressure is 5 mTorr;

[0055] S8. First dielectric layer through hole: A patterned source and drain electrode through hole pattern is obtained by photolithography, and the source and drain electrode through holes are formed by ICP / RIE etching technology. The etching gas used is Cl2 / BCl3, with flow rates of 60 / 10 sccm, ICP / RF power of 300 / 500 W, and the chamber pressure is 5 mTorr.

[0056] S9, gate electrode preparation: obtain patterned gate and pad area through photolithography process, deposit gate electrode 10 and pad metal stack, then perform metal stripping, obtain patterned gate electrode 09 and pad through photolithography and stripping process, as shown in FIG. Figure 7 As shown, in one embodiment, the thickness of the first metal layer Ni is 50 nm, and the thickness of the second metal layer Au is 200 nm;

[0057] S10, preparation of the third dielectric layer: using PECVD to deposit a SiO2 thin film constituting the third dielectric layer 13 on the wafer surface. In one embodiment, the deposition temperature is 300° C. and the deposition thickness is 200 nm.

[0058] S11, electrode through-hole: a patterned electrode pad through-hole pattern is obtained by photolithography, and an electrode pad through-hole is formed by ICP / RIE etching technology to expose the source electrode 08, the gate electrode 10 and the drain electrode 09. In one embodiment, the etching gas is CHF3 / O2, with a flow rate of 50 / 10 sccm, the ICP / RF power is 400 / 60 W, and the pressure in the chamber is 5 mTorr. After the etching is completed, Figure 8 shown.

[0059] In one embodiment, Figure 9 Schematic diagrams of transfer characteristic curves for a p-GaN enhanced-mode HEMT device with a stacked gate dielectric, a p-GaN enhanced-mode MIS-HEMT device with an Al2O3 gate dielectric, and a p-GaN enhanced-mode MIS-HEMT device with a conventional SiO2 dielectric passivation as a comparison. The p-GaN enhanced-mode MIS-HEMT device with a conventional SiO2 dielectric passivation has a threshold voltage of +0.93V, while the p-GaN enhanced-mode MIS-HEMT device with an Al2O3 gate dielectric has a threshold voltage of +1.42V. The p-GaN enhanced-mode HEMT device with a stacked gate dielectric provided in the embodiments has a threshold voltage of +2.62V. Using the metal oxide and AlN interface as the gate dielectric for the p-GaN enhanced-mode HEMT device effectively mitigates the negative threshold voltage drift problem.

[0060] In one embodiment, Figure 10Schematic diagram of gate leakage of a p-GaN enhanced HEMT device with a stacked gate dielectric, a p-GaN gate enhanced MIS-HEMT device with an Al2O3 gate dielectric, and a p-GaN gate enhanced MIS-HEMT device with a traditional SiO2 dielectric passivation. When a -2V gate voltage is applied, the gate leakage of the p-GaN enhanced HEMT device with a stacked gate dielectric provided in the embodiment is about 10 -10 A / mm, less than 10 -9 A / mm, an order of magnitude lower gate leakage than the two control groups without Al2O3 gate dielectric. The gate breakdown voltage reaches 5.87V.

[0061] The above embodiments are intended to help readers understand the structure and preparation method of the present invention. The embodiments of the present invention are not limited to the above embodiments. Those skilled in the art may make various other specific modifications and combinations based on the technical teachings disclosed in the present invention without departing from the essence of the present invention, and such modifications and combinations remain within the scope of protection of the present invention.

Claims

1. A stacked gate dielectric p-GaN enhanced HEMT device, characterized in that: It comprises a substrate layer (01), a nucleation layer (02), a buffer layer (03), a channel layer (04) and a barrier layer (05) stacked in sequence from bottom to top; The barrier layer (05) is provided with a source electrode (08), a p-GaN layer (06) and a drain electrode (09) spaced from one end to the other in sequence on its upper surface; an AlN layer (07) is provided on the p-GaN layer (06); a gate electrode (10) is provided on the AlN layer (07); and a first dielectric layer (11) and a second dielectric layer (12) are provided between the AlN layer (07) and the gate electrode (10); The first dielectric layer (11) covers all upper surfaces of the barrier layer (05) except the contact surfaces with the source electrode (08), the p-GaN layer (06) and the drain electrode (09), all surfaces of the p-GaN layer (06) except the contact surfaces with the barrier layer (05) and the AlN layer (07), and all surfaces of the AlN layer (07) except the contact surface with the p-GaN layer (06); The second dielectric layer (12) covers all upper surfaces of the first dielectric layer (11); All upper surfaces of the second dielectric layer (12) except the contact surface with the gate electrode (10) are covered with a third dielectric layer (13).

2. The stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 1, characterized in that: The thickness of the AlN layer (07) from bottom to top is 1 to 10 nm; The first dielectric layer (11) is a metal oxide film, wherein the metal oxide is at least one of NiO, ZrO2, Ta2O5, TiO2, HfO2, Al2O3 or Ga2O3, and the first dielectric layer (11) serves as both a gate dielectric and an underlying passivation layer. The thickness of the first dielectric layer (11) from bottom to top is 1 to 10 nm; The second dielectric layer (12) is a silicide film, the silicide is at least one of SiO2 and Si3N4, the upper surface of the second dielectric layer (12) is connected to the gate electrode (10), and the thickness of the second dielectric layer (12) from bottom to top is 5 to 20 nm; The third dielectric layer (13) is a SiO2 thin film, and the thickness of the third dielectric layer (13) from bottom to top is 50 to 200 nm.

3. The stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 1, characterized in that: The material of the substrate layer (01) is any one of silicon, sapphire, silicon carbide, gallium nitride, and diamond self-supporting substrate; The material of the nucleation layer (02) is AlN superlattice; the material of the buffer layer (03) is GaN or AlGaN; The material of the channel layer (04) is GaN or GaAs; the material of the barrier layer (05) is any one of AlGaN, InAlN, AlN or InGaN; The thicknesses of the substrate layer (01), nucleation layer (02), buffer layer (03), channel layer (04), barrier layer (05) and p-GaN layer (06) from bottom to top are 0.5-2 mm, 0.2-1 μm, 0.5-2.5 μm, 100-300 nm, 10-30 nm and 70-120 nm, respectively.

4. A method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device, characterized in that: The steps include: S1. Epitaxial growth: epitaxially growing a nucleation layer (02), a buffer layer (03), a channel layer (04), a barrier layer (05), a p-GaN layer (06) and an AlN layer (07) on a substrate layer (01) by metal organic chemical vapor deposition (MOCVD); S2. Mesa isolation etching: a patterned device mesa is obtained by photolithography, and the channel layer (04), the barrier layer (05), the p-GaN layer (06) and the AlN layer (07) are subjected to mesa isolation etching by ICP / RIE etching technology, wherein the etching depth exceeds the sum of the thickness of the barrier layer (05) and the channel layer (04); S3, p-GaN etching outside the gate region: a patterned p-GaN gate region is obtained by photolithography, and the p-GaN layer (06) and the AlN layer (07) except the gate region are completely removed by ICP / RIE etching technology, leaving only the p-GaN layer (06) and the AlN layer (07) below the gate; S4. Preparation of source and drain electrodes: obtaining patterned source electrode (08) and drain electrode (09) regions by photolithography, and preparing source electrode (08) and drain electrode (09) on the upper surface of barrier layer (05); S5, preparing the first dielectric layer: depositing the first dielectric layer (11) on the surface of the wafer; S6, preparation of the second dielectric layer: depositing a metal oxide thin film constituting the second dielectric layer (12) on the surface of the wafer; S7, second dielectric layer through hole: a patterned source-drain electrode through hole pattern is obtained by photolithography process, and the source-drain electrode through hole is formed by ICP / RIE etching technology; S8, first dielectric layer through hole: obtain a patterned source and drain electrode through hole pattern by photolithography process, and form the source and drain electrode through hole by ICP / RIE etching technology; S9, gate electrode preparation: obtaining a patterned gate and pad area through a photolithography process, depositing a gate electrode (10) and a pad metal stack, and then performing metal stripping; S10, preparation of the third dielectric layer: depositing a SiO2 thin film constituting the third dielectric layer (13) on the surface of the wafer; S11. Electrode through-hole: A graphic electrode pad through-hole pattern is obtained by photolithography, and an ICP / RIE etching technique is used to form an electrode pad through-hole to expose the source electrode (08), the gate electrode (10) and the drain electrode (09).

5. The method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 4, characterized in that: In the mesa isolation, p-GaN etching outside the gate region and electrode through-hole etching in steps S2, S3, S7, S8 and S11, the gas used is at least one of chlorine-based, fluorine-based, Ar, N2 or O2.

6. The method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 4, characterized in that: In step S4, the source electrode (08) and the drain electrode (09) are Ti / Al / Ni / Au or Ti / Al / Ti / Au stacks; after the source electrode (08) and the drain electrode (09) are peeled off, they are thermally annealed in a nitrogen atmosphere at a high temperature of more than 800°C for 15 to 60 seconds to form an ohmic alloy.

7. The method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 4, characterized in that: In step S5, the metal oxide film constituting the first dielectric layer (11) is formed by magnetron sputtering deposition, with a sputtering power of 100-150W, a chamber pressure of 5-10mTorr, a sputtering temperature of 80-300°C, and a sputtering rate of 0.1-0.5nm / min.

8. The method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 4, characterized in that: In step S6, the silicide film constituting the second dielectric layer (12) is formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) at a deposition temperature of 300-450°C.

9. The method for preparing a stacked gate dielectric p-GaN enhanced-mode HEMT device according to claim 4, wherein: In step S9, the gate electrode (10) and the pad metal are Ni / Au or Ni / TiN stacked layers.

10. The method for preparing a stacked gate dielectric p-GaN enhanced mode HEMT device according to claim 4, wherein: In step S9, the SiO2 film constituting the third dielectric layer (13) is formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) at a deposition temperature of 300-450°C.

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