Instruction distribution device and method, processor and electronic equipment

Abstract

The embodiment of the invention provides an instruction distribution device and method, a processor and electronic equipment. The instruction distribution device comprises a write selection module, a plurality of micro instruction queues and a read distribution module. The write selection module is configured to write microinstructions into a plurality of microinstruction queues; the plurality of microinstruction queues are configured to cache written microinstructions; and the read distribution module is configured to read the microinstructions from the plurality of microinstruction queues, obtain a target microinstruction group to be distributed at this time based on the read microinstructions, and execute a distribution operation. The instruction distribution device improves the bandwidth of instruction distribution by setting a plurality of microinstruction queues and a scheduling method of the plurality of microinstruction queues, thereby promoting the improvement of the performance of a processor.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction distribution device, an instruction distribution method, a processor, and an electronic device. Background Art

[0002] In a processor, the instruction pipeline can be divided into the front-end and back-end according to different functional stages. They work together to complete instruction execution. As the types and number of execution components in the back-end pipeline increase, the back-end's execution capabilities continue to improve. At the same time, current software applications are also increasingly demanding the execution capabilities of the front-end. Therefore, improving the processor capabilities of the front-end has become increasingly important. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides an instruction distribution device, comprising: a write selection module, multiple microinstruction queues and a read allocation module; wherein the write selection module is configured to write microinstructions into the multiple microinstruction queues; the multiple microinstruction queues are configured to cache the written microinstructions; the read allocation module is configured to read microinstructions from the multiple microinstruction queues, obtain the target microinstruction group to be distributed this time based on the read microinstructions, and perform a distribution operation.

[0004] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the write selection module is further configured to write the microinstructions into the multiple microinstruction queues according to a preset mapping relationship.

[0005] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the write selection module is further configured to, when the multiple microinstruction queues are two microinstruction queues, write microinstructions from the same microinstruction source evenly into the two microinstruction queues according to a preset mapping relationship.

[0006] For example, in an instruction distribution device provided in at least one embodiment of the present disclosure, the read allocation module includes: a reordering unit, configured to read microinstructions from the multiple microinstruction queues and reorder the read microinstructions according to the actual instruction order; a first determination unit, configured to determine at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints; and a distribution unit, configured to distribute the target microinstruction group.

[0007] For example, in an instruction distribution device provided in at least one embodiment of the present disclosure, the distribution unit is further configured to distribute the target microinstruction group through a read pointer, wherein, after the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

[0008] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the first determination unit also includes a microinstruction register, wherein the microinstruction register is configured to store the reordered microinstructions read for the first time when the target microinstruction group is obtained based on the reordered microinstructions read twice.

[0009] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the write selection module includes: a second determination unit, configured to determine at least one microinstruction group in the microinstruction according to preset constraints; and an allocation unit, configured to write the microinstructions in the at least one microinstruction group into the multiple microinstruction queues.

[0010] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the preset constraints include instruction attribute information and / or instruction execution information.

[0011] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the allocation unit is further configured to allocate the microinstructions in the at least one microinstruction group to the multiple microinstruction queues according to a preset mapping relationship.

[0012] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the allocation unit is further configured to dynamically allocate the microinstructions in the at least one microinstruction group to the multiple microinstruction queues.

[0013] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the distribution unit is further configured to record boundary information of each microinstruction group.

[0014] For example, in an instruction distribution device provided by at least one embodiment of the present disclosure, the allocation unit is further configured to write the boundary information of each microinstruction group into the multiple microinstruction queues, each microinstruction queue includes multiple entries, and each entry includes a flag bit, wherein the flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

[0015] For example, an instruction distribution device provided by at least one embodiment of the present disclosure further includes a microinstruction quantity queue, wherein the allocation unit is further configured to write the boundary information of each microinstruction group into the microinstruction quantity queue, and the microinstruction quantity queue is configured to store the number of microinstructions of each microinstruction group stored in each microinstruction queue respectively, and the boundary information includes the number of microinstructions.

[0016] For example, in an instruction distribution device provided in at least one embodiment of the present disclosure, the read allocation module also includes: a distribution unit, which is further configured to obtain the target microinstruction group and perform the distribution operation based on the boundary information and the microinstructions read from the multiple microinstruction queues.

[0017] At least one embodiment of the present disclosure also provides an instruction distribution method, comprising: writing microinstructions into multiple microinstruction queues, wherein the multiple microinstruction queues are configured to cache the written microinstructions; reading microinstructions from the multiple microinstruction queues, obtaining a target microinstruction group to be distributed this time based on the read microinstructions, and performing a distribution operation.

[0018] For example, in an instruction distribution method provided by at least one embodiment of the present disclosure, writing microinstructions into multiple microinstruction queues includes: writing the microinstructions into the multiple microinstruction queues according to a preset mapping relationship.

[0019] For example, in an instruction distribution method provided in at least one embodiment of the present disclosure, microinstructions are read from the multiple microinstruction queues, a target microinstruction group to be distributed this time is obtained based on the read microinstructions, and a distribution operation is performed, including: reading microinstructions from the multiple microinstruction queues, and reordering the read microinstructions according to the actual instruction order; determining at least one microinstruction group including the target microinstruction group based on the reordered microinstructions and preset constraints; and distributing the target microinstruction group.

[0020] For example, in an instruction distribution method provided in at least one embodiment of the present disclosure, distributing the target microinstruction group includes: distributing the target microinstruction group through a read pointer, wherein, after the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

[0021] For example, in an instruction distribution method provided in at least one embodiment of the present disclosure, writing microinstructions into multiple microinstruction queues includes: determining at least one microinstruction group in the microinstructions according to preset constraints; and writing the microinstructions in the at least one microinstruction group into the multiple microinstruction queues.

[0022] For example, in an instruction distribution method provided in at least one embodiment of the present disclosure, writing the microinstructions in the at least one microinstruction group into the multiple microinstruction queues includes: allocating the microinstructions in the at least one microinstruction group to the multiple microinstruction queues according to a preset mapping relationship.

[0023] For example, in an instruction distribution method provided in at least one embodiment of the present disclosure, writing the microinstructions in the at least one microinstruction group into the multiple microinstruction queues includes: dynamically allocating the microinstructions in the at least one microinstruction group to the multiple microinstruction queues.

[0024] For example, at least one embodiment of the present disclosure provides an instruction distribution method, further comprising: recording boundary information of each microinstruction group.

[0025] At least one embodiment of the present disclosure further provides a processor, comprising the instruction distribution device provided by any embodiment of the present disclosure.

[0026] At least one embodiment of the present disclosure further provides an electronic device, comprising the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0028] Figure 1 A schematic diagram illustrating an example of a front-end structure of a CPU core;

[0029] Figure 2 A schematic block diagram of an instruction distribution device provided in at least one embodiment of the present disclosure;

[0030] Figure 3 A schematic diagram of the operation of a write selection module provided by at least one embodiment of the present disclosure;

[0031] Figure 4 A schematic block diagram of an instruction distribution device provided in at least one embodiment of the present disclosure;

[0032] Figure 5 A schematic diagram of the operation of a read allocation module provided in at least one embodiment of the present disclosure;

[0033] Figure 6 A schematic diagram of an instruction distribution device provided by at least one embodiment of the present disclosure;

[0034] Figure 7 A schematic block diagram of another instruction distribution device provided in at least one embodiment of the present disclosure;

[0035] Figure 8A A schematic diagram of the operation of a distribution unit provided in at least one embodiment of the present disclosure;

[0036] Figure 8B Another working schematic diagram of a dispensing unit provided in at least one embodiment of the present disclosure;

[0037] Figure 9A A schematic diagram of a microinstruction queue provided for at least one embodiment of the present disclosure;

[0038] Figure 9B Another schematic diagram of a microinstruction queue provided by at least one embodiment of the present disclosure;

[0039] Figure 10 A schematic diagram of another instruction distribution device provided for at least one embodiment of the present disclosure;

[0040] Figure 11 A schematic flow chart of an instruction distribution method provided in at least one embodiment of the present disclosure;

[0041] Figure 12 A schematic block diagram of a processor provided for at least one embodiment of the present disclosure;

[0042] Figure 13 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure; and

[0043] Figure 14 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that the disclosure is not intended to be limited to the described embodiments. On the contrary, it is intended to cover variations, modifications, and equivalents within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0045] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Note that the examples described below are merely specific examples and are not intended to limit the embodiments of the present disclosure to the specific configurations, hardware, connections, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct further embodiments not described herein by reading this specification.

[0047] The terms used in this disclosure are those commonly used in the art currently in consideration of the functions of the present disclosure, but these terms may vary according to the intentions of those skilled in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as a general description based on the meaning of the terms and the present disclosure.

[0048] Flowcharts are used in this disclosure to illustrate the operations performed by the systems according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously, as needed. Furthermore, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0049] The front-end and back-end are two key parts that work closely together inside the central processing unit (CPU) core. They jointly drive the processing flow of instructions and ensure that the CPU can execute programs efficiently.

[0050] The front end is the starting point of the pipeline and is primarily responsible for instruction acquisition, decoding, and preliminary processing. It reads instructions (e.g., "machine instructions") from memory, a process controlled by a program counter that points to the address of the instruction currently to be executed. Based on the value of the program counter, the front end reads instructions from the instruction cache, which is used to store recently accessed instructions to reduce access latency to main memory. After acquiring the instruction, the front end's decoding unit decodes the instruction into one or more micro-operations (or "microinstructions"), parses the instruction's opcode and operands, and determines the type of instruction, such as arithmetic, logical, or branch instruction.

[0051] For example, the front-end also undertakes the important task of branch prediction. The branch predictor analyzes the program's execution path and predicts the direction of branch instructions. This includes a branch target buffer and a branch direction predictor, which help the front-end pre-fetch instructions that are likely to be executed, reducing pipeline stalls. Furthermore, the front-end attempts to pre-fetch subsequent instructions, implementing pre-fetching through the instruction prefetch queue to further optimize instruction fetch efficiency.

[0052] For example, another important function of the front-end is instruction scheduling. It performs preliminary scheduling of decoded instructions, optimizing their execution order. For example, it reduces data and structural conflicts through reordering. Another key component of the front-end is the instruction queue, which temporarily stores decoded instructions pending execution by the back-end.

[0053] The backend is the final part of the CPU pipeline, primarily responsible for actual instruction execution and result processing. It receives instructions decoded by the frontend and performs operations such as instruction execution, data access, and result writeback. The backend comprises multiple execution units, such as the integer arithmetic unit (ALU), floating-point arithmetic unit (FPU), and logical arithmetic unit (LAU). These units are responsible for executing decoded instructions and generating results. After the execution units complete instruction execution, the commit unit determines whether the result should be written back to the target register or memory.

[0054] The back end is also responsible for accessing memory or cache to read or write data, including load and store operations. The data cache stores recently accessed data, reducing access latency to main memory. The register file stores register values ​​used during instruction execution. The back end also handles conflicts and stalls in the pipeline and ensures efficient pipeline operation. The pipeline control unit coordinates the various pipeline stages and handles conflicts and stalls.

[0055] In the pipeline, the front-end and back-end work closely together to complete instruction processing. The front-end sends decoded instructions to the back-end's execution unit, which writes the results back to registers or memory after execution. The back-end reports any anomalies discovered during execution to the front-end, which then adjusts its instruction fetching and decoding strategies based on this information. This collaborative mechanism ensures efficient CPU program execution. The front-end's instruction fetching and decoding capabilities directly impact the back-end's execution efficiency, which in turn influences the front-end's instruction scheduling strategies. Through efficient collaboration between the front-end and back-end, modern CPUs achieve high-performance instruction processing to meet the demands of complex computing tasks.

[0056] Figure 1 The diagram below shows an example of a front-end structure of a CPU core. Figure 1 As shown, the front end 101 of the CPU core includes an instruction fetch unit, a decoding unit (also known as a decoding unit) and an emission unit (also known as a distribution unit). The instruction fetch unit includes a branch prediction 201 and a selection logic 202; the decoding unit includes an instruction cache 203, an instruction decode 204, a microinstruction cache 205 and a microinstruction queue 206; and the emission unit 207 is connected to the microinstruction queue 206. The CPU core has both an instruction cache and a microinstruction cache, so it has microarchitecture optimization. The instruction address obtained by the instruction fetch unit is predicted by the branch prediction 201 to obtain the instruction address to be executed next. At the same time, the instruction address passes through the selection logic 202 to determine whether the instruction corresponding to the instruction address needs to be decoded to obtain a microinstruction. If "yes", then go to Figure 1 The left path in the middle needs to decode the instruction; if "no", then go to Figure 1The path on the right does not need to decode the instruction, but accesses the microinstruction cache to obtain the corresponding microinstructions. For example, these microinstructions are usually organized in the form of microinstruction groups.

[0057] In processor design, a micro-op group (Micro-Ops Group) in instruction dispatch refers to a collection of multiple micro-instructions formed by breaking down complex instructions. Modern processors (especially CPUs using the Complex Instruction Set Computer (CISC) architecture) typically break down complex instructions into simpler micro-instructions that can be parallelized or pipelined when executing them. These micro-instructions are grouped together as a logical unit and dispatched by the processor's dispatch unit, dispatching them to various execution units (such as the arithmetic logic unit (ALU) and load / store units).

[0058] As the types and number of execution units in the back-end pipeline increase, back-end execution capabilities continue to improve. At the same time, current software applications are increasingly demanding front-end execution capabilities. Therefore, improving front-end processor capabilities is becoming increasingly important, and increasing instruction dispatch bandwidth is a key component. Instruction dispatch bandwidth refers to the number of instructions a processor can dispatch to different execution units per cycle.

[0059] The inventors of this disclosure have noted that current methods for increasing instruction dispatch bandwidth often simply increase the number of read ports in the microinstruction queue. This increases timing risks in implementation, and a large number of read ports increases the area of ​​the instruction dispatch device. Furthermore, when reading microinstructions from the microinstruction queue and dispatching the microinstruction group, this increases the critical path, making it more difficult to increase the processor's main frequency.

[0060] At least one embodiment of the present disclosure provides an instruction distribution device and an instruction distribution method, a processor, and an electronic device.

[0061] The instruction distribution device includes a write selection module, multiple microinstruction queues and a read allocation module. The write selection module is configured to write microinstructions into multiple microinstruction queues; the multiple microinstruction queues are configured to cache the written microinstructions; the read allocation module is configured to read microinstructions from multiple microinstruction queues, obtain the target microinstruction group to be distributed this time based on the read microinstructions, and perform a distribution operation. The instruction distribution device improves the bandwidth of instruction distribution by setting multiple microinstruction queues, thereby promoting the improvement of processor performance. Moreover, in at least one example, by setting a scheduling method for multiple microinstruction queues, microinstructions can be flexibly scheduled, further promoting the improvement of processor performance.

[0062] The instruction distribution method includes: writing microinstructions into multiple microinstruction queues, and the multiple microinstruction queues are configured to cache the written microinstructions; reading microinstructions from the multiple microinstruction queues, obtaining the target microinstruction group to be distributed this time based on the read microinstructions, and performing the distribution operation. The instruction distribution method improves the bandwidth of instruction distribution by setting multiple microinstruction queues, thereby promoting the improvement of processor performance. Moreover, in at least one example, by setting a scheduling method for multiple microinstruction queues, microinstructions are flexibly scheduled, further promoting the improvement of processor performance. The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0063] Figure 2 A schematic block diagram of an instruction distribution device provided in at least one embodiment of the present disclosure.

[0064] like Figure 2 As shown, the instruction dispatch device 200 of this embodiment is located in the pipeline of the processor core and includes a write selection module 210, multiple microinstruction queues 2201-220n (n is a positive integer greater than 1), and a read dispatch module 230. In the pipeline, the write selection module 210, multiple microinstruction queues 220, and read dispatch module 230 are connected in sequence.

[0065] The write selection module 210 is configured to write microinstructions into multiple microinstruction queues 2201~220n; the multiple microinstruction queues 2201~220n are configured to cache the written microinstructions; the read allocation module 230 is configured to read microinstructions from the multiple microinstruction queues 2201~220n, obtain the target microinstruction group to be distributed this time based on the read microinstructions, and perform the distribution operation.

[0066] For example, Figure 2 As shown, multiple microinstruction queues 2201-220n can be respectively represented as microinstruction queues numbered 2201, 2202, ... and 220n, which are used to cache microinstructions corresponding to different microinstruction slots. For example, a microinstruction slot is a logical or physical location reserved for different types of operations in the processor hardware, which is used to classify and distribute decoded microinstructions to corresponding execution units. For example, the number of multiple microinstruction queues and the structure of each microinstruction queue can be designed based on the performance of the pipeline, and the embodiments of the present disclosure do not impose any restrictions on this.

[0067] For example, each microinstruction queue includes a write port and a read port for managing operations between writing and reading microinstructions. The write selection module 210 writes microinstructions into the microinstruction queue through the write port, and the read dispatch module 230 reads microinstructions from the microinstruction queue through the read port and performs dispatch operations.

[0068] For example, the bandwidth of instruction distribution matches the number of read ports of the microinstruction queue, and the number of microinstructions distributed at each time by instruction distribution can be equal to the number of microinstructions that the read distribution module can read simultaneously at each time. For example, reading the microinstruction queue and distributing the target microinstruction group are carried out per cycle, and this cycle can be a processor machine cycle, that is, the time cycle of a basic operation of the CPU under the control of the clock signal, and each machine cycle can include one or more clock cycles. For example, the read distribution module can read the microinstructions in a plurality of microinstruction queues once or multiple times per clock cycle, and distribute the microinstruction group. For example, the target microinstruction group can be the microinstruction group distributed in the current clock cycle, and the target microinstruction group can be one or more microinstruction groups. For example, the target microinstruction group can be distributed to the execution unit of the pipeline, and the execution unit can include a memory access unit, a fixed-point arithmetic unit or a floating-point operation etc.

[0069] For example, the microinstructions being written may come from at least one microinstruction source, such as an instruction decode path and / or a micro-op cache (OC) fetch path. For example, the instruction decode path may read instructions from the instruction cache or memory and decode them into microinstructions. Another example is that the OC path may store decoded microinstructions. If the same instruction is executed again, the microinstructions can be read directly from the OC without requiring further decoding. The instruction decode path may include a single or multiple instruction decode paths, and the OC fetch path may include a single or multiple OC fetch paths. In other words, the disclosed embodiments do not limit the number of microinstruction sources and are applicable to processor microarchitectures that include single or multiple decode pipelines. The microinstructions written to the microinstruction queue at the same time may come from the same or different sources. For example, the instruction decode path and the OC fetch path may simultaneously provide microinstructions to the microinstruction queue at the same time. For another example, the instruction decoding channel or the microinstruction cache (OC) fetch channel can independently provide microinstructions to the microinstruction queue at the same time.

[0070] For example, the write select module 210 may be further configured to write microinstructions alternately.

[0071] For example, in at least one embodiment of the present disclosure, the write selection module 210 may be further configured to write the microinstructions into the plurality of microinstruction queues according to a preset mapping relationship. For example, the preset mapping relationship may be to write the microinstructions into the plurality of microinstruction queues 220 1 -220 n in a manner of fixedly allocating the microinstruction queues.

[0072] The instruction distribution device provided in at least one embodiment of the present disclosure adopts a design method of providing "multiple microinstruction queues". Without sacrificing the processor's main frequency, for example, it can increase the bandwidth of instruction distribution without increasing the read port of a single microinstruction queue, thereby improving processor performance.

[0073] Figure 3 A schematic diagram of the operation of a write selection module provided in at least one embodiment of the present disclosure is a specific example of the write selection module writing microinstructions into multiple microinstruction queues according to a preset mapping relationship.

[0074] For example, in some embodiments, the write selection module is further configured to, when the multiple microinstruction queues are two microinstruction queues, write microinstructions from the same microinstruction source to the two microinstruction queues evenly according to a preset mapping relationship. That is, over a long period of time (e.g., greater than 1000 machine cycles), write microinstructions to the two microinstruction queues with equal probability. For example, the write selection module may write microinstructions from the same microinstruction source to the two microinstruction queues at the same ratio (50% each) within a machine cycle. For example, the same microinstruction source may include an instruction decode channel or a microinstruction cache (OC) instruction fetch channel.

[0075] like Figure 3 As shown in , the sources of microinstructions can include instruction decoding channel and microinstruction cache (OC) instruction fetch channel. Figure 3 As shown, in this embodiment, the multiple microinstruction queues include two microinstruction queues, namely UOPQ-0 and UOPQ-1.

[0076] like Figure 3 As shown, each microinstruction slot can be represented by a slot. Figure 3 And the number of microinstructions allocated by slot in the subsequent diagrams, that is, each slot corresponds to one microinstruction.

[0077] For example, Figure 3 As shown in the figure, the write bandwidth of the two channels is different. The write bandwidth of the instruction decode channel takes 4 microinstructions as an example, corresponding to slots 0 to 3 in the instruction decode channel; the write bandwidth of the OC instruction fetch channel takes 8 microinstructions as an example, corresponding to slots 0 to 7 in the OC instruction fetch channel. Figure 3 As shown, each microinstruction queue (UOPQ-0 and UOPQ-1) has four write ports, corresponding to slot-0 to slot-3 of UOPQ-0 and slot-4 to slot-7 of UOPQ-1 respectively.

[0078] For example, Figure 3As shown in , if the source of the written microinstructions is the instruction decoding channel, the 4 microinstructions from the instruction decoding channel are evenly distributed to the 2 microinstruction queues. Figure 3 As shown, the microinstructions corresponding to slots 0 and 1 in the instruction decode channel are written into slots 0 and 1 of UOPQ-0, and the microinstructions corresponding to slots 2 and 3 in the instruction decode channel are written into slots 4 and 5 of UOPQ-1. If the microinstructions come from the OC instruction fetch channel, the 8 microinstructions are evenly distributed to the two microinstruction queues. For example, the microinstructions corresponding to slots 0 to 3 in the OC instruction fetch channel are written into slots 0 to 3 of UOPQ-0, and the microinstructions corresponding to slots 4 to 7 in the OC instruction fetch channel are written into slots 4 to 7 of UOPQ-1.

[0079] Figure 3 Only one example of evenly distributing microinstructions from the same microinstruction source is shown. The correspondence between the slot numbers in the microinstruction source and the slot numbers in the microinstruction queue is not unique.

[0080] In addition, the scheme for allocating microinstructions to multiple microinstruction queues may vary depending on the number of microinstruction queues and the bandwidth of different microinstruction sources, and the embodiments of the present disclosure do not limit this.

[0081] Figure 4 A schematic block diagram of an instruction distribution device provided by at least one embodiment of the present disclosure is Figure 2 A specific example of an instruction distribution device in FIG.

[0082] like Figure 4 As shown, the instruction distribution device 400 is used in the pipeline of the processor core, including a write selection module 410, multiple microinstruction queues 4201-420n (n is a positive integer greater than 1), and a read allocation module 430. The write selection module 410, the multiple microinstruction queues 4201-420n, and the read allocation module 430 are connected in sequence.

[0083] For example, Figure 4 As shown, the multiple microinstruction queues 4201 - 420n may be represented as microinstruction queues numbered 4201 , 4202 , . . . and 420n , respectively.

[0084] For example, Figure 4 As shown, the read allocation module 430 includes a reordering unit 431, a first determining unit 432, and a distributing unit 433. The reordering unit 431, the first determining unit 432, and the distributing unit 433 are connected in sequence.

[0085] For example, the reordering unit 431 is configured to read microinstructions from the plurality of microinstruction queues 4201-420n and reorder the read microinstructions according to an actual instruction order. For example, the actual instruction order refers to the original static order of instructions fetched by the front end of the pipeline, i.e., the address order of the instructions fetched. When writing these microinstructions to the plurality of microinstruction queues 4201-420n, for example, adjacent microinstructions in the actual instruction order may be written to different microinstruction queues. In this case, when reading them from the different microinstruction queues, their actual order can be restored through the reordering operation.

[0086] For example, the first determination unit 432 is configured to determine at least one microinstruction group including a target microinstruction group based on the reordered microinstructions and preset constraints, where the "target microinstruction group" refers to the microinstruction group that is the object of operation. For example, in some embodiments, the preset constraints may include instruction attribute information and / or instruction execution information. For example, the preset constraints may include only instruction attribute information, only instruction execution information, or both instruction attribute information and instruction execution information. For example, instruction attribute information may include instruction length and data dependency between instructions, etc.; instruction execution information may include the type and execution status of subsequent execution units, etc.

[0087] For example, the first determining unit 432 may determine a plurality of microinstruction groups, where the plurality of microinstruction groups include a target microinstruction group.

[0088] For example, the dispatch unit 433 is configured to dispatch the target microinstruction group. For example, the dispatch unit 433 can dispatch the target microinstruction group to the execution units of the pipeline.

[0089] The relevant description of the above-mentioned write selection module 410 and the multiple microinstruction queues 4201~420n can be found in Figure 2 The corresponding description is omitted here.

[0090] Figure 5 A schematic diagram of a read allocation module according to at least one embodiment of the present disclosure is provided. Figure 4 A specific example of a working read allocation module is provided.

[0091] for Figure 4 In the embodiment shown, after the first determining unit determines at least one microinstruction group including the target microinstruction group, the dispatching unit dispatches the target microinstruction group.

[0092] For example, Figure 5 As shown, the dispatch unit is further configured to dispatch the target microinstruction group through the read pointer. For example, after the target microinstruction group is dispatched, the read pointer points to the next valid microinstruction position of the target microinstruction group.

[0093] like Figure 5 As shown, each dispatch can be divided into three cases: a, b, and c. In each case, two rows of slots (slot-0 to slot-7) represent the microinstructions read from the microinstruction queue in two steps. That is, slots-0 to slot-7 in line 1 represent the microinstructions read from the microinstruction queue this time, and slots-0 to slot-7 in line 2 represent the microinstructions read from the microinstruction queue next time. The read pointer represents the starting position of the target microinstruction group, that is, the position of the microinstruction currently to be dispatched.

[0094] Figure 5 The gray slots in the following figures represent invalid instructions that may exist in the pipeline, such as "bubbles" in the pipeline. Invalid instructions mean that there are no valid instructions in the current slot, resulting in idleness.

[0095] like Figure 5 As shown, the read pointer can be divided into the following three cases:

[0096] Case a: After completing the dispatch of the microinstruction group (GROUP-0 in a), the dispatch unit dispatches the target microinstruction group (GROUP-1 in a) from the microinstructions read this time. In other words, the two dispatched microinstruction groups (GROUP-0 and GROUP-1) are microinstructions read from the same microinstruction queue at the same time, and the read pointer is still at the microinstruction read from the microinstruction queue at the same time (LINE 1).

[0097] Case b: After completing the dispatch of the microinstruction groups (Group-0 and Group-1 in b), the dispatch unit dispatches the target microinstruction group (Group-2 in b) from the next microinstruction read. In other words, the two dispatched microinstruction groups (Group-1 and Group-2) are microinstructions read from the microinstruction queue at different times, and the read pointer is located in the microinstruction read from the next microinstruction queue (LINE 2).

[0098] Case c: Similar to case a, after completing the dispatch of the microinstruction group (GROUP-0 in c), the dispatch unit dispatches the target microinstruction group (GROUP-1 in c) from the microinstructions read this time. The target microinstruction groups (GROUP-0 and GROUP-1) for both dispatches are still the microinstructions read from the microinstruction queue at the same time, and the read pointer is still at the microinstructions read from the microinstruction queue at the same time (LINE 1). The only difference is that the target microinstruction group (GROUP-1 in c) contains an invalid instruction.

[0099] like Figure 5As shown, invalid instructions exist in both case b (slot 7 in b) and case c (slots 6 and 7 in c). Targeted microinstruction relocation (or circuit design) is required to send valid instructions to the execution unit. Furthermore, because target microinstruction groups consist of microinstructions that span two reads, as in cases a and c, the read dispatch module needs to add registers to cache the microinstructions in the target microinstruction group that were previously read from the microinstruction queue.

[0100] For example, in at least one embodiment, the first determining unit further includes a microinstruction register. The microinstruction register is configured to store the reordered microinstructions read for the first time when the target microinstruction group is obtained based on the reordered microinstructions read twice.

[0101] Figure 6 A schematic diagram of an instruction distribution device provided in at least one embodiment of the present disclosure is provided. Figure 6 for Figure 4 A specific example of an instruction distribution device is shown.

[0102] like Figure 6 As shown, the instruction distribution device 600 includes a write selection module 610, a microinstruction queue UOPQ-0 and a microinstruction queue UOPQ-1, and a read allocation module 630, and the above modules are connected in sequence.

[0103] like Figure 6 As shown, the write select module 610 distributes microinstructions from the instruction decode path and / or the OC instruction fetch path to UOPQ-0 and UOPQ-1 based on path selection and microinstruction order. For example, if the instruction decode path bandwidth is 4 microinstructions and the OC instruction fetch path bandwidth is 8 microinstructions, the write bandwidth of the microinstruction queue is 8 microinstructions.

[0104] like Figure 6 As shown, the microinstruction queue UOPQ-0 and the microinstruction queue UOPQ-1 are configured to cache written microinstructions.

[0105] like Figure 6 As shown, the read allocation module 630 includes a reordering unit 631 , a first determining unit 632 , and a distributing unit 633 .

[0106] like Figure 6 As shown, the reorder unit 631 reads microinstructions from UOPQ-0 and UOPQ1 through the read control, and reorders the read microinstructions according to the actual instruction order. For example, the read bandwidth of UOPQ-0 and UOPQ1 is 3 microinstructions, which means that each read operation can read 3 microinstructions from the microinstruction queue.

[0107] like Figure 6 As shown, the first determining unit 632 determines at least one microinstruction group including the target microinstruction group in the read microinstructions according to the static constraints and the dynamic constraints, that is, Figure 6 "Define microinstruction groups" in . For example, static constraints can be fixed rules that can be determined at the instruction decoding stage, which are directly related to the processor hardware design and instruction set architecture characteristics and do not depend on the runtime state. For example, dynamic constraints can be rules that are adjusted in real time according to the current state of the processor at runtime, relying on information such as pipeline feedback, resource utilization, and speculative execution status to optimize the scheduling and distribution of microinstruction groups. For example, static constraints can be the above-mentioned instruction attribute information. For another example, dynamic constraints can be the above-mentioned instruction execution information.

[0108] like Figure 6 As shown, the distribution unit 633 distributes the target microinstruction group. For example, when distributing the target microinstruction group (such as GROUP 0), the distribution unit 633 can dynamically match it to an idle execution unit and port based on the operation type of the microinstruction (such as arithmetic and logical operations, memory access, floating-point operations). If a port conflict occurs (such as two microinstructions competing for the same arithmetic and logical unit port), the undistributed microinstructions will be temporarily saved in the distribution unit 633, waiting for resource release. The distribution unit 633 supports a multi-issue mechanism, allowing multiple independent microinstructions to be distributed to different ports in parallel within the same cycle. It can also simultaneously adopt an out-of-order scheduling strategy to allow non-dependent instructions to bypass blocking operations and execute in advance to improve parallelism.

[0109] The instruction distribution device provided in at least one embodiment of the present disclosure also adopts the design methods of "determining the microinstruction group after writing into the microinstruction queue" and "using the read pointer to distribute instructions". Without sacrificing the processor's main frequency, for example, without increasing the single microinstruction queue read port, the bandwidth of instruction distribution is increased, thereby improving processor performance.

[0110] Figure 7 A schematic block diagram of another instruction distribution device provided in at least one embodiment of the present disclosure is Figure 2 Another specific example of an instruction distribution device is provided.

[0111] like Figure 7 As shown, the instruction dispatching device 700 includes a write selection module 710, multiple microinstruction queues 720, and a read allocation module 730. The write selection module 710, multiple microinstruction queues 7201-720n (n is a positive integer greater than 1), and the read allocation module 730 are connected in sequence.

[0112] For example, Figure 7 As shown, the write selection module 710 includes a second determination unit 711 and an allocation unit 712 .

[0113] For example, Figure 7 As shown, the multiple microinstruction queues 7201 - 720n may be respectively represented as microinstruction queues numbered 7201 , 7202 , . . . and 720n .

[0114] For example, in at least one embodiment of the present disclosure, the second determining unit 711 is configured to determine at least one microinstruction group in the microinstructions according to preset constraints. For example, in at least one embodiment of the present disclosure, the allocating unit 712 is configured to write the microinstructions in the at least one microinstruction group into the plurality of microinstruction queues 720 1 -720 n. As described above, the preset constraints may include instruction attribute information and / or instruction execution information.

[0115] The relevant description of the above-mentioned multiple microinstruction queues 720 and the read allocation module 730 can be found in Figure 2 The corresponding description is omitted here.

[0116] The instruction distribution device provided by at least one embodiment of the present disclosure defines a microinstruction group before writing microinstructions into multiple microinstruction queues, and adopts a method such as writing microinstruction group boundary information to avoid writing invalid instructions into the microinstruction queues, thereby saving circuit overhead.

[0117] Figure 8A A schematic diagram of the operation of a distribution unit provided in at least one embodiment of the present disclosure is provided. Figure 8B Another working schematic diagram of a distribution unit provided by at least one embodiment of the present disclosure. Figure 8A and Figure 8B for Figure 7 Two specific examples of how the allocation unit works.

[0118] like Figure 8A and Figure 8B As shown, the multiple microinstruction queues include UOPQ-0 and UOPQ-1, and the write bandwidth of each microinstruction queue is 3 microinstructions.

[0119] For example, the allocation unit can be further configured to allocate the microinstructions in at least one microinstruction group to a plurality of microinstruction queues according to a preset mapping relationship. The preset mapping relationship can be a fixed allocation method. For example, a fixed number and / or a fixed number of microinstructions are allocated to a fixed microinstruction queue. For example, Figure 8A As shown, the allocation unit can allocate the microinstructions corresponding to slot-0 to slot-2 to UOPQ-0, and allocate the microinstructions corresponding to slot-3 to slot-5 to UOPQ-1.

[0120] For example, the allocation unit can be further configured to dynamically allocate the microinstructions in at least one microinstruction group to multiple microinstruction queues. For example, the dynamic allocation can be dynamically allocated to a microinstruction queue based on runtime conditions (such as load, dependency, resource availability). This allocation scheme can make full use of every entry in the microinstruction queue and will not write invalid microinstructions into the microinstruction queue. For example, Figure 8B As shown, the microinstructions in at least one microinstruction group are rearranged and written into UOPQ-0 and UOPQ-1. Figure 8B As shown, each microinstruction can be written into UOPQ-0 or UOPQ-1.

[0121] When writing microinstructions into the microinstruction queue, the valid microinstruction group boundaries need to be written into the microinstruction queue as well, so as to facilitate determining the microinstruction group when reading microinstructions from the microinstruction queue. For example, the dispatch unit can also be configured to record the boundary information of each microinstruction group.

[0122] Figure 9A A schematic diagram of a microinstruction queue provided by at least one embodiment of the present disclosure is provided. Figure 9B Another schematic diagram of a microinstruction queue provided in accordance with at least one embodiment of the present disclosure. Figure 9A and Figure 9B These are two specific examples of writing the valid microinstruction group boundary into the microinstruction queue.

[0123] For example, Figure 9A and Figure 9B As shown, the microinstruction queue can store microinstruction decoding information and microinstruction boundary information. For example, the microinstruction decoding information may include information such as microinstruction opcode, operand source and destination, etc. The microinstruction boundary information can be stored in the microinstruction queue in the following manner.

[0124] For example, in at least one embodiment of the present disclosure, the allocation unit may be further configured to write boundary information of each microinstruction group into a plurality of microinstruction queues, each microinstruction queue including a plurality of entries, each entry including a flag bit. For example, the flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

[0125] For example, Figure 9AAs shown, the microinstruction queue can contain multiple entries, each of which defines the microinstruction group boundary and marks the microinstruction group boundary of the last microinstruction in the microinstruction group to facilitate the determination of the target microinstruction group for distribution. Each entry can include microinstruction decoding information and microinstruction group boundary information. The boundary information includes a flag bit, which can be set to 1 bit. When the microinstruction is the end position of the microinstruction group (that is, the last instruction in the microinstruction group), the bit is set to 1, otherwise it remains 0. It should be noted that the embodiment of the present disclosure does not limit the length and configuration of the above-mentioned flag bit.

[0126] For example, the allocation unit may be further configured to write boundary information of each microinstruction group into a microinstruction quantity queue, which is configured to store the number of microinstructions of each microinstruction group stored in each microinstruction queue, wherein the boundary information includes the number of microinstructions.

[0127] For example, the microinstruction quantity queue may be one or more of a plurality of microinstruction queues, that is, the plurality of microinstruction queues may include a microinstruction quantity queue.

[0128] For example, Figure 9B As shown, the multiple microinstruction queues may include UOPQ-0, UOPQ-1, and UOPQ-2. UOPQ-0 and UOPQ-1 serve as microinstruction queues to store microinstruction decoding information, and UOPQ-2 serves as a microinstruction quantity queue to store the number of microinstructions in a microinstruction group, that is, each microinstruction group stores the number of microinstructions in each microinstruction group in UOPQ-0 or UOPQ-1.

[0129] For example, the read allocation module may further include a dispatch unit, wherein the dispatch unit is further configured to obtain a target microinstruction group and perform a dispatch operation based on the boundary information and the microinstructions read from the plurality of microinstruction queues.

[0130] For example, in Figure 9A In the boundary information storage method shown in FIG, the dispatch unit reads the flag bit in each entry in the microinstruction queue to determine the boundary of the microinstruction group, thereby obtaining the target microinstruction group and performing the dispatch operation. Figure 9B In the boundary information storage method shown, when the dispatch unit reads the microinstruction queue, it needs to read the values ​​of UOPQ-0 / 1 / 2. Based on the number of microinstructions in the microinstruction group stored in UOPQ-2, the corresponding microinstructions are read from UOPQ-0 / 1. UOPQ-0 / 1 is read in units of microinstructions, while UOPQ-2 is read in units of microinstruction groups.

[0131] Figure 10A schematic diagram of another instruction distribution device provided in at least one embodiment of the present disclosure, Figure 10 for Figure 7 A specific example of an instruction distribution device is shown.

[0132] like Figure 10 As shown, the instruction distribution device 1000 includes a write selection module 1010 , a microinstruction queue UOPQ- 0 and a microinstruction queue UOPQ- 1 , and a read allocation module 1030 .

[0133] like Figure 10 As shown, the write select module 1010 distributes microinstructions from the instruction decode path and the OC instruction fetch path to the microinstruction queue UOPQ-0 and microinstruction queue UOPQ-1 based on path selection and microinstruction order. For example, the instruction decode path bandwidth is 4 microinstructions (slots 0 to 3), the OC instruction fetch path bandwidth is 8 microinstructions (slots 0 to 7), and the write bandwidth of the microinstruction queue is 8 microinstructions (slots 0 to 7).

[0134] like Figure 10 As shown, the write selection module 1010 includes a second determination unit 1011 and an allocation unit 1012. For example, the second determination unit 1011 determines at least one microinstruction group from the microinstructions from the instruction decoding channel and the OC instruction fetch channel according to the static constraints and the dynamic constraints, that is, Figure 10 The allocation unit 1012 allocates the microinstructions in the at least one microinstruction group that has been determined to the microinstruction queue UOPQ-0 and the microinstruction queue UOPQ-1. For example, the allocation method can be referred to above. Figure 8A and Figure 8B The examples described are not repeated here.

[0135] like Figure 10 As shown, the multiple microinstruction queues may be microinstruction queue UOPQ-0 and microinstruction queue UOPQ-1 (or more microinstruction queues). The structure and configuration of the microinstruction queues can be referred to above. Figure 9A and Figure 9B The example described is not repeated here. The read bandwidth of each microinstruction queue is 3 microinstructions (slot-0 to slot-2).

[0136] like Figure 10 As shown, the read allocation module 1030 includes a distribution unit 1031, which determines the target microinstruction group from the microinstruction group read from the microinstruction queue and distributes it to the execution unit, that is, Figure 10 "Determine the microinstruction group to be distributed" in the instruction distribution. The instruction distribution bandwidth is 6 microinstructions (slot-0 to slot-5).

[0137] At least one embodiment of the present disclosure further provides an instruction distribution method. Figure 11 A schematic flow chart of an instruction distribution method provided in at least one embodiment of the present disclosure, which method may correspond to Figure 1 、 Figure 4 or Figure 7 The instruction distribution device shown.

[0138] like Figure 11 As shown, the instruction distribution method provided by at least one embodiment of the present disclosure includes at least steps S1110 to S1120. For example, the instruction distribution method can be applied to the instruction distribution device provided by any of the above embodiments of the present disclosure.

[0139] Step S1110: writing the microinstructions into a plurality of microinstruction queues, wherein the plurality of microinstruction queues are configured to cache the written microinstructions.

[0140] Step S1120: reading microinstructions from a plurality of microinstruction queues, obtaining a target microinstruction group to be distributed this time based on the read microinstructions, and performing a distribution operation.

[0141] For example, in at least one embodiment of the instruction distribution method, step S1110 may further include: writing the microinstructions into a plurality of microinstruction queues according to a preset mapping relationship.

[0142] For example, in at least one embodiment of the instruction distribution method, step S1110 may further include: when the multiple microinstruction queues are two microinstruction queues, writing microinstructions from the same microinstruction source into the two microinstruction queues evenly according to a preset mapping relationship.

[0143] For example, in at least one embodiment of the instruction distribution method, step S1120 may further include steps S1121 - S1123 .

[0144] Step S1121: read microinstructions from multiple microinstruction queues, and reorder the read microinstructions according to the actual instruction sequence.

[0145] Step S1122: Determine at least one microinstruction group including the target microinstruction group according to the reordered microinstructions and the preset constraints.

[0146] Step S1123: Distribute the target microinstruction group.

[0147] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, step S1123 may further include: distributing the target microinstruction group through a read pointer, wherein, after the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

[0148] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, step S1122 may further include: when the target microinstruction group is obtained based on the reordered microinstructions read twice, storing the reordered microinstructions read for the first time through the microinstruction register.

[0149] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, step S1110 may further include steps S1111 - S1112 .

[0150] Step S1111: Determine at least one microinstruction group in the microinstructions according to preset constraints.

[0151] Step S1112: Write the microinstructions in at least one microinstruction group into a plurality of microinstruction queues.

[0152] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, the preset constraints in step S1111 or step S1122 include instruction attribute information and / or instruction execution information.

[0153] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, step S1112 may further include: allocating microinstructions in at least one microinstruction group to multiple microinstruction queues according to a preset mapping relationship.

[0154] For example, in the instruction distribution method provided by at least one embodiment of the present disclosure, step S1112 may further include: dynamically allocating microinstructions in at least one microinstruction group to multiple microinstruction queues.

[0155] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, the method may further include: recording boundary information of each microinstruction group.

[0156] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, step S1112 may further include: writing the boundary information of each microinstruction group into multiple microinstruction queues, each microinstruction queue including multiple entries, each entry including a flag bit, wherein the flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

[0157] For example, in the instruction distribution method provided in at least one embodiment of the present disclosure, step S1112 may further include: writing the boundary information of each microinstruction group into the microinstruction quantity queue, the microinstruction quantity queue is configured to store the number of microinstructions of each microinstruction group stored in each microinstruction queue respectively, and the boundary information includes the number of microinstructions.

[0158] For example, the instruction distribution method provided by at least one embodiment of the present disclosure may further include step S1113.

[0159] Step S1113: According to the boundary information and the microinstructions read from the plurality of microinstruction queues, a target microinstruction group is obtained and a dispatch operation is performed.

[0160] It should be noted that, for the relevant content of the functions or beneficial effects of each step in the instruction distribution method provided in any embodiment of the present disclosure, for example, reference can be made to the relevant description of the instruction distribution device provided in any embodiment of the present disclosure, and no further details will be given here.

[0161] It should also be noted that, in various embodiments of the present disclosure, the execution order of the various steps of the instruction distribution method is not limited. Although the execution process of each step is described above in a specific order, this does not constitute a limitation on the embodiments of the present disclosure. The various steps in the instruction distribution method can be executed serially or in parallel, which can be determined according to actual needs.

[0162] For example, compared with the above description, the instruction distribution method provided by at least one embodiment of the present disclosure may also include more or fewer steps, and the embodiments of the present disclosure are not limited to this.

[0163] Figure 12 A schematic block diagram of a processor provided for at least one embodiment of the present disclosure.

[0164] like Figure 12 As shown, the processor 1200 includes an instruction distribution device 1210. The instruction distribution device 1210 may be the instruction distribution device provided by any of the above embodiments of the present disclosure.

[0165] For example, the processor 1200 may be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing capabilities and / or program execution capabilities.

[0166] For example, in the case where the processor 1200 is a central processing unit (CPU), the CPU includes a pipeline, which includes units or components such as branch prediction, instruction fetch, decoding, emission and renaming, execution unit, and instruction submission. For example, the emission and renaming unit includes the above-mentioned instruction distribution device 1210.

[0167] For example, in embodiments of the present disclosure, the central processing unit (CPU) may employ an X86 architecture, an ARM architecture, a RISC architecture (e.g., RISC-V), a MIPS architecture, or the like. Processor 1200 may be a general-purpose processor or a dedicated processor, and may be a single-core processor or a multi-core processor. The processors in embodiments of the present disclosure may be processors of any architecture and any instruction set, and are not limited in this disclosure.

[0168] At least some embodiments of the present disclosure further provide an electronic device, which includes the processor of any of the above embodiments.

[0169] Figure 13 A schematic block diagram of an electronic device provided in accordance with at least one embodiment of the present disclosure.

[0170] like Figure 13 As shown, the electronic device 1300 includes a processor 1310. The relevant description of the processor 1310 can be found in Figure 12 The corresponding description of the processor 1200 is not repeated here.

[0171] Figure 14 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0172] The electronic devices in the embodiments of the present disclosure may include mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), vehicle-mounted terminals (e.g., vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. Figure 14 The electronic device 1400 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0173] For example, Figure 14 As shown, in some examples, electronic device 1400 includes a processor 1401 (e.g., a central processing unit, a graphics processing unit, etc.). Processor 1401 can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 1402 or programs loaded from storage device 1408 into random access memory (RAM) 1403. For example, processor 1401 can be the processor provided in any of the above-mentioned embodiments. RAM 1403 also stores various programs and data required for the operation of the computer system. Processor 1401, ROM 1402, and RAM 1403 are connected to each other via a bus 1404. An input / output (I / O) interface 1405 is also connected to bus 1404.

[0174] For example, the following components can be connected to the I / O interface 1405: an input device 1406 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1407 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1409 which can also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1409 can allow the electronic device 1400 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. The drive 1410 is also connected to the I / O interface 1405 as needed. Removable media 1411, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1410 as needed, so that the computer program read therefrom can be installed into the storage device as needed. Although Figure 14 The electronic device 1400 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0175] For example, the electronic device 1400 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1409 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0176] For example, the electronic device 1400 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0177] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0178] There are a few points to note:

[0179] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0180] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0181] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An instruction distribution device, comprising: Write selection module, multiple microinstruction queues and read allocation module; wherein, The write selection module is configured to write microinstructions into the plurality of microinstruction queues; The plurality of microinstruction queues are configured to cache written microinstructions; The read dispatch module is configured to read microinstructions from the plurality of microinstruction queues, obtain a target microinstruction group to be dispatched this time based on the read microinstructions, and perform a dispatch operation.

2. The instruction distribution device according to claim 1, wherein: The write selection module is further configured to write the microinstructions into the multiple microinstruction queues according to a preset mapping relationship.

3. The instruction distribution device according to claim 2, wherein: The write selection module is further configured to, when the multiple microinstruction queues are two microinstruction queues, write microinstructions from the same microinstruction source into the two microinstruction queues evenly according to a preset mapping relationship.

4. The instruction distribution device according to claim 1, wherein: The read allocation module includes: a reordering unit configured to read microinstructions from the plurality of microinstruction queues and reorder the read microinstructions according to an actual instruction order; A first determining unit is configured to determine at least one microinstruction group including the target microinstruction group according to the reordered microinstructions and preset constraints; and The distribution unit is configured to distribute the target microinstruction group.

5. The instruction distribution device according to claim 4, wherein: The dispatch unit is further configured to dispatch the target microinstruction group by reading a pointer, After the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

6. The instruction distribution device according to claim 5, wherein: The first determining unit further includes a microinstruction register, wherein the microinstruction register is configured to store the reordered microinstructions read for the first time when the target microinstruction group is obtained based on the reordered microinstructions read twice.

7. The instruction distribution device according to claim 1, wherein: The write selection module includes: a second determining unit configured to determine at least one microinstruction group in the microinstructions according to a preset constraint; and The dispatch unit is configured to write the microinstructions in the at least one microinstruction group into the plurality of microinstruction queues.

8. The instruction distribution device according to claim 4 or 7, wherein: The preset constraints include instruction attribute information and / or instruction execution information.

9. The instruction distribution device according to claim 7, wherein: The allocation unit is further configured to allocate the microinstructions in the at least one microinstruction group to the multiple microinstruction queues according to a preset mapping relationship.

10. The instruction distribution device according to claim 7, wherein: The dispatch unit is further configured to dynamically dispatch the microinstructions in the at least one microinstruction group to the plurality of microinstruction queues.

11. The instruction distribution device according to claim 7, wherein: The dispatch unit is further configured to record boundary information of each microinstruction group.

12. The instruction distribution device according to claim 11, wherein: The allocation unit is further configured to write the boundary information of each microinstruction group into the multiple microinstruction queues, each microinstruction queue includes multiple entries, each entry includes a flag bit, The flag bit indicates whether the microinstruction stored in the corresponding entry is the last microinstruction in each microinstruction group, and the boundary information includes the flag bit.

13. The instruction distribution device according to claim 11, further comprising a microinstruction number queue, in, The allocation unit is further configured to write the boundary information of each microinstruction group into the microinstruction quantity queue, The microinstruction quantity queue is configured to store the quantity of microinstructions stored in each microinstruction queue of each microinstruction group, and the boundary information includes the quantity of microinstructions.

14. The instruction distribution device according to any one of claims 11 to 13, wherein: The read allocation module further includes: The dispatch unit is further configured to obtain the target microinstruction group and perform the dispatch operation according to the boundary information and the microinstructions read from the multiple microinstruction queues.

15. A method for distributing instructions, comprising: Writing the microinstructions into a plurality of microinstruction queues, wherein the plurality of microinstruction queues are configured to cache the written microinstructions; Microinstructions are read from the plurality of microinstruction queues, a target microinstruction group to be distributed this time is obtained based on the read microinstructions, and a distribution operation is performed.

16. The instruction distribution method according to claim 15, wherein: Writing the microinstructions into the plurality of microinstruction queues comprises: The microinstructions are written into the multiple microinstruction queues according to a preset mapping relationship.

17. The instruction distribution method according to claim 15, wherein: The step of reading microinstructions from the plurality of microinstruction queues, obtaining a target microinstruction group to be distributed this time based on the read microinstructions, and performing a distribution operation includes: Reading microinstructions from the plurality of microinstruction queues and reordering the read microinstructions according to an actual instruction sequence; Determining at least one microinstruction group including the target microinstruction group according to the reordered microinstructions and the preset constraints; and The target microinstruction group is distributed.

18. The instruction distribution method according to claim 17, wherein: The distributing the target microinstruction group includes: distributing the target microinstruction group by reading a pointer, After the target microinstruction group is distributed, the read pointer points to the next valid microinstruction position of the target microinstruction group.

19. The instruction distribution method according to claim 15, wherein: Writing the microinstructions into the plurality of microinstruction queues comprises: determining at least one microinstruction group in the microinstructions according to preset constraints; and The microinstructions in the at least one microinstruction group are written into the plurality of microinstruction queues.

20. The instruction distribution method according to claim 19, wherein: Writing the microinstructions in the at least one microinstruction group into the plurality of microinstruction queues comprises: The microinstructions in the at least one microinstruction group are allocated to the multiple microinstruction queues according to a preset mapping relationship.

21. The instruction distribution method according to claim 19, wherein: Writing the microinstructions in the at least one microinstruction group into the plurality of microinstruction queues comprises: The microinstructions in the at least one microinstruction group are dynamically allocated to the plurality of microinstruction queues.

22. The instruction distribution method according to claim 19, further comprising: Record the boundary information of each microinstruction group.

23. A processor comprising the instruction distribution device according to any one of claims 1 to 14.

24. An electronic device comprising the processor according to claim 23.

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