Memory management method and electronic equipment

Abstract

The invention discloses a memory management method and electronic equipment, the method is executed by the electronic equipment, in the method, a hardware accelerator detects a first event, and the first event indicates that the probability of page missing abnormity of a first DMA memory used by a first application is larger than a first threshold value; in response to the first event, the hardware accelerator executes one or more of the following operations: searching and killing a first process of the first application; first data of the first application in the disk is written into the first DMA memory, a first memory page table is updated, and the first memory page table comprises mapping from a virtual address on the hardware accelerator side to a physical address on the first DMA memory side. In the implementation of the invention, the hardware accelerator can process the page missing abnormity possibly occurring in the DMA memory, and the memory management efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a memory management method and electronic device. Background Art

[0002] The central processing unit (CPU) of an electronic device and a hardware accelerator (e.g., a graphics processing unit (GPU)) in a system-on-chip (SoC) or other system-on-chip (SoC) can share memory (e.g., direct memory access (DMA) memory) to enable high-speed data transfer between the CPU and the hardware accelerator. The hardware accelerator uses a system memory management unit (SMMU) to map virtual addresses on the hardware accelerator side to physical addresses on the DMA memory side.

[0003] When the CPU or hardware accelerator accesses data in DMA memory, a page fault exception occurs if the data is not in the DMA memory. Because the SMMU lacks the hardware's ability to automatically handle page fault exceptions, the SMMU does not reclaim the data in the DMA memory managed by the SMMU to avoid page fault exceptions when the hardware accelerator accesses the DMA memory. This means that the data remains in the DMA memory, resulting in a heavy load on the DMA memory. This shows that memory management efficiency is low for SMMU-managed DMA memory. Summary of the Invention

[0004] Embodiments of the present application provide a memory management method and an electronic device to improve memory management efficiency.

[0005] In a first aspect, an embodiment of the present application provides a memory management method, which is applicable to an electronic device or a component (such as a unit / module, circuit or chip, etc.) in the electronic device. Taking the method applicable to an electronic device as an example, the method includes: a hardware accelerator of the electronic device detects a first event; wherein, the first event indicates that the probability of a page fault exception occurring in a first DMA memory used by a first application is greater than a first threshold; in response to the first event, the hardware accelerator performs a first operation; wherein, the first operation includes one or more of the following: killing the first process of the first application; writing the first data of the first application in the disk to the first DMA memory, and updating the first memory page table according to the first data in the first DMA memory, the first memory page table including a mapping of the virtual address on the hardware accelerator side to the physical address on the first DMA memory side.

[0006] In an embodiment of the present application, if the hardware accelerator determines that the probability of a page fault exception occurring in the DMA memory used by the application is greater than a first threshold value, and the first threshold value is greater than or equal to zero (the first threshold value may be pre-configured or defined by a standard), that is, a page fault exception may occur in the DMA memory used by the application, the hardware accelerator may handle the possible page fault exception by instructing the CPU to kill the process of the application; or, the hardware accelerator may swap out the data of the application in the DMA memory to the disk in advance, and handle the possible page fault exception by rewriting all or part of the data of the application in the disk to the DMA memory (for example, a full page write or a single page write) and updating the SMMU page table. In other words, the hardware accelerator can handle the possible page fault exception of the DMA memory, so the hardware accelerator can recycle the data of the application in the DMA memory when the load of the DMA memory is large, thereby improving memory management efficiency.

[0007] In one possible implementation, the first event includes the running state of the first application switching from a frozen state to a non-frozen state; and / or, the first event includes the data corresponding to the first virtual address to be accessed by the central processing unit (CPU) of the electronic device is not stored in the first DMA memory.

[0008] In this embodiment, a plurality of implementation methods are provided for the hardware accelerator to determine that the DMA memory used by the application may have a page fault exception. For example, the running state of the application switches from a frozen state to a non-frozen state, indicating that the probability of the user operating the application in a short period of time is high, and the probability of the CPU and the hardware accelerator accessing part or all of the data of the application in the DMA memory in a short period of time is high. If the data of the application accessed by the CPU and the hardware accelerator is not in the DMA memory, the DMA memory will have a page fault exception. For another example, the virtual address to be accessed by the CPU is monitored. If the data corresponding to the virtual address is not in the DMA memory, the DMA memory will have a page fault exception. This makes the way in which the hardware accelerator determines that the DMA memory may have a page fault exception more flexible.

[0009] In one possible implementation, the first data is the second data or the third data, the second data includes the third data, the second data is all the data of the first application stored in the disk, and the third data is part of the data of the first application stored in the disk, and the part of the data is the data corresponding to the first virtual address to be accessed by the CPU of the electronic device.

[0010] In this embodiment, the hardware accelerator handles page fault exceptions that may occur in the DMA memory used by the application in various ways. For example, all the application data on the disk is rewritten to the DMA memory. Another example is rewriting part of the application data on the disk (i.e., the application data that the CPU wants to access) to the DMA memory, making the hardware accelerator more flexible in handling page fault exceptions that may occur in the DMA memory.

[0011] In one possible implementation, before the hardware accelerator detects the first event, the method further includes: the hardware accelerator detecting a second event; wherein the second event includes the running state of the first application switching from a non-frozen state to a frozen state; in response to the second event, the hardware accelerator swaps out the second data in the first DMA memory to the disk, and updates the first memory page table according to the second data on the disk.

[0012] In this embodiment, the hardware accelerator can manage the DMA memory used by the application based on the application's running state to ensure the performance of the application in the corresponding running state as much as possible. For example, if the application's running state switches from a non-frozen state to a frozen state, it means that the probability of the user operating the application in a short period of time is low, and the probability of the CPU and hardware accelerator accessing part or all of the application's data in the DMA memory in a short period of time is low. Therefore, the hardware accelerator can swap out part or all of the application's data in the DMA memory, such as swapping it out to disk, and update the SMMU page table, thereby reducing the load on the DMA memory.

[0013] In one possible implementation, the first DMA memory includes a first buffer queue, and the second data is stored in the first buffer queue; the hardware accelerator swaps out the second data in the first DMA memory to the disk, including: the hardware accelerator detects a third event; wherein the third event indicates that the data in the first DMA memory is no longer updated, and / or the identifier of each buffer area in the first buffer queue is a first identifier, and the first identifier is used to indicate that the data in the corresponding buffer area can be swapped out to the disk by the hardware accelerator; in response to the third event, the hardware accelerator swaps out the data in each buffer area in the first buffer queue to the disk.

[0014] In this embodiment, when the hardware accelerator swaps out part or all of the data of the application in the DMA memory used by the application to the disk, it can determine whether the part or all of the data is safe data, that is, data that the CPU and the hardware accelerator will not access in a short period of time. If it is safe data, the part or all of the data will be swapped out to the disk, thereby avoiding affecting the normal access of the CPU and the hardware accelerator. For example, the data in the DMA memory is no longer updated, indicating that the data in the DMA memory is in a stable state and will not be accessed by the CPU and the hardware accelerator in a short period of time. For another example, the identifier of each buffer area in the buffer queue storing the part or all of the data is the first identifier, indicating that the data in each buffer area in the buffer queue is in a stable state and will not be accessed by the CPU and the hardware accelerator in a short period of time.

[0015] In one possible implementation, the hardware accelerator updates the first memory page table based on the second data in the disk, including: the hardware accelerator deletes the mapping of the second virtual address to the first physical address in the first memory page table; wherein the second virtual address is the virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is the physical address corresponding to the second data on the first DMA memory side.

[0016] In this embodiment, after the hardware accelerator swaps out part or all of the data of the application in the DMA memory used by the application to the disk, it can delete the mapping related to the part or all of the data in the SMMU page table (i.e., unmap it). Since the hardware accelerator accesses the DMA memory through the SMMU page table, this avoids affecting the normal access of the hardware accelerator.

[0017] In a possible implementation, the first data is the second data, and the hardware accelerator writes the first data in the disk to the first DMA memory, including: the hardware accelerator writes the second data in the disk to a second buffer queue in the first DMA memory.

[0018] In this embodiment, a method is provided in which the hardware accelerator rewrites the application data in the disk into the DMA memory used by the application, for example, rewriting the data into a buffer queue of the DMA memory.

[0019] In one possible implementation, the method further includes: the hardware accelerator detects a fourth event; wherein the fourth event indicates that data in a first buffer area in a first buffer queue is different from data in a first buffer area in a second buffer queue, and / or data in a last buffer area in the first buffer queue is different from data in a last buffer area in the second buffer queue, and the first buffer queue is the buffer queue where the second data was located before being swapped out from the first DMA memory to the disk; in response to the fourth event, the hardware accelerator kills the first process of the first application.

[0020] In this embodiment, before the hardware accelerator swaps out part or all of the data of the application in the DMA memory used by the application to the disk, the part or all of the data is stored in the buffer queue 1 in the DMA memory. After the hardware accelerator rewrites part or all of the data of the application on the disk to the DMA memory, the part or all of the data is stored in the buffer queue 2 in the DMA memory. Therefore, the hardware accelerator determines whether the data read from the disk is correct data by comparing whether the data in the buffer queue 1 is the same as the data in the buffer queue 2. If they are not the same, it means that the data read from the disk is wrong data. The hardware accelerator can instruct the CPU to kill the process of the application to handle possible page fault exceptions. In addition, the hardware accelerator can only compare whether the data in the first buffer area and the last buffer area are the same, thereby improving the judgment efficiency of the hardware accelerator.

[0021] In one possible implementation, the method further includes: the hardware accelerator detecting a fifth event; wherein the fifth event indicates that the data in the first buffer area in the first buffer queue is the same as the data in the first buffer area in the second buffer queue, and the data in the last buffer area in the first buffer queue is the same as the data in the last buffer area in the second buffer queue, and the first buffer queue is the buffer queue where the second data was located before being swapped out from the first DMA memory to the disk; in response to the fifth event, the hardware accelerator updates the first memory page table according to the second data in the first DMA memory.

[0022] In this embodiment, before the hardware accelerator swaps out part or all of the data of the application in the DMA memory used by the application to the disk, the part or all of the data is stored in the buffer queue 1 in the DMA memory. After the hardware accelerator rewrites part or all of the data of the application in the disk to the DMA memory, the part or all of the data is stored in the buffer queue 2 in the DMA memory. Therefore, the hardware accelerator determines whether the data read from the disk is correct data by comparing whether the data in the buffer queue 1 is the same as the data in the buffer queue 2. If they are the same, it means that the data read from the disk is correct data, and the hardware accelerator can update the SMMU page table to avoid affecting the normal access of the hardware accelerator. In addition, the hardware accelerator can only compare whether the data in the first buffer area and the last buffer area are the same, thereby improving the judgment efficiency of the hardware accelerator.

[0023] In one possible implementation, the hardware accelerator updates the first memory page table according to the first data in the first DMA memory, including: the hardware accelerator adds a mapping of a second virtual address to a first physical address in the first memory page table; wherein the second virtual address is a virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is a physical address corresponding to the second data on the first DMA memory side.

[0024] In this embodiment, after the hardware accelerator rewrites part or all of the application data on the disk into the DMA memory used by the application, it can add a mapping related to the part or all of the data in the SMMU page table (i.e., remapping). Since the hardware accelerator accesses the DMA memory through the SMMU page table, this avoids affecting the normal access of the hardware accelerator.

[0025] In one possible implementation, the first data is the third data, and the hardware accelerator writes the first data in the disk to the first DMA memory, including: the hardware accelerator queries a second memory page table according to the first virtual address to obtain a third virtual address; wherein the second memory page table includes a mapping from the virtual address on the CPU side to the virtual address on the hardware accelerator side, and the third virtual address is the virtual address corresponding to the third data on the hardware accelerator side; the hardware accelerator accesses the third data in the disk according to the third virtual address, and writes the third data in the disk to the first DMA memory.

[0026] This embodiment provides a method for a hardware accelerator to rewrite application data on a disk that the CPU is accessing into DMA memory used by the application. For example, the hardware accelerator determines the virtual address of the data on the hardware accelerator based on a memory page table that maps virtual addresses on the CPU to virtual addresses on the hardware accelerator. Based on the virtual address of the data on the hardware accelerator, the hardware accelerator determines the storage area of ​​the data on the disk, thereby rewriting the data from the disk into the DMA memory.

[0027] In one possible implementation, the hardware accelerator updates the first memory page table based on the first data in the first DMA memory, including: the hardware accelerator adds a mapping of a third virtual address to a second physical address in the first memory page table; wherein the third virtual address is a virtual address corresponding to the third data on the hardware accelerator side, and the second physical address is a physical address corresponding to the third data on the first DMA memory side.

[0028] In this embodiment, after the hardware accelerator rewrites the data of the application to be accessed by the CPU in the disk into the DMA memory used by the application, it can add a mapping related to the data in the SMMU page table (i.e., remapping). Since the hardware accelerator accesses the DMA memory through the SMMU page table, it avoids affecting the normal access of the hardware accelerator.

[0029] In one possible implementation, the method further includes: when the first application is switched from the foreground to the background and the first application is not running a background task, the hardware accelerator determines that the running state of the first application is switched from a non-frozen state to a frozen state; or, when the first application is switched from the background to the foreground, or the first application is running a background task, the hardware accelerator determines that the running state of the first application is switched from a frozen state to a non-frozen state.

[0030] In this embodiment, multiple implementations of a hardware accelerator determining the running state of an application are provided. For example, if the application switches from the foreground to the background and is no longer running tasks, it means that the running state of the application switches from a non-frozen state to a frozen state. For another example, if the application switches from the background to the foreground, or if the application switches from the foreground to the background but is still running tasks, it means that the running state of the application switches from a frozen state to a non-frozen state. This makes the method for the hardware accelerator to determine the running state of an application more flexible.

[0031] In a second aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and one or more programs; wherein the one or more programs are stored in the memory, and the one or more programs include instructions, which, when executed by the processor, enable the electronic device to perform the method described in the first aspect or any possible design of the first aspect.

[0032] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which is used to store a computer program. When the computer program runs on a computer, the computer executes the method described in the first aspect or any possible design of the first aspect.

[0033] In a fourth aspect, an embodiment of the present application further provides a computer program product, comprising a computer program, which, when executed on a computer, enables the computer to execute the method described in the first aspect or any possible design of the first aspect.

[0034] In a fifth aspect, an embodiment of the present application also provides a chip system, comprising a processor and an interface, wherein the processor is used to call and run instructions from the interface so that the chip system executes the method described in the first aspect or any possible design of the first aspect.

[0035] The beneficial effects of the above-mentioned second to fifth aspects and their possible designs can refer to the description of the beneficial effects of the method described in the above-mentioned first aspect and any possible design thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0037] Figure 2 A schematic diagram of the software structure of an electronic device provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of implementing data transfer from a CPU to a hardware accelerator via DMA memory provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of a first DMA memory provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of a first DMA memory page fault exception provided in an embodiment of the present application;

[0041] Figure 6 A flowchart of a memory management method provided in an embodiment of the present application;

[0042] Figure 7 A schematic diagram of a first buffer queue provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of swapping out part or all of the data of a first application in a first DMA memory to a disk according to an embodiment of the present application;

[0044] Figure 9 An embodiment of the present application provides a schematic diagram of a first DMA memory page table;

[0045] Figure 10 A schematic diagram of a hardware accelerator managing a first DMA memory provided in an embodiment of the present application;

[0046] Figure 11 The embodiment of the present application provides a schematic diagram for comparing data in a first buffer queue and a second buffer queue;

[0047] Figure 12 A schematic diagram of another hardware accelerator managing a first DMA memory provided in an embodiment of the present application;

[0048] Figure 13 A schematic diagram of another hardware accelerator managing a first DMA memory provided in an embodiment of the present application;

[0049] Figure 14 A schematic diagram of writing part or all of the data of a first application in a disk to a first DMA memory provided by an embodiment of the present application;

[0050] Figure 15 A schematic diagram of the hardware structure of another electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0052] The technical solutions provided in the embodiments of the present application can be applied to electronic devices. The electronic devices can be mobile phones, tablet computers, desktop computers, laptop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices, and / or smart city devices. The embodiments of the present application do not impose any special restrictions on the specific types of the electronic devices.

[0053] For example, Figure 1 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application.

[0054] like Figure 1 As shown, the electronic device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180I, a touch sensor 180J, an ambient light sensor 180K, a bone conduction sensor 180L, etc.

[0055] It is understood that the structures illustrated in the embodiments of the present invention do not constitute specific limitations on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0056] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0057] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0058] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0059] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0060] The I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C busses. The processor 110 may be coupled to the touch sensor 180J, charger, flash, camera 193, etc. via different I2C bus interfaces. For example, the processor 110 may be coupled to the touch sensor 180J via the I2C interface, enabling communication between the processor 110 and the touch sensor 180J via the I2C bus interface, thereby implementing the touch function of the electronic device.

[0061] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface, enabling the function of answering calls through a Bluetooth headset.

[0062] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0063] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface, enabling the function of playing music through Bluetooth headphones.

[0064] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display 194 and the camera 193. MIPI interfaces include the camera serial interface (CSI) and the display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the electronic device's camera function. The processor 110 and the display 194 communicate via the DSI interface to implement the electronic device's display function.

[0065] The GPIO interface can be configured via software. The GPIO interface can be configured as either a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to the camera 193, display 194, wireless communication module 160, audio module 170, sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0066] USB port 130 is an interface that complies with USB standards and may be a Mini USB port, a Micro USB port, a USB Type-C port, or the like. USB port 130 can be used to connect a charger to charge an electronic device, transfer data between the electronic device and peripherals, connect headphones to play audio, and connect other electronic devices, such as augmented reality devices.

[0067] It is understood that the interface connection relationship between the modules illustrated in the embodiments of the present invention is only a schematic illustration and does not constitute a structural limitation of the electronic device. In other embodiments of the present application, the electronic device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0068] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the electronic device's wireless charging coil. While charging the battery 142, the charging management module 140 can also power the electronic device through the power management module 141.

[0069] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0070] The wireless communication function of the electronic device can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor.

[0071] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in an electronic device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0072] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied in electronic devices. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0073] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.) or displays an image or video through the display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0074] The wireless communication module 160 can provide wireless communication solutions for electronic devices, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. The wireless communication module 160 can be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0075] In some embodiments, the antenna 1 of the electronic device is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS) and / or satellite based augmentation system (SBAS).

[0076] The electronic device implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0077] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD). The display panel can also be made of an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini-LED, a micro-LED, a micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device can include one or N display screens 194, where N is a positive integer greater than one.

[0078] The electronic device can realize the shooting function through the ISP, camera 193, video codec, GPU, display 194 and application processor.

[0079] The ISP processes data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and converted into a visible image. The ISP can also perform algorithmic optimization on image noise, brightness, and color. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 193.

[0080] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then passes the electrical signal to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0081] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when an electronic device selects a frequency, the DSP performs a Fourier transform on the frequency energy.

[0082] Video codecs are used to compress or decompress digital video. Electronic devices may support one or more video codecs. This allows them to play or record videos in a variety of encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, and MPEG4.

[0083] The NPU is a neural network (NN) computing processor. Drawing on the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it rapidly processes input information and can continuously self-learn. The NPU enables intelligent cognitive applications in electronic devices, such as image recognition, face recognition, speech recognition, and text comprehension.

[0084] The internal memory 121 may include one or more random access memories (RAM) and one or more non-volatile memories (NVM).

[0085] Random access memory may include static random-access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM, for example, the fifth generation of DDR SDRAM is generally referred to as DDR5 SDRAM), etc.

[0086] Non-volatile memory may include disk storage devices and flash memory.

[0087] Flash memory can be divided into NOR FLASH, NAND FLASH, 3D NAND FLASH, etc. according to the operating principle; single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), etc. according to the storage cell potential level; universal flash storage (UFS) and embedded multi media card (eMMC) can be divided into UFS and embedded multi media card according to the storage specification.

[0088] The random access memory can be directly read and written by the processor 110, and can be used to store executable programs (such as machine instructions) of the operating system or other running programs, and can also be used to store user and application data.

[0089] The non-volatile memory may also store executable programs and user and application data, etc., and may be loaded into the random access memory in advance for direct reading and writing by the processor 110 .

[0090] The external memory interface 120 can be used to connect to an external non-volatile memory device to expand the storage capacity of the electronic device. The external non-volatile memory device communicates with the processor 110 via the external memory interface 120 to implement data storage. For example, files such as music and videos can be stored in the external non-volatile memory device.

[0091] The electronic device can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0092] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0093] The speaker 170A, also called a "speaker," is used to convert audio electrical signals into sound signals. The electronic device can listen to music or make hands-free calls through the speaker 170A.

[0094] The receiver 170B, also called a "handset", is used to convert audio electrical signals into sound signals. When the electronic device receives a call or voice message, the voice can be heard by placing the receiver 170B close to the human ear.

[0095] Microphone 170C, also known as "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device can be provided with at least one microphone 170C. In other embodiments, the electronic device can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device can also be provided with three, four or more microphones 170C to realize sound signal collection, noise reduction, and identification of sound sources, and realize directional recording function, etc.

[0096] The headphone jack 170D is used to connect a wired headphone and can be the USB interface 130 or a 3.5mm open mobile terminal platform (OMTP) standard interface or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0097] The pressure sensor 180A is used to sense pressure signals and convert the pressure signals into electrical signals.

[0098] The gyro sensor 180B may be used to determine the motion posture of the electronic device.

[0099] The air pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device calculates the altitude using the air pressure value measured by the air pressure sensor 180C to assist in positioning and navigation.

[0100] The magnetic sensor 180D includes a Hall sensor, and the electronic device can use the magnetic sensor 180D to detect the opening and closing of the flip cover.

[0101] The accelerometer 180E can detect the magnitude of an electronic device's acceleration in all directions (generally three axes). When the electronic device is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the electronic device's posture, enabling applications such as switching between landscape and portrait modes and pedometers.

[0102] Distance sensor 180F is used to measure distance. The electronic device can measure distance using infrared or laser. In some embodiments, when shooting a scene, the electronic device can use distance sensor 180F to measure distance to achieve fast focus.

[0103] The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector such as a photodiode.

[0104] The ambient light sensor 180K senses ambient light brightness. The electronic device can adaptively adjust the brightness of the display 194 based on the perceived ambient light. The ambient light sensor 180K can also be used to automatically adjust the white balance when taking photos. The ambient light sensor 180K can also work with the proximity sensor 180G to detect whether the electronic device is in a pocket to prevent accidental touches.

[0105] Fingerprint sensor 180H is used to collect fingerprints. Electronic devices can use the collected fingerprint characteristics to achieve fingerprint unlocking, access application locks, fingerprint photography, fingerprint answering calls, etc.

[0106] The temperature sensor 180I is used to detect temperature.

[0107] Touch sensor 180J, also known as a "touch-sensitive device," can be mounted on display screen 194. The touch sensor 180J and display screen 194 form a touch screen, also known as a "touchscreen." Touch sensor 180J detects touch operations applied to or near the touch sensor. The touch sensor can transmit the detected touch operations to an application processor to determine the type of touch event. Visual output related to the touch operations can be provided via display screen 194.

[0108] The bone conduction sensor 180L can acquire vibration signals.

[0109] Keys 190 include a power button, a volume button, and the like. Keys 190 may be mechanical keys or touch-sensitive keys. The electronic device may receive key inputs and generate key signal inputs related to user settings and function control of the electronic device.

[0110] Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (such as taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example: time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

[0111] The indicator 192 may be an indicator light, which may be used to indicate the charging status, power level changes, messages, missed calls, notifications, etc.

[0112] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to and separated from the electronic device by inserting it into or removing it from the SIM card interface 195. The electronic device can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. Electronic devices interact with the network through SIM cards to implement functions such as calls and data communications. In some embodiments, the electronic device uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device and cannot be separated from the electronic device.

[0113] For example, Figure 2 A schematic diagram of the software structure of an electronic device provided in an embodiment of the present application.

[0114] like Figure 2 As shown, the software structure of the electronic device can be a layered architecture. For example, the software can be divided into several layers, each with a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the operating system is divided into four layers: from top to bottom, the application layer, the application framework layer (framework, FWK), the runtime (runtime) and system library, and the kernel layer.

[0115] The application layer can include a series of application packages. Figure 2 As shown, the application layer may include camera, settings, skin module, user interface (UI), third-party applications, etc. Among them, third-party applications may include gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, short message, etc.

[0116] The application framework layer provides application programming interface (API) and programming framework for the application layer. The application framework layer may include some predefined functions. Figure 2 As shown, the application framework layer may include a window manager, a content provider, a view system, a phone manager, a resource manager, and a notification manager.

[0117] The window manager manages windowed applications. It can determine the display size, determine whether a status bar is present, lock the screen, and take screenshots. Content providers store and retrieve data and make it accessible to applications. This data can include video, images, audio, incoming and outgoing calls, browsing history and bookmarks, and phone books.

[0118] The view system includes visual controls, such as those for displaying text and images. The view system is used to build applications. A display interface can consist of one or more views. For example, a display interface containing a text notification icon might include a view for displaying text and a view for displaying images.

[0119] The phone manager is used to provide communication functions for electronic devices, such as call status management (including answering, hanging up, etc.).

[0120] The resource manager provides various resources for applications, such as localized strings, icons, images, layout files, video files, and so on.

[0121] The Notification Manager allows applications to display notifications in the status bar. These messages can be displayed briefly and then disappear automatically without user interaction. For example, the Notification Manager is used to notify users of completed downloads and message reminders. The Notification Manager can also display notifications in the top status bar of the system as icons or scrolling text, such as notifications from background applications, or as dialog windows on the screen. Examples include text messages in the status bar, beeps, vibrations on electronic devices, and flashing indicator lights.

[0122] The runtime includes the core library and the virtual machine. The runtime is responsible for the scheduling and management of the operating system.

[0123] The core library consists of two parts: one containing the Java language's callable functions and the other containing the operating system's core libraries. The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files in the application layer and application framework layer as binary files. The virtual machine manages object lifecycles, stack management, thread management, security and exception management, and garbage collection.

[0124] The system library can include multiple functional modules, such as surface manager, media libraries, 3D graphics processing library (such as OpenGL ES), 2D graphics engine (such as SGL), etc.

[0125] The surface manager is used to manage the display subsystem and provide fusion of 2D and 3D layers for multiple applications.

[0126] The media library supports playback and recording of a variety of common audio and video formats, as well as static image files. The media library can support a variety of audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc.

[0127] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0128] A 2D graphics engine is a drawing engine for 2D drawings.

[0129] The kernel layer is the layer between hardware and software. The kernel layer includes at least display driver, camera driver, audio driver, and sensor driver.

[0130] The hardware layer can include various sensors, such as accelerometers, gravity sensors, touch sensors, etc.

[0131] The electronic devices applicable to the embodiments of the present application are introduced above. The following introduces the relevant technical solutions involved in the embodiments of the present application.

[0132] 1) The central processing unit (CPU) of an electronic device and the hardware accelerators (such as GPU, NPU, codec, display subsystem (DSS), etc.) in the system-on-chip (SoC) of the electronic device can share memory (such as direct memory access (DMA) memory) to achieve high-speed data flow between the CPU and the hardware accelerator.

[0133] The hardware accelerator in the SoC is also known as the master internet protocol (master IP), or hardware IP. The CPU uses a memory management unit (MMU) to map virtual addresses on the CPU side to physical addresses on the DMA memory side. The MMU provides address translation based on the MMU page table.

[0134] The hardware accelerator uses a system memory management unit (SMMU) (also known as an input output memory management unit (IOMMU)) to implement the mapping of virtual addresses on the hardware accelerator side to physical addresses on the DMA memory side. That is, the SMMU is used to provide address translation based on the SMMU page table.

[0135] For example, Figure 3 This is a schematic diagram of a method for implementing data transfer from a CPU to a hardware accelerator via DMA memory provided in an embodiment of the present application. Figure 3 As shown, the CPU (such as image component, player component, codec interface, surface component, webview component) uses MMU for address translation as a producer to write data into DMA memory, and the hardware accelerator (such as picture decoder, codec, GPU, DSS) uses SMMU for address translation as a consumer to read data from DMA memory.

[0136] To increase the efficiency of asynchronous collaboration between the CPU and hardware accelerators, DMA memory often uses a buffer queue structure. A buffer queue is a queue structure that contains multiple buffer areas. Each buffer area in the buffer queue represents a DMA memory, so the buffer queue contains multiple DMA memories.

[0137] Taking the CPU and DSS as an example, after the CPU and GPU complete screen drawing, the CPU writes the data to a buffer area in the buffer queue (i.e., a DMA memory) by calling the surface component for display. At this point, the DSS continuously retrieves the buffer area with written data from the buffer queue and continuously refreshes it to the corresponding screen. At this point, the CPU and DSS complete a data flow through a buffer area (i.e., a DMA memory) in rotation.

[0138] 2) When the CPU or hardware accelerator accesses data in the DMA memory, if the data is not in the DMA memory, a page fault exception will occur. For example, when the CPU accesses data stored in the DMA memory, the CPU uses the MMU to search for the corresponding physical address based on the virtual address of the data accessed by the CPU on the CPU side, from the mapping relationship between the stored virtual address on the CPU side and the physical address on the DMA memory side (i.e., the MMU page table). If the corresponding physical address does not exist in the mapping relationship, it means that the data accessed by the CPU is not in the DMA memory, and a page fault exception occurs in the DMA memory. Among them, the MMU has the ability to automatically handle page fault exceptions in hardware, while the SMMU does not have the ability to automatically handle page fault exceptions in hardware.

[0139] For DMA memory managed by the SMMU, if the SMMU reclaims data from that DMA memory, a page fault exception will occur when the hardware accelerator accesses the data again. Because the SMMU lacks the hardware's ability to automatically handle page fault exceptions, to avoid page fault exceptions when the hardware accelerator accesses DMA memory, the SMMU does not reclaim the data from that DMA memory. This means that the data remains in the DMA memory, resulting in a heavy load on the DMA memory. This shows that memory management efficiency is low for DMA memory managed by the SMMU.

[0140] Currently, electronic device operating systems can solve the above problems in three ways, which are introduced below.

[0141] Method 1: The iOS system can use the chip's integrated MMU function to implement hardware-automated page fault exception handling on the hardware accelerator side. However, this method only works on chips with integrated MMU functions and is not applicable to chips without integrated MMU functions.

[0142] Method 2: The Android system can access the onTrimMemory interface and monitor memory load. This allows the application to execute a memory release method when the DMA memory load is high, freeing up some DMA memory. Although this method works on all chipsets, it relies heavily on the cooperation of the application developer (referred to as the app developer) and requires the application to actively access the onTrimMemory interface.

[0143] Method three: The Android system can use process killing to reclaim the data in the DMA memory used by the process. Although this method does not rely on the cooperation of the application developer, it sacrifices the user experience of the background cache.

[0144] In view of this, an embodiment of the present application provides a memory management method, which is used to improve memory management efficiency while taking into account chip versatility, application developer-friendly compatibility and user experience.

[0145] In the embodiments of this application, "when," "if," and "if" all indicate that the device will perform a corresponding action under certain objective circumstances. They do not limit the time, do not require the device to perform a judgment action when implemented, and do not imply any other limitations. Unless otherwise specified, "if" and "if" are interchangeable, and "when" and "under the circumstances" are interchangeable. "When" and "if" are interchangeable.

[0146] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0147] In the embodiments of the present application, the number of nouns, unless otherwise specified, means "singular noun or plural noun", that is, "one or more". "At least one" means one or more, and "plural" means two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " can indicate that the previous and next associated objects are in an "or" relationship. For example, A / B means: A or B. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0148] The ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish between multiple objects, and are not used to limit the size, content, order, timing, priority or importance of multiple objects. For example, the first event and the second event refer to two different events, and do not indicate the difference in priority or importance of the two events. For a technical feature, the technical features in the technical feature are distinguished by "A", "B", "C" and "D", and there is no order of precedence or order of size between the technical features described by "A", "B", "C" and "D". For example, Case A and Case B in this article are only to distinguish different contents, and do not limit the order of precedence or order of size, priority or importance, etc. between Case A and Case B.

[0149] The following describes the solution provided by the embodiment of the present application in detail with reference to the accompanying drawings. In the following description, the memory management method provided by the embodiment of the present application is applied to Figure 1-Figure 2 The electronic device shown is taken as an example.

[0150] To facilitate understanding of the embodiments of the present application, the CPU, hardware accelerator, first application and first DMA memory involved in the embodiments of the present application are first introduced below.

[0151] The electronic device may include a CPU and a hardware accelerator (also known as a hardware acceleration module or a hardware acceleration unit). The CPU may include an image component, a player component, a codec interface, a surface component, a network view component, etc. The hardware accelerator may include a GPU, an NPU, a codec, a DSS, etc. This embodiment of the present application is not limited to this.

[0152] The CPU can run one or more applications. Each application can correspond to one or more processes, and a process can include one or more threads executing tasks. The CPU and hardware accelerator can share memory (e.g., DMA memory) to enable high-speed data transfer between the CPU and the hardware accelerator for one or more applications running on the CPU.

[0153] That is, one or more applications running in the CPU can use the DMA memory to store the data of the application. The CPU can access the data of the application in the DMA memory by performing address translation through the MMU, that is, the MMU is used to provide an address translation function based on the MMU page table, and the MMU page table includes a mapping of the virtual address on the CPU side to the physical address on the DMA memory side. The hardware accelerator can access the data of the application in the DMA memory by performing address translation through the SMMU, that is, the SMMU is used to provide an address translation function based on the SMMU page table, and the SMMU page table includes a mapping of the virtual address on the hardware accelerator side to the physical address on the DMA memory side.

[0154] During a specific implementation, a first application running on the CPU can use a first DMA memory to store data of the first application, and the CPU and the hardware accelerator can share the first DMA memory to achieve high-speed data transfer between the CPU and the hardware accelerator. The first DMA memory may include one or more DMA memories.

[0155] Figure 4 A schematic diagram of a first DMA memory provided in an embodiment of the present application. Figure 4 As shown, the first DMA memory may be a buffer queue, which may include N buffer areas, namely buffer area 1, buffer area 2, buffer area 3, buffer area 4, ..., buffer area N. One buffer area may represent one DMA memory, that is, the first DMA memory may include N DMA memories, where N is a positive integer greater than or equal to 1.

[0156] The CPU can access the data of the first application in the first DMA memory based on the first MMU page table. The first MMU page table may include a mapping of a virtual address on the CPU side to a physical address on the first DMA memory side. For example, if data 1 of the first application is stored in buffer area 1 of the first DMA memory, the virtual address corresponding to data 1 of the first application on the CPU side is 0x0012321A, and the physical address corresponding to data 1 of the first application on the first DMA memory side is 0x04F251BC, then the first MMU page table may include a mapping of the virtual address 0x0012321A on the CPU side to the physical address 0x04F251BC on the first DMA memory side.

[0157] The hardware accelerator can access the data of the first application in the first DMA memory based on the first SMMU page table (or referred to as the first memory page table). The first SMMU page table may include a mapping of the virtual address on the hardware accelerator side to the physical address on the first DMA memory side. For example, if data 1 of the first application is stored in the buffer area 1 of the first DMA memory, the virtual address corresponding to data 1 of the first application on the hardware accelerator side is 0x025412CB, and the physical address corresponding to data 1 of the first application on the first DMA memory side is 0x04F251BC, then the first SMMU page table may include a mapping of the virtual address 0x025412CB on the hardware accelerator side to the physical address 0x04F251BC on the first DMA memory side.

[0158] Figure 5 A schematic diagram of a first DMA memory page fault exception provided in an embodiment of the present application. Figure 5As shown, when the CPU accesses the first application's data 1 in the first DMA memory, the CPU can use the MMU to search the first MMU page table for the physical address on the first DMA memory side corresponding to the CPU-side virtual address 0x0012321A based on the CPU-side virtual address of the first application's data 1. If the physical address on the first DMA memory side corresponding to the CPU-side virtual address 0x0012321A does not exist in the first MMU page table, it means that the first application's data 1 is not stored in the buffer area 1 of the first DMA memory, that is, a page fault exception has occurred in the first DMA memory.

[0159] When the hardware accelerator accesses the first application's data 1 in the first DMA memory, the hardware accelerator can use the SMMU to search the first SMMU page table for the corresponding physical address on the first DMA memory side based on the virtual address 0x04F251BC on the hardware accelerator side of the first application's data 1. If the physical address on the first DMA memory side corresponding to the virtual address 0x04F251BC on the hardware accelerator side does not exist in the first SMMU page table, it means that the first application's data 1 is not stored in the buffer area 1 of the first DMA memory, that is, a page fault exception has occurred in the first DMA memory.

[0160] See Figure 6 , is a flow chart of a memory management method provided in an embodiment of the present application. The specific process of the memory management method is described as follows.

[0161] S601: A hardware accelerator detects a first event; wherein the first event indicates that a probability of a page fault exception occurring in a first DMA memory used by a first application is greater than a first threshold.

[0162] In an embodiment of the present application, when the CPU and the hardware accelerator share a first DMA memory, the hardware accelerator may detect a first event. The first event may indicate that the probability of a page fault exception occurring in the first DMA memory used by the first application is greater than a first threshold. The first threshold is greater than or equal to zero. The first threshold may be pre-configured or defined by a standard. This embodiment of the present application does not limit this. For ease of explanation, the embodiment of the present application takes the first threshold equal to zero as an example. That is, the first event may indicate that a page fault exception may occur in the first DMA memory used by the first application, or the first event may indicate that the probability of a page fault exception occurring in the first DMA memory used by the first application is greater than zero.

[0163] The first event may include one or more of the following: the running state of the first application is switched from a frozen state to a non-frozen state; the data A of the first application corresponding to the first virtual address to be accessed by the CPU is not stored in the first DMA memory. The embodiment of the present application does not limit this. The first event is described in detail below.

[0164] 1) The first event may include the running state of the first application switching from a frozen state to an unfrozen state. That is, if the hardware accelerator determines that the running state of the first application (or the life cycle stage of the first application) switches from a frozen state to an unfrozen state, the hardware accelerator may determine that the probability of a page fault exception occurring in the first DMA memory used by the first application is greater than zero.

[0165] Among them, the non-frozen state includes the foreground running state, the background running state, etc. The frozen state may include the background cache state, the shallow frozen state, the deep frozen state, etc. The embodiment of the present application does not limit this.

[0166] The foreground running state means that the application is running in the foreground. In this running state, the application presents a user interface (UI) through which the user can interact with the application.

[0167] The background running state refers to an app that has switched from the foreground to the background and is still running tasks. In this running state, the app no ​​longer presents a user interface, but the app's tasks (or functions) are still running. For example, a music app runs music playback tasks in the background, and a navigation app runs navigation tasks in the background.

[0168] The background cache state refers to when an app switches from the foreground to the background, is no longer running tasks, and the user has not operated the app for a short period of time (e.g., a first duration). In this state, the app resides in the background to retain the user interface that was previously displayed when the app was running in the foreground, so that the user can continue to operate the app when the app switches from the background to the foreground.

[0169] Shallow freeze occurs when an app is in the background, no longer running tasks, and the user has not operated the app for a certain period of time (e.g., a second duration). In this state, the app only responds to system actions when certain system events occur, such as when the system performs a resolution conversion. The second duration is greater than the first duration.

[0170] The deep freeze state occurs when an app is no longer running tasks after being moved to the background and the user has not operated the app for a long period of time (e.g., the third duration). In this state, the app no ​​longer responds to system actions and is completely inactive. The third duration is greater than the second duration.

[0171] It can be understood that in the three running states of background cache state, shallow freeze state, and deep freeze state, the application does not run any tasks. The difference between the three states lies in the length of time the application resides in the background. When the application resides in the background and the length of time it does not run tasks is short (for example, the first length of time), the application's running state is in the background cache state. When the application resides in the background and the length of time it does not run tasks is long (for example, the second length of time), the application's running state is in the shallow freeze state. When the application resides in the background and the length of time it does not run tasks is very long (for example, the third length of time), the application's running state is in the deep freeze state. If an application in the background cache state has not been operated by the user (i.e., it does not run tasks) after the length of time it does not run tasks reaches the second length of time, it can switch to the shallow freeze state. If an application in the shallow freeze state has not been operated by the user (i.e., it does not run tasks) after the length of time it does not run tasks reaches the third length of time, it can switch to the deep freeze state.

[0172] It's understandable that in non-frozen states like foreground and background, the application is actively executing tasks. The CPU, acting as a producer, continuously writes data to the DMA memory used by the application, meaning it continuously produces data. The hardware accelerator, acting as a consumer, continuously reads data from the DMA memory used by the application, meaning it continuously consumes data. In other words, the data in the DMA memory used by the application is not in a stable state.

[0173] In frozen states such as background cache, shallow freeze, and deep freeze, the app no ​​longer runs any tasks. The CPU, acting as a producer, immediately stops writing data to the DMA memory used by the app. This means the producer immediately stops producing data. However, the hardware accelerator, acting as a consumer, gradually stops reading data from the app's DMA memory. This means the consumer gradually stops consuming data until it no longer accesses the data in the app's DMA memory. This means the data in the app's DMA memory is now stable.

[0174] That is, if the first application switches from the foreground to the background and no longer runs any tasks, it means that the running state of the first application switches from the non-frozen state to the frozen state. Therefore, when the first application switches from the foreground to the background and the first application does not run any background tasks, the hardware accelerator can determine that the running state of the first application switches from the non-frozen state to the frozen state.

[0175] If the first application switches from the background to the foreground, or switches from the foreground to the background but is still running a task, it means that the running state of the first application switches from the frozen state to the unfrozen state. Therefore, when the first application switches from the background to the foreground, or when the first application runs a background task, the hardware accelerator can determine that the running state of the first application switches from the frozen state to the unfrozen state.

[0176] The hardware accelerator may manage the first DMA memory used by the first application according to the running state of the first application, so as to ensure the performance of the first application in the corresponding running state as much as possible.

[0177] For example, if the running state of the first application switches from a non-frozen state to a frozen state, it indicates that the probability of the user operating the first application in a short period of time is low. This can be understood as the probability that the CPU and the hardware accelerator will access part or all of the first application's data in the first DMA memory in a short period of time. Therefore, to save space in the first DMA memory, the hardware accelerator can swap out part or all of the first application's data in the first DMA memory, for example, to disk (or write to disk).

[0178] If the running state of the first application switches from a frozen state to a non-frozen state, it means that the probability of the user operating the first application in a short period of time is high. It can be understood that the probability of the CPU and the hardware accelerator accessing part or all of the data of the first application in the first DMA memory in a short period of time is high. If part or all of the data of the first application in the first DMA memory accessed by the CPU and the hardware accelerator has been swapped out to the disk, a page fault exception will occur in the first DMA memory; if part or all of the data of the first application in the first DMA memory accessed by the CPU and the hardware accelerator has not been swapped out to the disk, a page fault exception will not occur in the first DMA memory. In other words, the first DMA memory used by the first application may have a page fault exception, or the probability of the first DMA memory used by the first application having a page fault exception is greater than zero. Therefore, in order to avoid the possibility of a page fault exception in the first DMA memory, the hardware accelerator can rewrite part or all of the data of the first application on the disk into the first DMA memory.

[0179] In a possible implementation, before the hardware accelerator detects the first event, the hardware accelerator may swap out part or all of the data of the first application in the first DMA memory to the disk by executing the following steps.

[0180] Step a1: The hardware accelerator detects a second event.

[0181] The second event may include the running state of the first application being switched from a non-frozen state to a frozen state.

[0182] It can be understood that when the first application is in a non-frozen state, the first application is executing a task. The CPU, acting as a producer, continuously writes data to the first DMA memory used by the first application, i.e., the producer continuously produces data. The hardware accelerator, acting as a consumer, continuously reads data from the first DMA memory used by the first application, i.e., the consumer continuously consumes data.

[0183] When the running state of the first application is frozen, the first application no longer runs tasks. The CPU, as a producer, will immediately stop writing data to the first DMA memory used by the first application, that is, the producer will immediately stop producing data. However, the hardware accelerator, as a consumer, will gradually stop reading data from the first DMA memory used by the first application, that is, the consumer will gradually stop consuming data until it no longer accesses the data in the first DMA memory. It is worth noting that when the running state of the first application is frozen, the hardware accelerator will gradually migrate consumption to the DMA memory used by other applications whose running state is not frozen. Therefore, the hardware accelerator will not stop until all the data in the first DMA memory used by the first application is read. When the hardware accelerator stops reading data from the first DMA memory, some data that has not been read by the hardware accelerator is still stored in the first DMA memory.

[0184] That is, a prerequisite for part or all of the data of the first application in the first DMA memory to be written to the disk is that the running state of the first application is frozen.

[0185] Step a2: In response to the second event, the hardware accelerator swaps out the data B of the first application in the first DMA memory to the disk, and updates the first SMMU page table according to the data B of the first application in the disk.

[0186] The first DMA memory includes a first buffer queue, and the data B of the first application is stored in the first buffer queue. That is, the data B of the first application is stored in the first buffer queue in the first DMA memory before being swapped out from the first DMA memory to the disk.

[0187] To ensure that the data B of the first application is secure data (i.e., data that the CPU and hardware accelerator will not access in the short term), the hardware accelerator can detect whether each buffer area in the first buffer queue is a secure buffer area (i.e., a buffer area that the CPU and hardware accelerator will not access in the short term). If each buffer area in the first buffer queue is a secure buffer area, the hardware accelerator can swap out the data in each buffer area in the first buffer queue to the disk.

[0188] For example, in step a2, the hardware accelerator may swap out the data B of the first application in the first DMA memory to the disk by executing steps a21 to a22.

[0189] Step a21: The hardware accelerator detects a third event.

[0190] The third event may indicate that the data in the first DMA memory is no longer updated, and / or the identifier of each buffer area in the first buffer queue is a first identifier. The first identifier may be used to indicate that the data in the corresponding buffer area can be swapped out to the disk by the hardware accelerator.

[0191] The data in the first DMA memory is no longer updated. This can be understood as the CPU, acting as a producer, has stopped writing data to the first DMA memory used by the first application, and the hardware accelerator, acting as a consumer, has stopped reading data from the first DMA memory used by the first application. In other words, the producer has stopped producing data, and the consumer has stopped consuming data. The data in the first DMA memory is now stable and will not be accessed by the CPU or hardware accelerator for a short period of time. In other words, the data in the first DMA memory can be swapped out to disk by the hardware accelerator.

[0192] Each buffer area in the first buffer queue is identified by a first identifier, which can be understood as indicating that the data in each buffer area in the first buffer queue is in a stable state and will not be accessed by the CPU or the hardware accelerator in the short term. In other words, the data in each buffer area in the first buffer queue can be swapped out to the disk by the hardware accelerator.

[0193] For example, Figure 7 This is a schematic diagram of a first buffer queue provided in an embodiment of the present application. Figure 7 As shown, the first DMA memory can be a buffer queue, which can include N buffer areas, namely buffer area 1, buffer area 2, buffer area 3, buffer area 4, ..., buffer area N. N is a positive integer greater than or equal to 1. After the running state of the first application switches from the non-frozen state to the frozen state, the CPU, as the producer, stops writing data to the first DMA memory used by the first application, but the hardware accelerator, as the consumer, continues to read data from buffer area 2. Therefore, the data in buffer area 1, buffer area 3, buffer area 4, ..., buffer area N can all be swapped out to disk by the hardware accelerator, that is, the identifiers of buffer area 1, buffer area 3, buffer area 4, ..., buffer area N are all first identifiers. However, the data in buffer area 2 cannot be swapped out to disk by the hardware accelerator, that is, the identifier of buffer area 2 is the second identifier (or attached identifier), which can be used to indicate that the data in the corresponding buffer area cannot be swapped out to disk by the hardware accelerator. That is, the first buffer queue in the first DMA memory for storing the data B of the first application includes buffer area 1, buffer area 2, buffer area 3, . . . , buffer area N.

[0194] Step a22: In response to the third event, the hardware accelerator swaps out the data in each buffer area in the first buffer queue to the disk.

[0195] It can be understood that after the running state of the first application switches from the non-frozen state to the frozen state, although the CPU as the producer will not continue to write data to the first DMA memory used by the first application, the hardware accelerator as the consumer will continue to read data from the first DMA memory used by the first application. Therefore, in order to avoid affecting the current access of the hardware accelerator, part or all of the data of the first application in the first DMA memory needs to be written to the disk after the hardware accelerator stops reading data from the first DMA memory. And in order to avoid affecting the subsequent access of the CPU and the hardware accelerator, the data written to the disk needs to be the data in the buffer area corresponding to the first identifier. In other words, the data written to the disk cannot be the data in the buffer area corresponding to the second identifier.

[0196] For example, in step a2, the hardware accelerator may update the first SMMU page table according to the data B of the first application in the disk by executing step a23.

[0197] Step a3: The hardware accelerator deletes the mapping from the second virtual address to the first physical address in the first SMMU page table.

[0198] The second virtual address is a virtual address corresponding to the data B of the first application on the hardware accelerator side, and the first physical address is a physical address corresponding to the data B of the first application on the first DMA memory side.

[0199] It is understood that after the hardware accelerator swaps the first application's data B in the first DMA memory out to the disk, the hardware accelerator can delete the mapping from the first application's data B virtual address on the hardware accelerator side to the first application's data B physical address on the first DMA memory side in the first SMMU page table. Furthermore, the CPU can also delete the mapping from the first application's data B virtual address on the CPU side to the first application's data B physical address on the first DMA memory side in the first MMU page table. In other words, the hardware accelerator can unmap the first application's data B in the first SMMU page table, and the CPU can unmap the first application's data B in the first MMU page table.

[0200] For example, for the above Figure 4As shown in the first SMMU page table and the first MMU page table, after the hardware accelerator swaps out the data 1 of the first application in the buffer area 1 of the first DMA memory to the disk, the hardware accelerator can delete the mapping of the virtual address 0x025412CB on the hardware accelerator side to the physical address 0x04F251BC on the first DMA memory side in the first SMMU page table, and the CPU can delete the mapping of the virtual address 0x0012321A on the CPU side to the physical address 0x04F251BC on the first DMA memory side in the first MMU page table, thereby obtaining the above Figure 5 The first SMMU page table and the first MMU page table are shown.

[0201] For example, Figure 8 This is a schematic diagram of swapping out part or all of the data of a first application in a first DMA memory to a disk according to an embodiment of the present application. Figure 8 As shown in the figure, the placement of disks can be divided into four steps, which are introduced below.

[0202] In step 1, the first application is frozen. That is, the first application no longer runs tasks. The CPU, acting as a producer, immediately stops writing data to the first DMA memory used by the first application. This means the producer immediately stops producing data. However, the hardware accelerator, acting as a consumer, gradually stops reading data from the first DMA memory used by the first application. This means the consumer gradually stops consuming data.

[0203] In step 2, the data in buffer area N in the first DMA memory is in a stable state. That is, the hardware accelerator, acting as a consumer, has stopped reading data from buffer area N in the first DMA memory used by the first application. In other words, the producer has stopped producing data, and the consumer has stopped consuming data. The data in buffer area N in the first DMA memory is in a stable state. The data in buffer area N in the first DMA memory will not be accessed by the CPU or the hardware accelerator in the short term and can be swapped out to disk by the hardware accelerator.

[0204] In step 3, the hardware accelerator swaps out the data of the first application in the buffer area N in the first DMA memory to the disk, that is, writes the data to the disk.

[0205] In step 4, the hardware accelerator deletes the mapping from the virtual address 0x013412AF on the hardware accelerator side to the physical address 0x04F261BC on the first DMA memory side in the first SMMU page table, that is, demapping.

[0206] 2) The first event may include that data A of the first application corresponding to the first virtual address to be accessed by the CPU is not stored in the first DMA memory. In other words, if the hardware accelerator determines that data A of the first application corresponding to the first virtual address to be accessed by the CPU is not stored in the first DMA memory, the hardware accelerator may determine that a probability of a page fault exception occurring in the first DMA memory used by the first application is greater than zero.

[0207] Here, the first application's data A belongs to the first application's data B. That is, the first application's data B includes the first application's data A. This can be understood as the first application's data B being all of the first application's data stored on the disk, and the first application's data A being only part of the first application's data stored on the disk. The first virtual address is the virtual address corresponding to the first application's data A on the CPU.

[0208] It is understood that the hardware accelerator can monitor the first virtual address that the CPU is about to access and determine whether the data A of the first application corresponding to the first virtual address that the CPU is about to access is stored in the first DMA memory. If the data A of the first application is stored in the first DMA memory, the hardware accelerator can determine that the first DMA memory used by the first application does not have a page fault exception, that is, the probability of the first DMA memory used by the first application having a page fault exception is zero; if the data A of the first application is not stored in the first DMA memory, the hardware accelerator can determine that the first DMA memory used by the first application has a page fault exception, that is, the probability of the first DMA memory used by the first application having a page fault exception is greater than zero.

[0209] In a possible implementation, the hardware accelerator may determine whether the data A of the first application corresponding to the first virtual address to be accessed by the CPU is stored in the first DMA memory by performing the following steps.

[0210] Step b1: The hardware accelerator searches for a third virtual address corresponding to the first virtual address from a first DMA memory page table (or referred to as a second memory page table) according to the first virtual address.

[0211] The first DMA memory page table may include a mapping from a virtual address on the CPU side to a virtual address on the hardware accelerator side. The third virtual address is a virtual address corresponding to the data A of the first application on the hardware accelerator side.

[0212] Step b2: The hardware accelerator searches the first SMMU page table for the second physical address corresponding to the third virtual address according to the third virtual address.

[0213] The second physical address is the physical address corresponding to the data A of the first application on the first DMA memory side.

[0214] Step b3: If the second physical address exists in the first SMMU page table, the hardware accelerator determines that the data A of the first application is stored in the first DMA memory; if the second physical address does not exist in the first SMMU page table, the hardware accelerator determines that the data A of the first application is not stored in the first DMA memory.

[0215] For example, Figure 9 The embodiment of the present application provides a schematic diagram of a first DMA memory page table. Figure 9 As shown, when the CPU accesses the data 1 of the first application in the first DMA memory, the CPU can send the virtual address 0x0012321A of the data 1 of the first application on the CPU side to the hardware accelerator. The hardware accelerator searches the first DMA memory page table for the virtual address 0x04F251BC of the data 1 of the first application on the hardware accelerator side based on the virtual address 0x0012321A of the data 1 of the first application on the CPU side. The hardware accelerator searches the first SMMU page table for the corresponding physical address on the first DMA memory side based on the virtual address 0x04F251BC of the data 1 of the first application on the hardware accelerator side. If the physical address on the first DMA memory side corresponding to the virtual address 0x04F251BC on the hardware accelerator side does not exist in the first SMMU page table, it means that the data 1 of the first application is not stored in the first DMA memory, that is, a page fault exception occurs in the first DMA memory.

[0216] S602. In response to a first event, the hardware accelerator performs a first operation; wherein the first operation includes one or more of the following: killing a first process of a first application; writing first data of the first application in a disk to a first DMA memory, and updating a first SMMU page table according to the first data in the first DMA memory, wherein the first SMMU page table includes a mapping from a virtual address on the hardware accelerator side to a physical address on the first DMA memory side.

[0217] In the embodiment of the present application, the first data of the first application can be data B of the first application (or called second data), or can also be data A of the first application (or called third data). Here, since data B of the first application is all the data of the first application stored on the disk, and data A of the first application is part of the data of the first application stored on the disk (i.e., the data corresponding to the first virtual address to be accessed by the CPU), writing data B of the first application on the disk to the first DMA memory can be called a full-page write, and writing data A of the first application on the disk to the first DMA memory can be called a single-page write.

[0218] That is, after the hardware accelerator detects the first event, that is, after the hardware accelerator determines that the probability of a page fault exception occurring in the first DMA memory used by the first application is greater than zero, the hardware accelerator can process the page fault exception that may occur in the first DMA memory by executing the first operation, thereby improving memory management efficiency.

[0219] In a specific implementation process, the hardware accelerator may determine the first operation to be executed based on the storage space occupied by the data of the first application on the disk. The first operation is described below in different situations.

[0220] In case A, when the storage space occupied by the first application's data on the disk is greater than or equal to a second threshold, the first operation may include killing the first process of the first application. That is, when the hardware accelerator determines that a page fault exception may occur in the first DMA memory, the hardware accelerator may kill the first process of the first application. For example, the hardware accelerator may send a killing message to the CPU instructing the CPU to kill the first process of the first application. The second threshold is greater than zero and may be pre-configured or defined by a standard, which is not limited in this embodiment of the present application.

[0221] It is understandable that if the first application's data occupies a large amount of storage space on the disk (e.g., greater than or equal to the second threshold), the first application's data will increase the disk load, and the increased load will be significant. Therefore, to improve disk management efficiency, after the hardware accelerator determines that the first DMA memory used by the first application may have a page fault exception, the hardware accelerator can directly kill the first application to handle the possible page fault exception in the first DMA memory, thereby improving memory management efficiency and disk management efficiency.

[0222] For example, Figure 10 A schematic diagram of a hardware accelerator managing a first DMA memory provided in an embodiment of the present application.

[0223] like Figure 10As shown, when the first application switches from the foreground to the background, the hardware accelerator determines whether the first application is running a background task. If the first application is running a background task, the hardware accelerator determines that the running state of the first application is in a non-frozen state. If the first application is not running a background task, the hardware accelerator determines that the running state of the first application is in a frozen state. The hardware accelerator determines that the data of the first application in the first DMA memory is no longer updated, that is, the data of the first application in the first DMA memory is in a stable state and will not be accessed by the CPU and the hardware accelerator in a short time. The hardware accelerator swaps out the data B of the first application in the first DMA memory to the disk. The hardware accelerator monitors the first virtual address that the CPU wants to access, and determines whether the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory. If the data A of the first application corresponding to the first virtual address that the CPU wants to access is stored in the first DMA memory, it is determined that there is no page fault exception in the first DMA memory. If the data A of the first application corresponding to the first virtual address to be accessed by the CPU is not stored in the first DMA memory, the hardware accelerator determines the storage space occupied by the data B of the first application on the disk, and kills the first process of the first application if the storage space occupied by the data B of the first application on the disk is greater than or equal to a second threshold.

[0224] In case B, when the storage space occupied by the data of the first application on the disk is less than the second threshold and greater than the third threshold (that is, the second threshold is greater than the third threshold), the first operation may include writing the data B of the first application on the disk to the first DMA memory, and updating the first SMMU page table based on the data B of the first application in the first DMA memory. That is, when the hardware accelerator determines that a page fault exception may occur in the first DMA memory, the hardware accelerator may write the data B of the first application on the disk to the first DMA memory, and update the first SMMU page table based on the data B of the first application in the first DMA memory. Among them, the third threshold is greater than or equal to zero, and the third threshold can be pre-configured or defined by the standard, which is not limited in this embodiment of the present application.

[0225] It is understandable that if the storage space occupied by the first application's data on the disk is generally large (for example, less than the second threshold and greater than the third threshold), then the first application's data will increase the disk load, but the increased load is generally large. Therefore, in order to improve disk management efficiency and not affect the user's experience with the background cache, after the hardware accelerator determines that the first DMA memory used by the first application may have a page fault exception, the hardware accelerator can write the first application's data B on the disk to the first DMA memory (i.e., write the entire page), thereby improving memory management efficiency and disk management efficiency while not affecting the user's experience with the background cache.

[0226] In one possible implementation, after the hardware accelerator detects the first event, in response to the first event, the hardware accelerator may execute the following steps to write the data B of the first application in the disk to the first DMA memory, and update the first SMMU page table according to the data B of the first application in the first DMA memory.

[0227] Step c1: The hardware accelerator writes the data B of the first application in the disk to the second buffer queue in the first DMA memory.

[0228] It can be understood that in the above step a2, the hardware accelerator swaps out the data B of the first application in the first buffer queue in the first DMA memory to the disk, and in this step c1, the hardware accelerator rewrites the data B of the first application in the disk to the second buffer queue in the first DMA memory. In other words, before the data B of the first application in the first DMA memory is written to the disk, the data B of the first application is stored in the first buffer queue in the first DMA memory. After the data B of the first application in the first DMA memory is written to the disk and rewritten to the first DMA memory, the data B of the first application is restored in the second buffer queue in the first DMA memory. In other words, the first buffer queue is the buffer queue where the data B of the first application is located before it is swapped out from the first DMA memory to the disk, and the second buffer queue is the buffer queue where the data B of the first application is located after it is rewritten from the disk to the first DMA memory.

[0229] To ensure the accuracy of the data B of the first application read from the disk by the hardware accelerator as much as possible, after writing the data B of the first application from the disk to the second buffer queue in the first DMA memory, the hardware accelerator can determine whether the data B of the first application in the first buffer queue is identical to the data B of the first application in the second buffer queue. If the data B of the first application in the first buffer queue is different from the data B of the first application in the second buffer queue, it indicates that the data B of the first application read from the disk by the hardware accelerator after writing to the disk is incorrect data. If the data B of the first application in the first buffer queue is the same as the data B of the first application in the second buffer queue, it indicates that the data B of the first application read from the disk by the hardware accelerator after writing to the disk is correct data.

[0230] Furthermore, in order to improve the judgment efficiency of the hardware accelerator, the hardware accelerator can only compare whether the data in the first buffer area in the first buffer queue is the same as the data in the first buffer area in the second buffer queue, and whether the data in the last buffer area in the first buffer queue is the same as the data in the last buffer area in the second buffer queue.

[0231] For example, after the hardware accelerator performs the above step c1, the hardware accelerator may further perform the following steps d1 to d2.

[0232] Step d1: The hardware accelerator detects a fourth event.

[0233] The fourth event indicates that the data in the first buffer area in the first buffer queue is different from the data in the first buffer area in the second buffer queue, and / or the data in the last buffer area in the first buffer queue is different from the data in the last buffer area in the second buffer queue.

[0234] Step d2: In response to the fourth event, the hardware accelerator kills the first process of the first application.

[0235] For another example, after the hardware accelerator executes the above step c1, the hardware accelerator may further execute the following steps e1 to e2.

[0236] Step e1: The hardware accelerator detects a fifth event.

[0237] The fifth event indicates that the data in the first buffer area in the first buffer queue is the same as the data in the first buffer area in the second buffer queue, and the data in the last buffer area in the first buffer queue is the same as the data in the last buffer area in the second buffer queue.

[0238] Step e2: In response to the fifth event, the hardware accelerator updates the first SMMU page table according to the data B of the first application in the first DMA memory.

[0239] Figure 11 The embodiment of the present application provides a schematic diagram for comparing data in a first buffer queue and a second buffer queue. Figure 11As shown, the first DMA memory can be a buffer queue, which can include N buffer areas, namely buffer area 1, buffer area 2, buffer area 3, buffer area 4, ..., buffer area N. N is a positive integer greater than or equal to 1. Before the data B of the first application in the first DMA memory is written to the disk, the data B of the first application is stored in the first buffer queue (including buffer area 1, buffer area 3, buffer area 4, ..., buffer area N) in the first DMA memory. At this time, the data B of the first application in the first buffer queue are data 11, data 13, data 14, ..., data 1N. After the data B of the first application in the first DMA memory is written to the disk and re-stored in the first DMA memory, the data B of the first application is re-stored in the second buffer queue (including buffer area 1, buffer area 3, buffer area 4, ..., buffer area N) in the first DMA memory. At this time, the data B of the first application in the second buffer queue are data 21, data 23, data 24, ..., buffer area 2N. The hardware accelerator can compare whether the data 11 in the buffer area 1 in the first buffer queue is the same as the data 21 in the buffer area 1 in the second buffer queue, and whether the data 1N in the buffer area N in the first buffer queue is the same as the data 2N in the buffer area N in the second buffer queue. If they are different, it means that the data B of the first application read from the disk by the hardware accelerator after the disk is wrong. In order to prevent the CPU and the hardware accelerator from accessing the wrong data B of the first application, the hardware accelerator can instruct the CPU to kill the first process of the first application. If they are the same, it means that the data B of the first application read from the disk by the hardware accelerator after the disk is correct data, and the hardware accelerator can re-establish the mapping related to the data B of the first application in the first SMMU page table.

[0240] Optionally, if the current running state of the first application is a frozen state, the hardware accelerator may further send first indication information to the CPU, wherein the first indication information is used to instruct the CPU to switch the running state of the first application from the frozen state to a non-frozen state.

[0241] Step c2: The hardware accelerator adds a mapping from the second virtual address to the first physical address in the first SMMU page table.

[0242] It is understood that after the hardware accelerator writes the first application's data B from the disk to the first DMA memory, the hardware accelerator can increment the virtual address of the first application's data B on the hardware accelerator side in the first SMMU page table to the physical address of the first application's data B on the first DMA memory side. Furthermore, the CPU can also increment the virtual address of the first application's data B on the CPU side in the first MMU page table to the physical address of the first application's data B on the first DMA memory side. In other words, the hardware accelerator can re-establish the mapping related to the first application's data B in the first SMMU page table, and the CPU can re-establish the mapping related to the first application's data B in the first MMU page table.

[0243] For example, for the above Figure 5 As shown in the first SMMU page table and the first MMU page table, after the hardware accelerator writes the data 1 of the first application in the disk to the buffer area 1 of the first DMA memory, the hardware accelerator can add a mapping of the virtual address 0x025412CB on the hardware accelerator side in the first SMMU page table to the physical address 0x04F251BC on the first DMA memory side, and the CPU can add a mapping of the virtual address 0x0012321A on the CPU side in the first MMU page table to the physical address 0x04F251BC on the first DMA memory side, thereby obtaining the above Figure 4 The first SMMU page table and the first MMU page table are shown.

[0244] For example, Figure 12 A schematic diagram of another hardware accelerator managing a first DMA memory provided in an embodiment of the present application.

[0245] like Figure 12As shown, when the first application switches from the foreground to the background, the hardware accelerator determines whether the first application is running a background task. If the first application is running a background task, the hardware accelerator determines that the first application's running state is not frozen. If the first application is not running a background task, the hardware accelerator determines that the first application's running state is frozen. The hardware accelerator determines that the first application's data in the first DMA memory is no longer updated, that is, the first application's data in the first DMA memory is in a stable state and will not be accessed by the CPU and the hardware accelerator in a short period of time. The hardware accelerator swaps the first application's data B in the first DMA memory out to the disk. The hardware accelerator monitors the first virtual address to be accessed by the CPU and determines whether the first application's data A corresponding to the first virtual address to be accessed by the CPU is stored in the first DMA memory. If the first application's data A corresponding to the first virtual address to be accessed by the CPU is stored in the first DMA memory, it is determined that no page fault exception has occurred in the first DMA memory. If the first application's data A corresponding to the first virtual address to be accessed by the CPU is not stored in the first DMA memory, the hardware accelerator determines the storage space occupied by the first application's data B on the disk. When the storage space occupied by the data B of the first application on the disk is less than the second threshold and greater than the third threshold, the hardware accelerator writes the data B of the first application on the disk to the first DMA memory and updates the first SMMU page table according to the data B of the first application in the first DMA memory, that is, the hardware accelerator triggers a full-page write.

[0246] In case C, when the storage space occupied by the first application's data on the disk is less than or equal to the third threshold, the first operation may include writing the first application's data A on the disk to the first DMA memory and updating the first SMMU page table based on the first application's data A in the first DMA memory. That is, when the hardware accelerator determines that a page fault exception may occur in the first DMA memory, the hardware accelerator may write the first application's data A on the disk to the first DMA memory and update the first SMMU page table based on the first application's data A in the first DMA memory.

[0247] It is understandable that if the storage space occupied by the first application's data on the disk is small (for example, less than or equal to the third threshold), then the first application's data will not increase the disk load, or although it will increase the disk load, the increased load is small. Therefore, after the hardware accelerator determines that the first DMA memory used by the first application may have a page fault exception, the hardware accelerator can write the first application's data A on the disk to the first DMA memory (i.e., single-page write), thereby improving memory management efficiency.

[0248] In one possible implementation, after the hardware accelerator detects the first event, in response to the first event, the hardware accelerator may execute the following steps to write data A in the disk to the first DMA memory, and update the first SMMU page table according to the data A of the first application in the first DMA memory.

[0249] Step d1: The hardware accelerator searches the first DMA memory page table for a third virtual address corresponding to the first virtual address according to the first virtual address.

[0250] Step d2: the hardware accelerator accesses the data A of the first application in the disk according to the third virtual address, and writes the data A of the first application in the disk into the first DMA memory.

[0251] Step d3: The hardware accelerator adds a mapping from the third virtual address to the second physical address in the first SMMU page table.

[0252] It is understood that after the hardware accelerator writes the first application's data A from the disk to the first DMA memory, the hardware accelerator can increment the virtual address of the first application's data A on the hardware accelerator side in the first SMMU page table to the physical address of the first application's data B on the first DMA memory side. Furthermore, the CPU can also increment the virtual address of the first application's data A on the CPU side in the first MMU page table to the physical address of the first application's data A on the first DMA memory side. In other words, the hardware accelerator can re-establish the mapping related to the first application's data A in the first SMMU page table, and the CPU can re-establish the mapping related to the first application's data A in the first MMU page table.

[0253] For example, Figure 13 A schematic diagram of another hardware accelerator managing a first DMA memory provided in an embodiment of the present application.

[0254] like Figure 13As shown, when the first application switches from the foreground to the background, the hardware accelerator determines whether the first application is running a background task. If the first application is running a background task, the hardware accelerator determines that the first application's running state is not frozen. If the first application is not running a background task, the hardware accelerator determines that the first application's running state is frozen. The hardware accelerator determines that the first application's data in the first DMA memory is no longer updated, that is, the first application's data in the first DMA memory is in a stable state and will not be accessed by the CPU and the hardware accelerator in a short period of time. The hardware accelerator swaps the first application's data B in the first DMA memory out to the disk. The hardware accelerator monitors the first virtual address to be accessed by the CPU and determines whether the first application's data A corresponding to the first virtual address to be accessed by the CPU is stored in the first DMA memory. If the first application's data A corresponding to the first virtual address to be accessed by the CPU is stored in the first DMA memory, it is determined that no page fault exception has occurred in the first DMA memory. If the first application's data A corresponding to the first virtual address to be accessed by the CPU is not stored in the first DMA memory, the hardware accelerator determines the storage space occupied by the first application's data B on the disk. When the storage space occupied by the data B of the first application on the disk is less than or equal to the third threshold, the hardware accelerator writes the data A of the first application on the disk to the first DMA memory and updates the first SMMU page table according to the data A of the first application in the first DMA memory, that is, the hardware accelerator triggers single-page write.

[0255] For example, Figure 14 This is a schematic diagram of writing part or all of the data of a first application in a disk to a first DMA memory provided by an embodiment of the present application. Figure 14 As shown in the figure, rewriting after flushing can be divided into three steps, which are introduced below.

[0256] Step 1: The hardware accelerator writes the data of the first application in the buffer area N in the disk to the first DMA memory, that is, rewrites the data.

[0257] In step 4, the hardware accelerator adds a mapping from the virtual address 0x013412AF on the hardware accelerator side to the physical address 0x04F261BC on the first DMA memory side in the first SMMU page table, that is, remapping.

[0258] In step 3, the first application is in an unfrozen state. That is, the first application is running tasks. The CPU, acting as a producer, continuously writes data to the first DMA memory used by the first application, i.e., the producer continuously produces data. The hardware accelerator, acting as a consumer, continuously reads data from the first DMA memory used by the first application, i.e., the consumer continuously consumes data.

[0259] Based on the above solution, after determining that the probability of a page fault exception occurring in the first DMA memory used by the first application is greater than zero, the hardware accelerator can process the page fault exception that may occur in the first DMA memory by executing the first operation, thereby improving memory management efficiency.

[0260] Based on the above embodiments and the same concept, an embodiment of the present application further provides an electronic device, which is used to implement the memory management method provided in the embodiment of the present application.

[0261] like Figure 15 As shown, electronic device 1500 may include: memory 1501, one or more processors 1502, and one or more computer programs (not shown). The above components may be coupled via one or more communication buses 1503. Optionally, when electronic device 1500 is used to implement the memory management method provided in the embodiments of the present application, electronic device 1500 may further include a display screen 1504.

[0262] Memory 1501 stores one or more computer programs (codes), each of which includes computer instructions. Processors 1502 invoke the computer instructions stored in memory 1501, causing electronic device 1500 to execute the memory management method provided in the embodiments of the present application. Display screen 1504 is used to display images, videos, application interfaces, and other related user interfaces.

[0263] In a specific implementation, the memory 1501 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more disk storage devices, flash memory devices or other non-volatile solid-state storage devices. The memory 1501 can store an operating system (hereinafter referred to as system), such as ANDROID, IOS, WINDOWS, or embedded operating systems such as LINUX. The memory 1501 can be used to store the implementation program of the embodiment of the present application. The memory 1501 can also store a network communication program, which can be used to communicate with one or more additional devices, one or more user devices, or one or more electronic devices. The one or more processors 1502 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application.

[0264] It should be noted that Figure 15 This is only one implementation of the electronic device 1500 provided in the embodiment of the present application. In actual applications, the electronic device 1500 may also include more or fewer components, which is not limited here.

[0265] Based on the above embodiments and the same concept, an embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a computer, the computer executes the memory management method provided in the above embodiments.

[0266] Based on the above embodiments and the same concept, an embodiment of the present application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer executes the memory management method provided in the above embodiments.

[0267] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0268] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0269] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0270] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0271] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A memory management method, characterized in that: Applied to electronic equipment, the method includes: The hardware accelerator of the electronic device detects a first event; wherein the first event indicates that a probability of a page fault exception occurring in a first direct memory access (DMA) memory used by the first application is greater than a first threshold; In response to the first event, the hardware accelerator performs a first operation, wherein the first operation includes one or more of the following: Killing the first process of the first application; Writing first data of the first application in the disk to the first DMA memory, and updating a first memory page table according to the first data in the first DMA memory, wherein the first memory page table includes a mapping from a virtual address on the hardware accelerator side to a physical address on the first DMA memory side.

2. The method according to claim 1, wherein The first event includes the running state of the first application being switched from a frozen state to a non-frozen state; and / or, The first event includes that data corresponding to a first virtual address to be accessed by a central processing unit (CPU) of the electronic device is not stored in the first DMA memory.

3. The method according to claim 1 or 2, wherein: The first data is the second data or the third data, the second data includes the third data, the second data is all the data of the first application stored in the disk, the third data is part of the data of the first application stored in the disk, and the part of the data is the data corresponding to the first virtual address to be accessed by the CPU of the electronic device.

4. The method according to claim 3, wherein Before the hardware accelerator detects the first event, the method further includes: The hardware accelerator detects a second event; wherein the second event includes the running state of the first application switching from a non-frozen state to a frozen state; In response to the second event, the hardware accelerator swaps out the second data in the first DMA memory to the disk, and updates the first memory page table according to the second data in the disk.

5. The method according to claim 4, wherein The first DMA memory includes a first buffer queue, and the second data is stored in the first buffer queue; The hardware accelerator swaps out the second data in the first DMA memory to the disk, including: The hardware accelerator detects a third event, wherein the third event indicates that data in the first DMA memory is no longer updated, and / or the identifier of each buffer area in the first buffer queue is a first identifier, and the first identifier is used to indicate that data in the corresponding buffer area can be swapped out to the disk by the hardware accelerator; In response to the third event, the hardware accelerator swaps out data in each buffer area in the first buffer queue to the disk.

6. The method according to claim 4 or 5, characterized in that The hardware accelerator updates the first memory page table according to the second data in the disk, including: The hardware accelerator deletes the mapping of the second virtual address in the first memory page table to the first physical address; wherein the second virtual address is the virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is the physical address corresponding to the second data on the first DMA memory side.

7. The method according to any one of claims 3 to 6, characterized in that: The first data is the second data, and the hardware accelerator writes the first data in the disk to the first DMA memory, including: The hardware accelerator writes the second data in the disk to a second buffer queue in the first DMA memory.

8. The method according to claim 7, wherein The method further comprises: The hardware accelerator detects a fourth event, wherein the fourth event indicates that data in a first buffer area in a first buffer queue is different from data in a first buffer area in a second buffer queue, and / or data in a last buffer area in the first buffer queue is different from data in a last buffer area in the second buffer queue, the first buffer queue being the buffer queue where the second data was located before being swapped out from the first DMA memory to the disk; In response to the fourth event, the hardware accelerator kills the first process of the first application.

9. The method according to claim 7, wherein The method further comprises: The hardware accelerator detects a fifth event, wherein the fifth event indicates that data in a first buffer area in a first buffer queue is identical to data in a first buffer area in a second buffer queue, and data in a last buffer area in the first buffer queue is identical to data in a last buffer area in the second buffer queue, the first buffer queue being the buffer queue where the second data was located before being swapped out from the first DMA memory to the disk; In response to the fifth event, the hardware accelerator updates the first memory page table according to the second data in the first DMA memory.

10. The method according to any one of claims 7 to 9, characterized in that: The hardware accelerator updates the first memory page table according to the first data in the first DMA memory, including: The hardware accelerator adds a mapping of a second virtual address to a first physical address in the first memory page table; wherein the second virtual address is a virtual address corresponding to the second data on the hardware accelerator side, and the first physical address is a physical address corresponding to the second data on the first DMA memory side.

11. The method according to any one of claims 3 to 6, wherein: The first data is the third data, and the hardware accelerator writes the first data in the disk to the first DMA memory, including: The hardware accelerator queries a second memory page table according to the first virtual address to obtain a third virtual address; wherein the second memory page table includes a mapping from the virtual address on the CPU side to the virtual address on the hardware accelerator side, and the third virtual address is a virtual address corresponding to the third data on the hardware accelerator side; The hardware accelerator accesses the third data in the disk according to the third virtual address, and writes the third data in the disk into the first DMA memory.

12. The method according to claim 11, wherein The hardware accelerator updates the first memory page table according to the first data in the first DMA memory, including: The hardware accelerator adds a mapping of a third virtual address to a second physical address in the first memory page table; wherein the third virtual address is a virtual address corresponding to the third data on the hardware accelerator side, and the second physical address is a physical address corresponding to the third data on the first DMA memory side.

13. The method according to any one of claims 1 to 12, wherein: The method further comprises: When the first application is switched from the foreground to the background and the first application is not running any background tasks, the hardware accelerator determines that the running state of the first application is switched from the non-frozen state to the frozen state; or When the first application is switched from the background to the foreground, or the first application runs a background task, the hardware accelerator determines that the running state of the first application is switched from the frozen state to the non-frozen state.

14. An electronic device, characterized in that: The electronic device includes: one or more processors and memory; The memory is coupled to the one or more processors, and is configured to store computer program codes, where the computer program codes include computer instructions. The one or more processors call the computer instructions to enable the electronic device to execute the method according to any one of claims 1 to 13.

15. A chip system, characterized in that: The chip system is applied to an electronic device, and the chip system includes one or more processors, and the processor is used to call computer instructions to enable the electronic device to execute the method as described in any one of claims 1-12.

16. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on an electronic device, the electronic device is caused to execute the method according to any one of claims 1 to 13.

17. A computer program product, characterized in that The method comprises computer-readable instructions which, when executed by one or more processors, implement the method of any one of claims 1 to 13.

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