Signal output device with adjustable conversion rate

Abstract

The invention discloses a signal output device with an adjustable conversion rate. The signal output device comprises a plurality of output units. The output units are connected in parallel between the input end and the output end, respectively correspond to the adjustable signal delay amount, and each output unit comprises a delay path and an output circuit. The delay path is configured to provide an adjustable signal delay amount to receive an input signal from an input end and delay the input signal, thereby generating a delayed signal. The output circuit receives the delay signal and generates an output signal to the output end. Wherein the output end outputs a total output signal according to the output signals generated by the output circuits of all the output units, and the conversion rate of the total output signal is determined by the combination of the adjustable signal delays of the output units.

Description

Technical Field

[0001] The present invention relates to a signal output technology, in particular to a signal output device with an adjustable conversion rate. Background Art

[0002] In electronic devices, signal transmission often requires the use of a signal output circuit, in which a driving circuit within the signal output circuit drives the signal for output.

[0003] When the driver circuit's output signal transitions, the rise time (rise time) from a low state to a high state and the fall time (fall time) from a high state to a low state must meet requirements to keep the slew rate within a reasonable range. For example, when the driver circuit operates at high speed, shorter rise and fall times can be tolerated, thereby allowing a higher slew rate. However, when the driver circuit operates at low speed, the rise and fall times must be greater than the default values, allowing only a lower slew rate. If the driver circuit does not have a flexible slew rate adjustment mechanism, it will not be able to meet the slew rate requirements of different speeds. Summary of the Invention

[0004] In view of the existing technical problems, one object of the present invention is to provide a signal output device with an adjustable conversion rate to improve the existing technology.

[0005] The present invention includes a programmable slew The device is a signal output device for a signal rate, comprising: a plurality of output units. The output units are connected in parallel between the input end and the output end, respectively corresponding to the adjustable signal delay amount, and each output unit comprises: A delay path and an output circuit. The delay path is configured to provide an adjustable signal delay, receiving an input signal from an input terminal and delaying it to generate a delayed signal. The output circuit receives the delayed signal and generates an output signal to an output terminal. The output terminal outputs a total output signal based on the output signals generated by the output circuits of all output units, and the conversion rate of the total output signal is determined by the combination of the adjustable signal delays of the output units.

[0006] The features, implementation and efficacy of the present invention are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram showing a signal output device with an adjustable conversion rate according to an embodiment of the present invention; Figure 2A as well as Figure 2B 1. Each of the blocks shows a block diagram of an output unit in one embodiment of the present invention; Figure 3 A waveform diagram showing a total output signal output from an output terminal in one embodiment of the present invention; Figure 4 A block diagram showing an output unit according to another embodiment of the present invention; Figure 5 A block diagram of an output unit according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0008] One object of the present invention is to provide a signal output device with an adjustable conversion rate. By configuring output units corresponding to the adjustable signal delay amounts, the conversion rate of the total output signal is determined by the combination of the adjustable signal delay amounts set in different output units, thereby achieving a flexible output mechanism with adjustable conversion rate.

[0009] Please refer to Figure 1 . Figure 1 FIG. 1 is a block diagram showing a signal output device 100 with a programmable slew rate according to an embodiment of the present invention.

[0010] In one embodiment, the signal output device 100 can be used in a signal transmission interface such as, but not limited to, a High Definition Multimedia Interface (HDMI), a DisplayPort (DP), or a Universal Serial Bus (USB), and configured as a driver circuit in a signal output circuit (TX) to output a signal. However, the present invention is not limited thereto.

[0011] The signal output device 100 includes a plurality of output units 110 and a control circuit 120 .

[0012] The output unit 110 is connected in parallel between the input terminal IN and the output terminal OUT, respectively corresponding to the adjustable signal delay amount.

[0013] Please also refer to Figure 2A as well as Figure 2B . Figure 2A as well as Figure 2B 1 and 2 show a block diagram of an output unit 110 according to an embodiment of the present invention. The output unit 110 includes a delay path 200 and an output circuit 210 .

[0014] The delay path 200 is configured to provide an adjustable signal delay to receive an input signal SIN from an input terminal IN and delay the input signal SIN to generate a delayed signal SDE.

[0015] In this embodiment, the delay path 200 includes a multiplexer 220 , a first delay sub-path 230 , and a second delay sub-path 240 .

[0016] The first delay sub-path 230 is electrically coupled between the input terminal IN and the multiplexer 220 and has a first number M of delay elements for delaying the input signal SIN to generate a first delayed signal SD1 , where M is an integer greater than or equal to 0.

[0017] The second delay sub-path 240 is electrically coupled between the input terminal IN and the multiplexer 220 and has a second delay element number N different from the first delay element number M for delaying the input signal SIN to generate a second delayed signal SD2 , where N is an integer greater than or equal to 0.

[0018] exist Figure 2A In the embodiment, M=0 and N=1 are used as an example. Specifically, since the number of first delay elements M is 0, the first delay sub-path 230 does not include any delay elements. The first delayed signal SD1 is equivalent to the input signal SIN being directly output without delay. Since the number of second delay elements N is 1, the second delay sub-path 240 includes one delay element 250. When one delay element 250 can cause one unit of delay, the second delayed signal SD2 is equivalent to the input signal SIN being delayed by one unit of delay.

[0019] exist Figure 2B In the embodiment, M=1 and N=2 are used as an example. Specifically, since the number of first delay elements M is 1, the first delay sub-path 230 includes one delay element 250. The first delayed signal SD1 is equivalent to the input signal SIN being delayed by one unit. Since the number of second delay elements N is 2, the second delay sub-path 240 includes two delay elements 250. The second delayed signal SD2 is equivalent to the input signal SIN being delayed by two units.

[0020] It should be noted that the above values ​​of the number of first delay elements M and the number of second delay elements N are merely examples. In other embodiments, the number of first delay elements M and the number of second delay elements N may be set to other possible values. Furthermore, the first delay sub-paths 230 and the second delay sub-paths 240 corresponding to different output units 110 may also be configured with different combinations of the number of first delay elements M and the number of second delay elements N (e.g., some output units 110 may be configured with the number of first delay elements M and the number of second delay elements N). Figure 2A The output unit 110 is configured in the form of Figure 2B The present invention is not limited thereto.

[0021] Multiplexer 220 is configured to select one of the first delayed signal SD1 and the second delayed signal SD2 to output as delayed signal SDE. Therefore, the selection made by multiplexer 220 determines the corresponding adjustable signal delay of output unit 110. In one embodiment, multiplexer 220 makes this selection based on control of delay control signal DCS.

[0022] For example, in Figure 2A In the embodiment, when the multiplexer 220 selects the first delay sub-path 230 , the adjustable signal delay of the output unit 110 is set to 0. When the multiplexer 220 selects the second delay sub-path 240 , the adjustable signal delay of the output unit 110 is set to 1 unit of delay.

[0023] And in Figure 2B In the embodiment, when the multiplexer 220 selects the first delay sub-path 230, the adjustable signal delay of the output unit 110 is set to 1 delay unit. When the multiplexer 220 selects the second delay sub-path 240, the adjustable signal delay of the output unit 110 is set to 2 delay units.

[0024] The output circuit 210 receives the delay signal SDE and generates an output signal SO to the output terminal OUT. In one embodiment, the output circuit 210 is a flip-flop and includes a P-type transistor MP and an N-type transistor MN.

[0025] The P-type transistor MP is electrically coupled between the supply voltage terminal VDD and the connection terminal CT. More specifically, the source of the P-type transistor MP is electrically coupled to the supply voltage terminal VDD, and the drain of the P-type transistor MP is electrically coupled to the connection terminal CT. The connection terminal CT is electrically coupled to the output terminal OUT.

[0026] The N-type transistor MN is electrically coupled between the connection terminal CT and the ground terminal GND. More specifically, the drain of the N-type transistor MN is electrically coupled to the connection terminal CT, and the source of the N-type transistor MN is electrically coupled to the ground terminal GND.

[0027] The P-type transistor MP and the N-type transistor MN are controlled by the delay signal SDE and generate the output signal SO at the connection terminal CT. More specifically, the gates of the P-type transistor MP and the N-type transistor MN receive the delay signal SDE and are turned on or off according to the state of the delay signal SDE, thereby generating the output signal SO at the connection terminal CT.

[0028] For example, when the input signal SIN received by the delay path 200 is high, the delay signal SDE is also high, turning off the P-type transistor MP and turning on the N-type transistor MN. The turned-on N-type transistor MN has a corresponding on-resistance (Ron) and discharges the connection terminal CT, causing the output signal SO to be low.

[0029] When the input signal SIN received by the delay path 200 is low, the delay signal SDE is also low, turning on the P-type transistor MP and turning off the N-type transistor MN. The turned-on P-type transistor MP has a corresponding on-resistance value and charges the connection terminal CT, causing the output signal SO to be high.

[0030] It should be noted that the structure of the output circuit 210 is merely an example. In other embodiments, the output circuit 210 may be implemented by other types of circuits other than a trigger. The present invention is not limited thereto.

[0031] Figure 1 The output terminal OUT outputs the total output signal SOUT according to the output signal SO generated by the output circuit 210 of all the output units 110. In one embodiment, a load capacitor CL may be provided on the output terminal OUT.

[0032] The slew rate of the total output signal SOUT is determined by the combination of the adjustable signal delays of the output unit 110. The following describes how to set the adjustable signal delays and the relationship between the adjustable signal delays and the slew rate.

[0033] In one embodiment, Figure 1 The control circuit 120 is configured to generate a delay control signal DCS for each output unit 110, thereby controlling the selection of the multiplexer 220 in the delay path 200 of each output unit 110. By allocating the number of delay elements in the first delay sub-path 230 and the second delay sub-path 240 and selecting the delay sub-path according to the delay control signal DCS, the output unit 110 can have a specific combination of adjustable signal delays to achieve a desired conversion rate.

[0034] For example, by allocating the number of delay elements and selecting the delay control signal DCS, the output units 110 can be divided into multiple output groups. The output units 110 within each output group have the same adjustable signal delay, while the output units 110 in different output groups have different adjustable signal delays.

[0035] exist Figure 1 In the embodiment, the output unit 110 is divided into three output groups 130A, 130B, and 130C. A possible configuration will be described below.

[0036] Each output unit 110 of the output group 130A is Figure 2A The multiplexer 220 selects the first delay signal SD1 generated by the first delay sub-path 230 and outputs it as the delayed signal SDE, which is then processed by the output circuit 210 to generate the output signal SO. In this case, the adjustable signal delay corresponding to each output unit 110 of the output group 130A is 0.

[0037] Each output unit 110 of the output group 130B is Figure 2A The multiplexer 220 selects the second delayed signal SD2 generated by the second delay sub-path 240 and outputs it as the delayed signal SDE, which is then processed by the output circuit 210 to generate the output signal SO. In this case, the adjustable signal delay corresponding to each output unit 110 of the output group 130B is 1 unit of delay.

[0038] Each output unit 110 of the output group 130C is Figure 2B The multiplexer 220 selects the second delayed signal SD2 generated by the second delay sub-path 240 and outputs it as the delayed signal SDE, which is then processed by the output circuit 210 to generate the output signal SO. In this case, the adjustable signal delay corresponding to each output unit 110 of the output group 130B is 2 units of delay.

[0039] The following example uses the case where the number of output units 110 included in each of the output groups 130A, 130B, and 130C is equal and the total number is K (ie, each output group includes K / 3 output units 110). Figure 3 The process of the total output signal SOUT transitioning from a low state to a high state is described.

[0040] Please refer to Figure 3 . Figure 3 The waveform diagram of the total output signal SOUT outputted from the output terminal OUT in one embodiment of the present invention is shown. Figure 3 In the figure, the horizontal axis represents time and the vertical axis represents signal size.

[0041] exist Figure 3 , starting from time zero, time point T1 corresponds to a time length of 1 unit of delay, and time point T2 corresponds to a time length of 2 units of delay.

[0042] In this embodiment, the input signal SIN received by the output unit 110 changes from a high state to a low state, and the output signal SO generated by each output unit 110 changes from a low state to a high state, thereby causing the total output signal SOUT outputted by the output terminal OUT to also change from a low state to a high state.

[0043] Since the adjustable signal delay corresponding to each output unit 110 of the output group 130A is 0, each output unit 110 of the output group 130A generates the output signal SO from the time point 0 (e.g., ignoring the signal processing time of the output circuit 210). Therefore, between time point 0 and time point T1, the total output signal SOUT outputted by the output terminal OUT only includes the output signal SO generated by each output unit 110 of the output group 130A, and the signal level increases from 0 to the first potential LV1.

[0044] If the on-resistance of the P-type transistor MP in the output circuit 210 of the output cell 110 is R, and since the number of output cells 110 in the output group 130A is K / 3 and they are connected in parallel, the equivalent resistance of the output cells 110 in the output group 130A is R / (K / 3) = 3R / K. If the capacitance of the load capacitor CL at the output terminal OUT is C, the equivalent capacitive-resistive time constant of the output cell 110 between time 0 and time T1 is the product of the equivalent resistance of the output cell 110, 3R / K, and the capacitance of the load capacitor CL, i.e., (3R / K)×C = 3RC / K.

[0045] Because the adjustable signal delay corresponding to each output unit 110 of output group 130B is 1 unit of delay, each output unit 110 of output group 130B generates output signal SO starting at time T1. Therefore, between time T1 and time T2, the total output signal SOUT outputted by output terminal OUT will include the output signal SO generated by each output unit 110 of output groups 130A and 130B, thereby increasing the signal level from the first voltage level LV1 to the second voltage level LV2.

[0046] If the on-resistance of the P-type transistor MP in the output circuit 210 of the output cell 110 is R, and since the total number of output cells 110 in output groups 130A and 130B is 2K / 3 and they are connected in parallel, the equivalent resistance of the output cells 110 in output groups 130A and 130B is R / (2K / 3) = 3R / 2K. If the capacitance of the load capacitor CL at the output terminal OUT is C, the equivalent capacitive-resistive time constant of the output cells 110 in output groups 130A and 130B between time points T1 and T2 is (3R / 2K) × C = 3RC / 2K. When the equivalent capacitive-resistive time constant decreases, the total output signal SOUT rises faster between time points T1 and T2 than between time points 0 and T1.

[0047] Because the adjustable signal delay corresponding to each output unit 110 of output group 130C is 2 units of delay, each output unit 110 of output group 130C generates output signal SO starting at time T2. Therefore, after time T2, the total output signal SOUT outputted by the output terminal OUT will simultaneously include the output signal SO generated by each output unit 110 of output groups 130A, 130B, and 130C, and the signal level will then increase from the second voltage level LV2 to the third voltage level LV3.

[0048] If the on-resistance of the P-type transistor MP in the output circuit 210 of the output unit 110 is R, then since the total number of output units 110 in the output groups 130A, 130B, and 130C is K and they are connected in parallel, the equivalent resistance of the output units 110 in the output groups 130A, 130B, and 130C is R / K. If the capacitance of the load capacitor CL at the output terminal OUT is C, the equivalent capacitive-resistive time constant of the output unit 110 between time points T1 and T2 is R / K×C=RC / K. If the equivalent capacitive-resistive time constant further decreases, the total output signal SOUT rises faster after time point T2 than between time points T1 and T2.

[0049] In one embodiment, the time required for the total output signal SOUT to rise from 20% of its maximum value to 80% of its maximum value is defined as the rise time, while the equivalent slope between the signal value and time during this period is defined as the slew rate. In one embodiment, the slew rate of the total output signal SOUT is determined by a combination of adjustable signal delays of the output unit 110.

[0050] In more detail, the above Figure 3 As can be seen from the example, by dividing the output cells 110 into different groups and setting different adjustable signal delays, the signal transmission timing of the output circuit 210 of the output cells 110 in different groups can be different, thereby causing the equivalent resistance of the output cells 110 relative to the output terminal OUT to gradually increase over time. This configuration prolongs the rise time of the total output signal SOUT, thereby preventing the slew rate from being excessively high. Therefore, the combination of adjustable signal delays determines the slew rate of the total output signal SOUT.

[0051] For example, when the adjustable signal delay of at least some of the output units 110 is configured to a larger value, the rise time of the total output signal SOUT will be further prolonged, thereby further reducing the slew rate. Conversely, when the adjustable signal delay of at least some of the output units 110 is configured to a smaller value, the rise time of the total output signal SOUT will be shortened, thereby increasing the slew rate.

[0052] Furthermore, in one embodiment, the linearity of the total output signal SOUT is determined by the number of output groups and the number of output units in each output group.

[0053] In more detail, the above Figure 3 As can be seen from the example, when the combination of adjustable signal delay amounts includes more different adjustable signal delay values, the number of output groups increases, which increases the number of changes in the equivalent resistance value and the rise time can be divided into more different segments to rise slowly.

[0054] When the number of output units in each output group is different, the change in the equivalent resistance value of the output group is different, which may also affect the rise amplitude of the rise time of different segments. The rise time of each segment is related to the equivalent capacitance-resistance time constant.

[0055] Therefore, by properly selecting the number of output groups and the number of output units contained in the output groups, the linearity of signal transmission corresponding to each output group can be made closer to consistency, thereby improving the linearity of the overall conversion rate.

[0056] It should be noted that Figure 3 The embodiment of the invention is described by taking the case where the total output signal SOUT changes from a low state to a high state. Figure 3 The description above also applies to the fall time and corresponding slew rate when the total output signal SOUT transitions from a high state to a low state. The only difference is that when the total output signal SOUT transitions from a high state to a low state, the equivalent resistance value of the output unit 110 is related to the on-resistance value of the N-type transistor MN in the output circuit 210, resulting in a different equivalent capacitance-resistance time constant.

[0057] Please refer to Figure 4 . Figure 4 FIG. 2 is a block diagram showing an output unit 110 according to another embodiment of the present invention. Figure 4 The output unit 110 includes a delay path 400 and an output circuit 410 .

[0058] In this embodiment, the delay path 400 includes two delay elements 420 and two bypass elements 430. Each bypass element 430 is provided corresponding to a delay element 420 and is configured to bypass the corresponding delay element 420 when enabled and not to bypass the delay element 420 when disabled.

[0059] In one embodiment, Figure 1The control circuit 120 is configured to generate a delay control signal DCS for each output unit 110 to control the enabling or disabling of the bypass element 430 in the delay path 400 of each output unit 110. By controlling the delay element 420 to be bypassed or non-bypassed by the delay control signal DCS, the output unit 110 can have a specific combination of adjustable signal delays to achieve a desired conversion rate.

[0060] by Figure 4 For example, the delay control signal DCS may bypass all the delay elements 420 of a portion of the output cells 110, bypass one delay element 420 of another portion of the output cells 110, and not bypass all the delay elements 420 of yet another portion of the output cells 110. Figure 1 The three output groups 130A, 130B and 130C are shown, and correspond to adjustable signal delays of 0, 1 and 2 units of delay respectively. The total output signal SOUT can be achieved as follows by configuring the above output groups. Figure 3 The output effect is shown.

[0061] On the other hand, the output circuit 410 of this embodiment also includes a P-type transistor MP and an N-type transistor MN, and the connection method of the P-type transistor MP and the N-type transistor MN is the same as that of the output circuit 210 of Figure 2. However, the output circuit 410 further includes a first bias load transistor BP and a second bias load transistor BN.

[0062] A first bias load transistor BP and a P-type transistor MP are connected in series between a supply voltage terminal VDD and a connection terminal CT, and are controlled by a bias voltage VP to be normally on to serve as a load. A second bias load transistor BN and an N-type transistor MN are connected in series between the connection terminal CT and a ground terminal GND, and are controlled by a bias voltage VN to be normally on to serve as a load.

[0063] Please refer to Figure 5 . Figure 5 A block diagram of an output unit 110 according to another embodiment of the present invention is shown. Figure 5 The output unit 110 includes a delay path 500 and an output circuit 510 .

[0064] In this embodiment, the delay path 500 does not include any delay elements. The output circuit 510 can be configured as the output circuit 210 of FIG. 2 in this embodiment, or can be selectively configured as in other embodiments. Figure 4 The structure of the output circuit 410.

[0065] However, it should be noted that due to Figure 5The delay of the output unit 110 shown is not adjustable. Therefore, the signal output device 100 can only set part of the output unit 110 to Figure 5 and set the other output units 110 to Figure 2A 、 Figure 2B or Figure 4 form.

[0066] In some technologies, when all output units in a signal output device have the same delay, connecting them in parallel and simultaneously outputting signals results in a lower equivalent resistance, leading to a higher signal conversion rate. However, in some low-frequency signal output device applications, excessively high signal conversion rates are undesirable. For example, in 3 GHz high-definition multimedia interfaces, systems often require signal rise and fall times to be above 75 picoseconds.

[0067] The signal output device with adjustable conversion rate in the present invention utilizes output units with corresponding adjustable signal delays, allowing the conversion rate of the overall output signal to be determined by the combination of the different adjustable signal delays set for each output unit, thereby achieving a flexible output mechanism with adjustable conversion rate. In practical applications, the combination of adjustable signal delays will be determined based on the different signal transmission interfaces and frequency levels to achieve a desired conversion rate.

[0068] It should be noted that the above-mentioned implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0069] For example, the signal output device 100 can use all the output units 110 as Figure 2A and Figure 2B All output units 110 are configured in the form of Figure 4 or part of the output unit 110 is configured as Figure 2A and Figure 2B The output unit 110 is configured in the form of Figure 4 And, Figure 4 The output circuit 410 can be used with Figure 2A 、 Figure 2B The delay path 200 is set, and the output circuit 210 of FIG2 can be used with Figure 4 The present invention is not limited to a specific configuration.

[0070] In summary, the signal output device with adjustable conversion rate in the present invention configures output units corresponding to the adjustable signal delay amounts so that the conversion rate of the total output signal is determined by the combination of different adjustable signal delay amounts set in different output units, thereby achieving a flexible output mechanism with adjustable conversion rate.

[0071] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art may modify the technical features of this case based on the explicit or implicit content of this case. All such modifications may fall within the scope of the patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the claims of this application.

Explanation of symbols

[0072] 100:Signal output device 110: Output unit 120: Control circuit 130A, 130B, 130C: Output group 200: Delay path 210: Output circuit 220: Multitasker 230: First delay subpath 240: Second delay subpath 250: Delay component 400: Delayed Path 410: output circuit 420: Delay component 430:Bypass component 500: Delayed Path 510: output circuit BN: Second bias load transistor BP: First bias load transistor CL: load capacitance CT: Connector DCS: Delayed Control Signal GND: Ground terminal IN: Input terminal LV1: First potential LV2: Second potential LV3: Third potential MN: N-type transistor MP: P-type transistor OUT: output terminal SD1: First delayed signal SD2: Second delayed signal SDE: Delayed signal SIN: input signal SO: output signal SOUT: total output signal T1, T2: time points VDD: supply voltage terminal

Claims

1. A signal output device with an adjustable conversion rate, characterized in that: Include: A plurality of output units are connected in parallel between an input terminal and an output terminal, each corresponding to an adjustable signal delay. Each of the plurality of output units comprises: a delay path configured to provide the adjustable signal delay, to receive an input signal from the input end and delay the input signal, thereby generating a delayed signal; and an output circuit receiving the delayed signal and generating an output signal to an output terminal; The output end outputs a total output signal according to the output signals generated by the output circuits of all the output units, and a conversion rate of the total output signal is determined by a combination of the adjustable signal delay amounts of the output units.

2. The signal output device according to claim 1, wherein: The plurality of output units are divided into a plurality of output groups. The plurality of output units in each of the plurality of output groups have the same adjustable signal delay, while the plurality of output units in different output groups have different adjustable signal delays.

3. The signal output device according to claim 2, wherein: An equivalent capacitance-resistance time constant of the multiple output units is the product of an equivalent resistance value of the multiple output units and a capacitance value of a load capacitor at the output end. The number of the multiple output groups and the number of the multiple output units in each of the multiple output groups determine the multiple effective capacitance-resistance time constants, thereby determining the linearity of the conversion rate of the total output signal.

4. The signal output device according to claim 1, wherein: The delay path consists of: a multitasker; a first delay sub-path electrically coupled between the input terminal and the multiplexer, having a first number M of delay elements for delaying the input signal to generate a first delayed signal, wherein M is an integer greater than or equal to 0; as well as a second delay sub-path electrically coupled between the input terminal and the multiplexer, having a second number N of delay elements different from the first number M of delay elements, for delaying the input signal to generate a second delayed signal, wherein N is an integer greater than or equal to 0; The multiplexer is configured to select one of the first delayed signal and the second delayed signal and output it as the delayed signal.

5. The signal output device according to claim 4, wherein: The invention also includes a control circuit configured to generate a delay control signal for each of the plurality of output units to control the multiplexer to select.

6. The signal output device according to claim 1, wherein: The delay path of each of the plurality of output units comprises: at least one delay element; and At least one bypass element is configured to bypass the delay element when enabled and not to bypass the delay element when disabled.

7. The signal output device according to claim 6, wherein: The invention also includes a control circuit configured to generate a delay control signal for each of the plurality of output units to enable or disable the bypass element.

8. The signal output device according to claim 1, wherein: The delay paths of at least some of the output units do not include any delay elements.

9. The signal output device according to claim 1, wherein: The output circuit is a trigger and includes: a P-type transistor electrically coupled between a supply voltage terminal and a connection terminal, wherein the connection terminal is electrically coupled to the output terminal; and an N-type transistor electrically coupled between the connection terminal and a ground terminal; The P-type transistor and the N-type transistor are controlled by the delay signal and generate the output signal at the connection end.

10. The signal output device according to claim 9, wherein: The trigger also contains: a first bias load transistor connected in series with the P-type transistor between the supply voltage terminal and the connection terminal; and A second bias load transistor is connected in series with the N-type transistor between the connection terminal and the ground terminal.

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