Two-phase non-overlapping clock circuit, application method, equipment and storage medium
By combining delay circuits and clock shaping circuits, a stable non-overlapping clock signal is generated, which solves the problem of unstable timing of non-overlapping two-phase clock signals and improves the stability and consistency of the clock signal.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-14
AI Technical Summary
In the prior art, the non-overlap time of two-phase clock signals is easily affected by factors such as process parameter deviations, power supply voltage fluctuations and temperature changes, making it difficult to keep the non-overlap time stable and consistent.
By combining delay circuits and clock shaping circuits, the clock signals are delayed and shaped to generate first and second non-overlapping clock signals. The phase relationship is constrained by logic interlocking and shaping circuits.
It effectively reduces the impact of process parameter deviations, power supply voltage fluctuations, and temperature changes on clock phase relationships, and improves the stability and consistency of non-overlapping time between two non-overlapping clocks.
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Figure CN121864067A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuits, and more particularly to a two-phase non-overlapping clock circuit, application method, device, and storage medium. Background Technology
[0002] Nowadays, with the development of integrated circuits, the conversion of analog signals to digital signals has become a core part of the signal processing field. After analog signals are converted into digital signals through analog-to-digital conversion, a large number of digital algorithms can be used for data processing, significantly improving information utilization.
[0003] However, to obtain two non-overlapping clock signals, it is usually necessary to control the phase relationship of the clock signals. However, in actual circuit implementation, the generation method of the clock signal phase relationship is easily affected by factors such as process parameter deviations, power supply voltage fluctuations, and temperature changes, making it difficult to maintain a stable and consistent non-overlapping time between the two clock phases. Summary of the Invention
[0004] This application provides a two-phase non-overlapping clock circuit, application method, device, and storage medium that can improve the stability and consistency of the non-overlapping time between two-phase non-overlapping clocks.
[0005] In a first aspect, embodiments of this application provide a two-phase non-overlapping clock circuit, which includes at least a delay circuit and a clock shaping circuit;
[0006] The delay circuit is used to delay the input clock signal, which includes a reference clock signal and an inverted reference clock signal. The delay circuit includes at least a first delay circuit and a second delay circuit. The first delay circuit and the second delay circuit include a delay inverter and a load capacitor connected to the delay inverter. The first delay circuit is used to generate a first delayed clock signal, and the second delay circuit is used to generate a second delayed clock signal.
[0007] The clock shaping circuit is connected to the first delay circuit and the second delay circuit, and is used to perform logic interlocking and shaping processing on the clock signal, the first delayed clock signal and the second delayed clock signal, and output a first non-overlapping clock signal and a second non-overlapping clock signal.
[0008] One possible implementation of the delay inverter includes:
[0009] First transistor and second transistor;
[0010] The first transistor is connected in series with the second transistor;
[0011] The source of the first transistor is connected to a positive bias current source, and the source of the second transistor is connected to a negative bias current source.
[0012] The gates of the first transistor and the second transistor are connected together, serving as the input terminal of the delay inverter;
[0013] The drains of the first transistor and the second transistor are connected together, serving as the output terminal of the delay inverter.
[0014] In one possible implementation, one end of the load capacitor is connected to the output terminal of the delay inverter, and the other end of the load capacitor is grounded.
[0015] In one possible implementation, the delay circuit further includes a current mirror subtraction circuit, which is used to provide the output currents of the positive bias current source and the negative bias current source.
[0016] In one feasible implementation, the current mirror subtraction circuit includes a first current mirror unit, a second current mirror unit, and a shunt unit, wherein the output terminal of the shunt unit includes a first output terminal and a second output terminal.
[0017] The output terminal of the first current mirror unit is connected to the output terminal of the second current mirror unit, and the connection point serves as the input terminal of the shunt unit.
[0018] The first output terminal is connected to the input terminal of the positive bias current source, and the second output terminal is connected to the input terminal of the negative bias current source.
[0019] One feasible implementation of the clock shaping circuit includes:
[0020] The logic gate circuit includes a first AND gate circuit, a second AND gate circuit, a first shaper inverter, a second shaper inverter, a third shaper inverter, a fourth shaper inverter, and a fifth shaper inverter.
[0021] The input terminal of the first shaping inverter is connected to the input terminal of the reference clock signal, and the output terminal of the first shaping inverter is used to output the inverted reference clock signal;
[0022] The input terminal of the first AND gate circuit is connected to the input terminal of the reference clock signal and the output terminal of the third shaping inverter, respectively.
[0023] The input terminal of the second AND gate circuit is connected to the output terminal of the first shaping inverter and the output terminal of the second shaping inverter, respectively;
[0024] The input terminal of the second shaping inverter is connected to the output terminal of the first delay circuit, and the output terminal of the first delay circuit is used to output the first delayed clock signal;
[0025] The input terminal of the third shaping inverter is connected to the output terminal of the second delay circuit, and the output terminal of the second delay circuit is used to output the second delayed clock signal.
[0026] The output terminal of the second shaping inverter is connected to the input terminal of the fourth shaping inverter;
[0027] The output terminal of the third shaping inverter is connected to the input terminal of the fifth shaping inverter.
[0028] One feasible implementation of the clock shaping circuit includes:
[0029] A driving circuit, the driving circuit including a first driving circuit and a second driving circuit;
[0030] The output terminal of the fourth shaping inverter is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is used to output the first non-overlapping clock signal.
[0031] The output terminal of the fifth shaping inverter is connected to the input terminal of the second driving circuit, and the output terminal of the second driving circuit is used to output the second non-overlapping clock signal.
[0032] Secondly, embodiments of this application provide an application method for a two-phase non-overlapping clock circuit, which is applied to the two-phase non-overlapping clock circuit described in any of the first aspects;
[0033] A reference clock signal is input to a first delay circuit to obtain a first delayed clock signal; an inverted reference clock signal is input to a second delay circuit to obtain a second delayed clock signal, wherein the clock signal includes the reference clock signal and the inverted reference clock signal, and the delay times corresponding to the first delay circuit and the second delay circuit are different;
[0034] The clock signal, the first delayed clock signal, and the second delayed clock signal are logically interlocked and shaped using a clock shaping circuit to obtain a first non-overlapping clock signal and a second non-overlapping clock signal.
[0035] Thirdly, embodiments of this application provide an electronic device, the device including: a processor, a memory, and a system bus;
[0036] The processor and the memory are connected via the system bus;
[0037] The memory is used to store a program, which includes instructions that, when executed by the processor, cause the processor to perform any of the implementation steps of the application method of the two-phase non-overlapping clock circuit described above.
[0038] Fourthly, embodiments of this application provide a computer-readable storage medium for storing a computer program, which, when executed by a terminal device, implements any of the implementation steps of the application method for the above-described two-phase non-overlapping clock circuit.
[0039] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:
[0040] As can be seen from the above technical solution, the present invention provides a two-phase non-overlapping clock circuit, wherein the two-phase non-overlapping clock circuit includes at least a delay circuit and a clock shaping circuit. The delay circuit is used to delay the input clock signal, which includes a reference clock signal and an inverted reference clock signal. The delay circuit includes at least a first delay circuit and a second delay circuit, each including a delay inverter and a load capacitor connected to the delay inverter. The first delay circuit generates a first delayed clock signal, and the second delay circuit generates a second delayed clock signal. The clock shaping circuit, connected to the first and second delay circuits, performs logic interlocking and shaping processing on the clock signal, the first delayed clock signal, and the second delayed clock signal, outputting a first non-overlapping clock signal and a second non-overlapping clock signal.
[0041] As can be seen, this scheme, by setting up a first delay circuit and a second delay circuit, delays the clock signal for different durations, and then uses a clock shaping circuit to shape the delayed clock signal, thereby generating a first non-overlapping clock signal and a second non-overlapping clock signal. Therefore, by sending the clock signals through independent delay paths and constraining the phase relationship using a clock shaping circuit, this scheme can effectively control the non-overlapping time between two clock phases, thereby effectively reducing the impact of timing errors caused by process parameter deviations, power supply voltage fluctuations, and temperature changes on the clock phase relationship, and improving the stability and consistency of the non-overlapping time between the two non-overlapping clock phases. Attached Figure Description
[0042] Figure 1 A schematic diagram of a two-phase non-overlapping clock circuit provided in an embodiment of this application;
[0043] Figure 2 A circuit schematic diagram of a two-phase non-overlapping clock circuit provided for an embodiment of this application;
[0044] Figure 3A circuit schematic diagram of a delay circuit provided in an embodiment of this application;
[0045] Figure 4 An equivalent circuit diagram for charging a load capacitor is provided in an embodiment of this application;
[0046] Figure 5 An equivalent circuit diagram of a load capacitor during discharge is provided in an embodiment of this application;
[0047] Figure 6 A schematic diagram of a current mirror subtraction circuit provided in an embodiment of this application;
[0048] Figure 7 An application method for a two-phase non-overlapping clock circuit provided in this application embodiment;
[0049] Figure 8 This is a schematic diagram illustrating the output result of a two-phase non-overlapping clock signal provided in an embodiment of this application. Detailed Implementation
[0050] As mentioned earlier, to obtain two non-overlapping clock signals, it is usually necessary to control the phase relationship of the clock signals. However, in actual circuit implementation, the generation method of the clock signal phase relationship is easily affected by factors such as process parameter deviations, power supply voltage fluctuations, and temperature changes, making it difficult to maintain a stable and consistent non-overlapping time between the two clock phases.
[0051] To address the aforementioned problems, this application provides a two-phase non-overlapping clock circuit, an application method, an apparatus, and a storage medium. The two-phase non-overlapping clock circuit includes at least a delay circuit and a clock shaping circuit. The delay circuit delays an input clock signal, which includes a reference clock signal and an inverted reference clock signal. The delay circuit includes at least a first delay circuit and a second delay circuit, each including a delay inverter and a load capacitor connected to the delay inverter. The first delay circuit generates a first delayed clock signal, and the second delay circuit generates a second delayed clock signal. The clock shaping circuit, connected to the first and second delay circuits, performs logic interlocking and shaping processing on the clock signal, the first delayed clock signal, and the second delayed clock signal, outputting a first non-overlapping clock signal and a second non-overlapping clock signal.
[0052] As can be seen, this scheme, by setting up a first delay circuit and a second delay circuit, delays the clock signal for different durations, and then uses a clock shaping circuit to shape the delayed clock signal, thereby generating a first non-overlapping clock signal and a second non-overlapping clock signal. Therefore, by sending the clock signals through independent delay paths and constraining the phase relationship using a clock shaping circuit, this scheme can effectively control the non-overlapping time between two clock phases, thereby effectively reducing the impact of timing errors caused by process parameter deviations, power supply voltage fluctuations, and temperature changes on the clock phase relationship, and improving the stability and consistency of the non-overlapping time between the two non-overlapping clock phases.
[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0054] Figure 1 This is a schematic diagram of a two-phase non-overlapping clock circuit provided as an embodiment of this application. (In conjunction with...) Figure 1 As shown, the two-phase non-overlapping clock circuit in this embodiment includes at least two core modules: a delay circuit and a clock shaping circuit. The delay circuit is used to delay the incoming clock signal, which includes a reference clock signal and an inverted reference clock signal. The clock shaping circuit is used to perform logic interlocking and shaping on the clock signal, the first delayed clock signal, and the second delayed clock signal.
[0055] Specifically Figure 2 A circuit schematic diagram of a two-phase non-overlapping clock circuit provided in this application embodiment, combined with... Figure 2 It can be seen that the delay circuit includes at least a first delay circuit and a second delay circuit, and the clock shaping circuit is connected to the first delay circuit and the second delay circuit. The clock shaping circuit includes logic gate circuits and driver circuits. The logic gate circuits include a first AND gate circuit ADD1, a second AND gate circuit ADD2, a first shaping inverter INV1, a second shaping inverter INV2, a third shaping inverter INV3, a fourth shaping inverter INV4, and a fifth shaping inverter INV5. The driver circuit includes a first driver circuit BUFFER1 and a second driver circuit BUFFER2.
[0056] The specific connection relationship is as follows: the input terminal of the first shaping inverter INV1 is connected to the input terminal of the reference clock signal, and the output terminal of the first shaping inverter INV1 is used to output the inverted reference clock signal; the input terminal of the first AND gate circuit ADD1 is connected to the input terminal of the reference clock signal and the output terminal of the third shaping inverter INV3 respectively; the input terminal of the second AND gate circuit ADD2 is connected to the output terminal of the first shaping inverter INV1 and the output terminal of the second shaping inverter INV2 respectively.
[0057] Furthermore, the input terminal of the second shaping inverter INV2 is connected to the output terminal of the first delay circuit, and the output terminal of the first delay circuit is used to output the first delayed clock signal; the input terminal of the third shaping inverter INV3 is connected to the output terminal of the second delay circuit, and the output terminal of the second delay circuit is used to output the second delayed clock signal; the output terminal of the second shaping inverter INV2 is connected to the input terminal of the fourth shaping inverter INV4; and the output terminal of the third shaping inverter INV3 is connected to the input terminal of the fifth shaping inverter INV5.
[0058] Next, the output of the fourth shaping inverter INV4 is connected to the input of the first driving circuit BUFFER1; the output of the first driving circuit BUFFER1 is used to output the first non-overlapping clock signal; the output of the fifth shaping inverter INV5 is connected to the input of the second driving circuit BUFFER2; the output of the second driving circuit BUFFER2 is used to output the second non-overlapping clock signal.
[0059] It should be noted that, Figure 3 This application provides a circuit schematic diagram of a delay circuit. The delay circuit includes a delay inverter and a load capacitor connected to the delay inverter. The input terminal of the delay inverter is connected to a clock signal, and the output terminal of the delay inverter is connected to one end of the load capacitor, while the other end of the load capacitor is grounded. Through the delay inverter and the load resistor, a first delay circuit in the delay circuit generates a first delayed clock signal, and a second delay circuit in the delay circuit generates a second delayed clock signal.
[0060] Combination Figure 3 Further analysis reveals that the delayed inverter in this embodiment is composed of a first transistor and a second transistor connected in series. The source of the first transistor is connected to a positive bias current source, and the source of the second transistor is connected to a negative bias current source. The gates of the first and second transistors are shared as the input terminal of the delayed inverter. The drains of the first and second transistors are shared as the output terminal of the delayed inverter. Specifically, the first transistor can be a PMOS transistor, and the second transistor can be an NMOS transistor.
[0061] Furthermore, to analyze the timing characteristics of the delay circuit during the charging process of the load capacitor in depth, the relevant circuit formulas are derived below based on specific operating conditions: When the clock signal is a step signal from 1 to 0, the pull-up PMOS transistor is turned on, the NMOS transistor is turned off, the output is high, and the load capacitor... Charging begins; at this point, the switching circuit can be equivalent to a first-order RC network, such as... Figure 4 An equivalent circuit diagram for charging a load capacitor is provided in this application embodiment. Figure 4 It can be seen that when the input signal is a step signal from 1 to 0, the output transitions from 0 to 1. The specific derivation conditions are as follows:
[0062] ;
[0063] ;
[0064] in, The output voltage of the delay inverter. This is the power supply voltage. This is the drain-source voltage of the PMOS transistor (the voltage difference between the drain and source). It is the gate-source voltage (the voltage difference between the gate and the source). This is the input voltage of the time-delay inverter.
[0065] By PMOS transistor Load capacitance at the node During charging, the current flowing through the PMOS transistor is obtained. :
[0066] ;
[0067] Ignoring channel length modulation effects, the IV output characteristic of the PMOS transistor in the linear region is:
[0068] ;
[0069] Ignoring channel length modulation effects, the IV output characteristic of the PMOS transistor in the saturation region is:
[0070] ;
[0071] in, This is the threshold voltage of the PMOS transistor. The carrier mobility in the PMOS transistor. This refers to the oxide capacitance per unit area of the PMOS transistor. This refers to the channel width of the PMOS transistor. This represents the channel length of the PMOS transistor.
[0072] Assuming the clock signal is an ideal step signal, it is known that , ,Right now:
[0073] ;
[0074] ;
[0075] Therefore, in At that time, the PMOS transistor is in the saturation region; At that time, the PMOS transistor is in the linear region.
[0076] when At this time, the PMOS transistor is in the saturation region. According to the output characteristics of the PMOS transistor, the output current of the PMOS transistor at this time is... for:
[0077] ;
[0078] Therefore, we can calculate that:
[0079] ;
[0080] The characteristic time constant of a PMOS transistor Normalization factor of PMOS threshold voltage In this case, for Normalization yields:
[0081] ;
[0082] Integrating both sides of the equation, we get:
[0083] ;
[0084] in, This is the normalized voltage value at which the output voltage reaches the threshold voltage of the PMOS transistor. This is the normalized voltage value when the output voltage reaches 0.1.
[0085] By integrating the calculations, the first charging time corresponding to the saturation region of the PMOS transistor can be obtained. for:
[0086] ;
[0087] when At this time, the PMOS transistor is in the linear region. Based on the output characteristics of the PMOS transistor, the output current of the PMOS transistor at this time... for:
[0088] ;
[0089] exist In this case, for Normalization yields:
[0090] ;
[0091] Integrating both sides of the equation, we get:
[0092] ;
[0093] in, This is the normalized voltage value when the output voltage reaches 0.9.
[0094] By integrating the calculations, the second charging time corresponding to the linear region of the PMOS transistor can be obtained. for:
[0095] ;
[0096] In summary, the rise time of the input clock signal in the delay circuit is... for:
[0097] ;
[0098] ;
[0099] Similarly, when the clock signal is a step signal from 0 to 1, the pull-down NMOS transistor is turned on, the PMOS transistor is turned off, the output is low, and the load capacitor... Discharge begins; at this point, the switching circuit can be equivalent to a first-order RC network, such as... Figure 5 An equivalent circuit diagram of a load capacitor during discharge is provided in an embodiment of this application. Figure 5 It can be seen that when the input signal is a step signal from 0 to 1, the output transitions from 1 to 0. The specific derivation conditions are as follows:
[0100] ;
[0101] ;
[0102] By NMOS transistor Load capacitance at the node Discharging allows us to obtain the current flowing through the NMOS transistor. for:
[0103] ;
[0104] Ignoring channel length modulation effects, the IV output characteristic of the NMOS transistor in the linear region is:
[0105] ;
[0106] Ignoring channel length modulation effects, the IV output characteristic of the NMOS transistor in the saturation region is:
[0107] ;
[0108] in, This is the threshold voltage of the NMOS transistor. The carrier mobility in an NMOS transistor. The capacitance per unit area of the oxide layer of the NMOS transistor. The channel width of the NMOS transistor. This represents the channel length of the NMOS transistor.
[0109] Assuming the clock signal is an ideal step signal, it is known that ,Right now:
[0110] ;
[0111] ;
[0112] Therefore, in At that time, the NMOS transistor is in the saturation region; At that time, the NMOS transistor is in the linear region.
[0113] Similarly, based on the above analysis, the discharge time corresponding to the saturation region of the NMOS transistor can be obtained. for:
[0114] ;
[0115] Among them, the characteristic time constant of the NMOS transistor Normalization factor of NMOS transistor threshold voltage .
[0116] Based on this, the delay time of the delay circuit can be further determined. The calculation model is as follows:
[0117] ;
[0118] ;
[0119] in, The delay time for the clock signal to transition from a high input level to a low output level. This is the delay time for the clock signal to transition from a low input level to a high output level. This represents the voltage change during the transition from a high level to a low level. This represents the voltage change during the transition from a low level to a high level. This represents the average discharge current of the NMOS transistor. The average charging current of the PMOS transistor is calculated by taking half of the maximum on-state current as the average current, i.e.:
[0120] ;
[0121] ;
[0122] in, The conductivity factor of an NMOS transistor. Given the conductivity factor of the PMOS transistor, the delay time can be obtained. for:
[0123] ;
[0124] ;
[0125] in, This is the ratio of the characteristic time constant of a PMOS transistor to that of an NMOS transistor.
[0126] Furthermore, embodiments of this application can also establish circuit equations in the complex frequency domain based on first-order RC circuits using PMOS and NMOS transistors to obtain the delay time of the delay circuit. Another calculation model is as follows:
[0127] Taking the discharge branch of an NMOS transistor as an example, its S-domain circuit equation is:
[0128] ;
[0129] in, This is the equivalent resistance of the discharge branch of the NMOS transistor.
[0130] Performing an inverse Laplace transform on the above equation yields a time-domain voltage expression:
[0131] ;
[0132] Based on the delay characteristics of a first-order RC circuit, the core formula for calculating the delay time can be derived:
[0133] ;
[0134] ;
[0135] Therefore, the delay time can be obtained. for:
[0136] ;
[0137] in, and For NMOS and PMOS transistors from arrive Average resistance between and The average resistance of the NMOS transistor For example:
[0138] ;
[0139] ;
[0140] ;
[0141] ;
[0142] in, This is the channel length modulation factor of the NMOS transistor. This is the saturation drain current of the NMOS transistor. This is the saturation drain voltage of the NMOS transistor.
[0143] The average resistance of the NMOS transistor is the average of the two instantaneous resistances mentioned above:
[0144] ;
[0145] According to the Taylor expansion, we further obtain:
[0146] ;
[0147] Therefore, the average resistance of the NMOS transistor can be calculated. Approximately:
[0148] ;
[0149] Similarly, due to the PMOS transistor's The same method can be used to derive it, so it will not be elaborated here.
[0150] It should be noted that, to simplify the calculation, the embodiments of this application make the following approximate assumptions in the derivation of the above formulas, namely, the input voltage of the delay circuit... This can be a step signal, ignoring the intrinsic delay of PMOS and NMOS transistors, and the load capacitance. The capacitor is fixed. Since all assumptions are based on the differences in signal characteristics and parameter magnitudes of the actual circuit, they will not affect the core analysis accuracy of the delay characteristics; therefore, such assumptions are reasonable.
[0151] Furthermore, the delay circuit in this embodiment also includes a current mirror subtraction circuit. Based on the output current provided by the current mirror subtraction circuit to the positive bias current source and the negative bias current source, the stability of the timing characteristics of the delay circuit is ensured. Figure 6 The schematic diagram of a current mirror subtraction circuit provided in this application embodiment, as shown in Figure 6, includes a first current mirror unit, a second current mirror unit, and a shunt unit. Each of the first and second current mirror units is equipped with upper and lower sets of current mirror circuits, and their output terminals are connected to form a node P, which serves as the input terminal of the shunt unit. The output terminals of the shunt unit include a first output terminal and a second output terminal. The output terminals of the first and second current mirror units are connected, and the connection point serves as the input terminal of the shunt unit. The first output terminal is connected to the input terminal of a positive bias current source, and the second output terminal is connected to the input terminal of a negative bias current source.
[0152] When the current mirror subtraction circuit enters the working state, the output currents of the first current mirror unit and the second current mirror unit are calculated at node P. The calculated difference current is transmitted to the shunt unit and distributed to its corresponding two branches. The currents of these two branches are supplied to the positive bias current source and the negative bias current source, respectively. In this way, the output currents of the two bias current sources can be precisely controlled, thereby effectively ensuring the stability of the timing characteristics of the delay circuit.
[0153] This application does not limit the specific parameter configuration and application form of the current mirror subtraction circuit, which can be flexibly adjusted and adapted according to the needs of the actual scenario. For example, when the output current ratio of the first current mirror unit and the second current mirror unit is approximately 1:1, the current subtraction operation implemented by this circuit can achieve a current attenuation effect of 100:1, thereby efficiently generating the small-amplitude operating current required during the operation of the delay circuit.
[0154] As can be seen from the above analysis, the two-phase non-overlapping clock circuit provided by the present invention includes at least a delay circuit and a clock shaping circuit. The delay circuit is used to delay the input clock signal, which includes a reference clock signal and an inverted reference clock signal. The delay circuit includes at least a first delay circuit and a second delay circuit, each including a delay inverter and a load capacitor connected to the delay inverter. The first delay circuit generates a first delayed clock signal, and the second delay circuit generates a second delayed clock signal. The clock shaping circuit, connected to the first and second delay circuits, performs logic interlocking and shaping processing on the clock signal, the first delayed clock signal, and the second delayed clock signal, outputting a first non-overlapping clock signal and a second non-overlapping clock signal.
[0155] As can be seen, this scheme, by setting up a first delay circuit and a second delay circuit, delays the clock signal for different durations, and then uses a clock shaping circuit to shape the delayed clock signal, thereby generating a first non-overlapping clock signal and a second non-overlapping clock signal. Therefore, by sending the clock signals through independent delay paths and constraining the phase relationship using a clock shaping circuit, this scheme can effectively control the non-overlapping time between two clock phases, thereby effectively reducing the impact of timing errors caused by process parameter deviations, power supply voltage fluctuations, and temperature changes on the clock phase relationship, and improving the stability and consistency of the non-overlapping time between the two non-overlapping clock phases.
[0156] Furthermore, Figure 7 This application provides an method for applying a two-phase non-overlapping clock circuit. Combined with... Figure 7 As shown, it may include steps S701-S702.
[0157] S701: Input the reference clock signal to the first delay circuit to obtain the first delayed clock signal; input the inverted reference clock signal to the second delay circuit to obtain the second delayed clock signal, wherein the clock signal includes the reference clock signal and the inverted reference clock signal, and the delay times corresponding to the first delay circuit and the second delay circuit are different.
[0158] In this embodiment, the reference clock signal is input to the first delay circuit via ADD1 to obtain the first delayed clock signal, while the inverted reference clock signal, shaped by the first shaping inverter in the clock shaping circuit, is input to the second delay circuit via ADD2 to obtain the second delayed clock signal. It should be noted that the load capacitors in the first and second delay circuits have different capacitance values, resulting in different delay times for the first and second delay circuits.
[0159] S702: Based on the clock shaping circuit, the clock signal, the first delayed clock signal and the second delayed clock signal are logically interlocked and shaped to obtain the first non-overlapping clock signal and the second non-overlapping clock signal.
[0160] In the embodiments of this application, the clock shaping circuit includes logic gate circuits and driving circuits, wherein the logic gate circuits include ADD1, ADD2, INV1, INV2, INV3, INV4 and INV5, and the driving circuits include BUFFER1 and BUFFER2.
[0161] As can be seen from the above embodiments, the clock shaping circuit in the embodiments of this application can realize logical interlocking and shaping of the clock signal, the first delayed clock signal and the second delayed clock signal, thereby outputting the first non-overlapping clock signal and the second non-overlapping clock signal.
[0162] Furthermore, Figure 8 This application provides a schematic diagram of the output result of a two-phase non-overlapping clock signal, combined with... Figure 8 As can be seen, the diagram clearly presents the timing relationship between the reference clock signal, the first non-overlapping clock signal, and the second non-overlapping clock signal. Using the reference clock signal as the timing reference, the first and second non-overlapping clock signals are complementary clocks generated from it, with a non-overlapping interval of duration t1 between them. Simultaneously, the effective level of the first non-overlapping clock signal lasts for duration t2, while the second non-overlapping clock signal remains at an inactive level during this t2 time period. Through the coordination of the non-overlapping interval t1 and the effective duration t2, the core characteristic of non-overlapping two-phase clocks is achieved.
[0163] Furthermore, embodiments of this application also provide an electronic device, including: a processor, a memory, and a system bus;
[0164] The processor and the memory are connected via the system bus;
[0165] The memory is used to store one or more programs, the one or more programs including instructions that, when executed by the processor, cause the processor to perform any of the implementation steps of the above-described application method of the two-phase non-overlapping clock circuit.
[0166] Furthermore, embodiments of this application also provide a computer-readable storage medium for storing a computer program, which, when executed by a terminal device, implements any of the implementation steps of the above-described application method for a two-phase non-overlapping clock circuit.
[0167] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application. It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on describing the differences from other embodiments. The same or similar parts between the various embodiments can be referred to mutually.
[0168] The system disclosed in the embodiments is described simply because it corresponds to the method disclosed in the embodiments; relevant details can be found in the method section.
[0169] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0170] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A two-phase non-overlapping clock circuit, characterized in that, The two-phase non-overlapping clock circuit includes at least a delay circuit and a clock shaping circuit; The delay circuit is used to delay the input clock signal, which includes a reference clock signal and an inverted reference clock signal. The delay circuit includes at least a first delay circuit and a second delay circuit. The first delay circuit and the second delay circuit include a delay inverter and a load capacitor connected to the delay inverter. The first delay circuit is used to generate a first delayed clock signal, and the second delay circuit is used to generate a second delayed clock signal. The clock shaping circuit is connected to the first delay circuit and the second delay circuit, and is used to perform logic interlocking and shaping processing on the clock signal, the first delayed clock signal and the second delayed clock signal, and output a first non-overlapping clock signal and a second non-overlapping clock signal.
2. The two-phase non-overlapping clock circuit according to claim 1, characterized in that, The delay inverter includes: First transistor and second transistor; The first transistor is connected in series with the second transistor; The source of the first transistor is connected to a positive bias current source, and the source of the second transistor is connected to a negative bias current source. The gates of the first transistor and the second transistor are connected together, serving as the input terminal of the delay inverter; The drains of the first transistor and the second transistor are connected together, serving as the output terminal of the delay inverter.
3. The two-phase non-overlapping clock circuit according to claim 1, characterized in that, One end of the load capacitor is connected to the output terminal of the delay inverter, and the other end of the load capacitor is grounded.
4. The two-phase non-overlapping clock circuit according to claim 2, characterized in that, The delay circuit further includes a current mirror subtraction circuit, which is used to provide the output current of the positive bias current source and the negative bias current source.
5. The two-phase non-overlapping clock circuit according to claim 4, characterized in that, The current mirror subtraction circuit includes a first current mirror unit, a second current mirror unit, and a shunt unit. The output terminals of the shunt unit include a first output terminal and a second output terminal. The output terminal of the first current mirror unit is connected to the output terminal of the second current mirror unit, and the connection point serves as the input terminal of the shunt unit. The first output terminal is connected to the input terminal of the positive bias current source, and the second output terminal is connected to the input terminal of the negative bias current source.
6. The two-phase non-overlapping clock circuit according to claim 1, characterized in that, The clock shaping circuit includes: The logic gate circuit includes a first AND gate circuit, a second AND gate circuit, a first shaper inverter, a second shaper inverter, a third shaper inverter, a fourth shaper inverter, and a fifth shaper inverter. The input terminal of the first shaping inverter is connected to the input terminal of the reference clock signal, and the output terminal of the first shaping inverter is used to output the inverted reference clock signal; The input terminal of the first AND gate circuit is connected to the input terminal of the reference clock signal and the output terminal of the third shaping inverter, respectively. The input terminal of the second AND gate circuit is connected to the output terminal of the first shaping inverter and the output terminal of the second shaping inverter, respectively; The input terminal of the second shaping inverter is connected to the output terminal of the first delay circuit, and the output terminal of the first delay circuit is used to output the first delayed clock signal; The input terminal of the third shaping inverter is connected to the output terminal of the second delay circuit, and the output terminal of the second delay circuit is used to output the second delayed clock signal. The output terminal of the second shaping inverter is connected to the input terminal of the fourth shaping inverter; The output terminal of the third shaping inverter is connected to the input terminal of the fifth shaping inverter.
7. The two-phase non-overlapping clock circuit according to claim 6, characterized in that, The clock shaping circuit includes: A driving circuit, the driving circuit including a first driving circuit and a second driving circuit; The output terminal of the fourth shaping inverter is connected to the input terminal of the first driving circuit, and the output terminal of the first driving circuit is used to output the first non-overlapping clock signal. The output terminal of the fifth shaping inverter is connected to the input terminal of the second driving circuit, and the output terminal of the second driving circuit is used to output the second non-overlapping clock signal.
8. An application method for a two-phase non-overlapping clock circuit, characterized in that, Applied to the two-phase non-overlapping clock circuit according to any one of claims 1-7; A reference clock signal is input to a first delay circuit to obtain a first delayed clock signal; an inverted reference clock signal is input to a second delay circuit to obtain a second delayed clock signal, wherein the clock signal includes the reference clock signal and the inverted reference clock signal, and the delay times corresponding to the first delay circuit and the second delay circuit are different; The clock signal, the first delayed clock signal, and the second delayed clock signal are logically interlocked and shaped using a clock shaping circuit to obtain a first non-overlapping clock signal and a second non-overlapping clock signal.
9. An electronic device, characterized in that, The device includes: a processor, a memory, and a system bus; The processor and the memory are connected via the system bus; The memory is used to store a program, the program including instructions that, when executed by the processor, cause the processor to perform the steps of the application method of the two-phase non-overlapping clock circuit of claim 8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which, when executed by a terminal device, implements the steps of the application method of the two-phase non-overlapping clock circuit as described in claim 8.