Memory chip and preparation method thereof

Abstract

The invention provides a storage chip and a preparation method of the storage chip, the storage chip provided by the invention comprises a storage wafer and a control wafer, and the storage wafer and the control wafer are stacked and are in bonding connection through a three-dimensional heterogeneous integrated structure; the storage wafer comprises a first substrate and a plurality of storage units, the control wafer comprises a second substrate and a plurality of control units, and the control units are connected with the storage units and control the storage units to perform read-write operation; the storage wafer comprises a magnetoresistive random access memory; the control wafer includes at least one of a carbon nanotube transistor and a two-dimensional material-based transistor. The memory chip has the characteristics of low power consumption and high data transmission speed, the preparation process of the control wafer is convenient to be compatible with the subsequent process of the chip, and the product reliability is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory chip and a method for preparing the memory chip. Background Art

[0002] The traditional von Neumann architecture separates memory and computing units, making the functions of each computer component more clearly defined and relatively easy to design and implement. The designs of the memory and computing units can be optimized to address their respective characteristics, improving their respective performance. For example, the memory can focus on improving storage capacity and data read / write speeds, while the computing unit can focus on improving computational speed and processing power. The independence of the memory from the computing unit allows for flexible data sharing and transfer between different computing tasks. The computing unit can read and process different data from the memory as needed, and then store the processed data back in the memory for use in other computing tasks. This flexibility facilitates complex computing tasks and diverse applications. However, the relatively slow data transfer speed between the memory and the computing unit has become a bottleneck restricting overall computer performance. Frequent data transfer between the memory and the computing unit consumes significant energy. Summary of the Invention

[0003] The present invention mainly provides a memory chip and a method for preparing the memory chip. The memory chip has the characteristics of low power consumption and high speed.

[0004] To solve the above technical problems, the first technical solution adopted by the present invention is: providing a memory chip, comprising: a memory wafer and a control wafer, wherein the memory wafer and the control wafer are stacked and bonded via a three-dimensional heterogeneous integrated structure;

[0005] The storage wafer includes a first substrate and a plurality of storage units, and the control wafer includes a second substrate and a plurality of control units. The control units are connected to the storage units and control the storage units to perform read and write operations.

[0006] The storage wafer includes a magnetoresistive random access memory; the control wafer includes at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials.

[0007] In one embodiment, the memory wafer further comprises a first bonding layer disposed on a side of the plurality of memory cells away from the first substrate; the control wafer further comprises a second bonding layer disposed on a side of the plurality of control cells away from the second substrate; wherein the first bonding layer and the second bonding layer are bonded to form a three-dimensional heterogeneous integrated structure; or

[0008] The memory wafer further comprises a first bonding layer disposed on a side of the plurality of memory cells away from the first substrate; the control wafer further comprises a second bonding layer disposed on a side of the second substrate away from the plurality of control cells; wherein the first bonding layer and the second bonding layer are bonded to form a three-dimensional heterogeneous integrated structure; or

[0009] The memory wafer further comprises a first bonding layer disposed on a side of the first substrate away from the plurality of memory cells; the control wafer further comprises a second bonding layer disposed on a side of the plurality of control cells away from the second substrate; wherein the first bonding layer and the second bonding layer are bonded to form a three-dimensional heterogeneous integrated structure; or

[0010] The storage wafer also includes a first bonding layer arranged on a side of the first substrate away from the plurality of storage units; the control wafer also includes a second bonding layer arranged on a side of the second substrate away from the plurality of control units; wherein the first bonding layer and the second bonding layer are bonded to form a three-dimensional heterogeneous integrated structure.

[0011] In one embodiment, the memory wafer further includes a first bonding layer disposed on a side of the plurality of memory cells away from the first substrate, and a third bonding layer disposed on a side of the first substrate away from the plurality of memory cells;

[0012] The control wafer also includes a second bonding layer arranged on the side of the control units away from the second substrate; the second bonding layer of one control wafer is bonded to the first bonding layer, and the second bonding layer of another control wafer is bonded to the third bonding layer.

[0013] In one embodiment, the control wafer further includes a second bonding layer disposed on a side of the plurality of control units away from the second substrate, and a fourth bonding layer disposed on a side of the second substrate away from the plurality of control units;

[0014] The memory wafer further includes a first bonding layer arranged on a side of the plurality of memory cells away from the first substrate; the first bonding layer of one memory wafer is bonded to the second bonding layer, and the first bonding layer of another memory wafer is bonded to the fourth bonding layer.

[0015] In one embodiment, at least two memory wafers are stacked and bonded, and are disposed on the same side of the control wafer; or

[0016] At least two control wafers are stacked and bonded, and are arranged on the same side of the memory wafer.

[0017] In one embodiment, each control unit includes: a read control unit for controlling data reading and a write control unit for controlling data writing, the read control unit is a carbon nanotube transistor, and / or the write control unit is a carbon nanotube transistor; or

[0018] Each control unit includes a read / write control unit for controlling data reading and writing, and the read / write control unit is a carbon nanotube transistor.

[0019] In one embodiment, there are multiple control wafers, and the control units in some of the control wafers serve as slave control units, while the control units in the remaining control wafers serve as master control units.

[0020] The master control unit and the slave control unit are respectively connected to the same storage unit, and the slave control unit is used to perform read and write operations on the storage unit instead of the master control unit.

[0021] In one embodiment, the memory chip further includes a heat dissipation layer disposed between the control wafer and the memory wafer;

[0022] The heat dissipation layer includes carbon nanotubes.

[0023] In one embodiment, the memory chip further includes: a sensing component; the sensing component is disposed in a memory wafer or a control wafer; or, the sensing component is independently disposed in a sensing wafer, and the sensing wafer, the memory wafer, and the control wafer are stacked and bonded together through a three-dimensional heterogeneous integrated structure.

[0024] To solve the above technical problems, the second technical solution adopted by the present invention is to provide a method for preparing a memory chip, comprising:

[0025] A memory wafer and a control wafer are provided; the memory wafer includes a first substrate and a plurality of memory cells, and the control wafer includes a second substrate and a plurality of control cells; the memory cells include magnetoresistive random access memories; and the control cells include at least one of carbon nanotube transistors and transistors based on two-dimensional materials;

[0026] The storage wafer and the control wafer are stacked and arranged, and a three-dimensional heterogeneous integrated structure is arranged to bond the storage wafer and the control wafer together; the control unit is connected to the storage unit and controls the storage unit to perform read and write operations.

[0027] The present invention has the following beneficial effects: Unlike the prior art, the memory chip provided by the present invention comprises: a memory wafer and a control wafer, the memory wafer and the control wafer being stacked and bonded together via a three-dimensional heterogeneous integrated structure; the memory wafer comprising a first substrate and a plurality of memory cells; the control wafer comprising a second substrate and a plurality of control units, the control units being connected to the memory cells to control read and write operations of the memory cells; the memory wafer comprising a magnetoresistive random access memory; and the control wafer comprising at least one of a carbon nanotube transistor and a transistor based on a two-dimensional material. This memory chip has the characteristics of low power consumption and fast data transmission speed, and the fabrication process of the control wafer is compatible with chip back-end processes, resulting in high product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a structural diagram of the first embodiment of the memory chip provided by the present application;

[0030] Figure 2a is a structural diagram of a second embodiment of the memory chip provided by this application;

[0031] Figure 2b is a schematic structural diagram of a third embodiment of the memory chip provided by the present application;

[0032] Figure 2c is a schematic structural diagram of a fourth embodiment of a memory chip provided by the present application;

[0033] Figure 3 is an equivalent circuit diagram of the control unit and storage unit of the memory chip provided by this application;

[0034] Figure 4 is a schematic structural diagram of a fifth embodiment of the memory chip provided by the present application;

[0035] Figure 5 is a schematic structural diagram of a sixth embodiment of the memory chip provided by the present application;

[0036] Figure 6 is a schematic structural diagram of a seventh embodiment of the memory chip provided by the present application;

[0037] Figure 7 is a schematic structural diagram of an eighth embodiment of the memory chip provided by the present application;

[0038] Figure 8 is a schematic structural diagram of a ninth embodiment of the memory chip provided by the present application;

[0039] Figure 9 is a schematic structural diagram of a tenth embodiment of a memory chip provided by the present application;

[0040] Figure 10 is a structural diagram of the eleventh embodiment of the memory chip provided by the present application;

[0041] Figure 11 is a schematic structural diagram of a twelfth embodiment of the memory chip provided by the present application;

[0042] Figure 12a for Figure 7A cross-sectional view of an embodiment of a memory chip is shown;

[0043] Figure 12b for Figure 12a A top view of an embodiment of a memory chip is shown;

[0044] Figure 13a for Figure 7 A cross-sectional view of another embodiment of a memory chip is shown;

[0045] Figure 13b for Figure 13a A top view of an embodiment of a memory chip is shown;

[0046] Figure 14 This is a flow chart of an embodiment of a method for manufacturing a memory chip of the present application. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0048] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0049] The term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship. Furthermore, "many" in this document means two or more than two.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0051] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0052] The traditional von Neumann architecture separates memory and computing units. The relatively slow data transfer speed between the memory and computing units has become a bottleneck restricting overall computer performance. Frequent data transfer between the memory and computing units consumes a significant amount of energy.

[0053] Three-dimensional heterogeneous integration can overcome the shortcomings of the von Neumann architecture. Specifically, by vertically stacking multiple layers of devices, this architecture can integrate more functional modules within the same chip area, contributing to system miniaturization and multifunctionality, while increasing integration density. This shortens the signal transmission distance between different functional modules, reduces signal latency, and improves data transmission speed and overall system efficiency. Furthermore, tight integration between wafers helps reduce signal interference and improves system stability and reliability. The shortened signal transmission distance reduces energy loss during signal transmission, thereby helping to reduce overall chip power consumption.

[0054] In view of this, the present application provides a memory chip, which includes: a memory wafer and a control wafer, the memory wafer and the control wafer are stacked and bonded via a three-dimensional heterogeneous integrated structure. The memory wafer includes a first substrate and a plurality of memory cells, the plurality of memory cells are arranged on the first substrate, and the control wafer includes a second substrate and a plurality of control units, the plurality of control units are arranged on the second substrate. The first substrate and the second substrate are, for example, silicon substrates. The control unit is connected to the memory cells and is used to control the memory cells to perform read and write operations. In one embodiment, the number of control units corresponds to the number of memory cells, and the control units are connected to the memory cells in a one-to-one correspondence. The memory wafer includes a magnetoresistive random access memory; the control wafer includes at least one of a carbon nanotube transistor and a transistor based on a two-dimensional material. It should be noted that a carbon nanotube transistor refers to a transistor using a carbon nanotube material as a channel material, and a transistor based on a two-dimensional material refers to a transistor using a two-dimensional material as a channel material, and the two-dimensional material is, for example, at least one of molybdenum disulfide (MoS2) and tungsten diselenide (WSe2). The magnetoresistive random access memory (MRAM) may include, for example, at least one of a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) and a spin-transfer torque magnetoresistive random access memory (STT-MRAM). This application uses the SOT-MRAM as the MRAM and the carbon nanotube transistor as the control wafer for illustration.

[0055] This application utilizes three-dimensional heterogeneous integration technology to perform three-dimensional heterogeneous integration on a storage wafer including a magnetoresistive random access memory and a control wafer including at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials to obtain a storage chip. The storage chip has the advantages of low latency, low power consumption, large bandwidth, and high reliability.

[0056] In order to enable those skilled in the art to better understand the technical solution of the present invention, a memory chip provided by the present invention is described in further detail below with reference to the accompanying drawings and specific implementation methods.

[0057] See Figure 1 , Figure 1This is a structural diagram of the first embodiment of the memory chip of the present application, which specifically includes a memory wafer 10 and a control wafer 20 .

[0058] Specifically, the memory wafer 10 and the control wafer 20 are both independent wafer layers, each including a substrate, which is a basic material used to support and construct various semiconductor structures. Substrates generally include silicon substrates, silicon carbide substrates, sapphire substrates, and gallium arsenide substrates. In the memory chip of the present application, the substrate is a silicon substrate.

[0059] Specifically, the memory wafer 10 and the control wafer 20 are stacked and bonded together via a three-dimensional heterogeneous integrated structure. The three-dimensional heterogeneous integrated structure may include, for example, through-silicon vias (TSVs) and hybrid bonding. TSVs create vertical conductive channels between wafer or chip layers to enable high-density signal transmission. Hybrid bonding connects metal to metal, or metal to dielectric layers.

[0060] Furthermore, the storage wafer 10 includes a first substrate 101 and a plurality of storage cells 11, and the plurality of storage cells 11 are arranged in an array. The storage cell 11 is a magnetic tunnel junction (SOT-MTJ, also known as a spin-orbit torque magnetic tunnel junction), which is composed of two magnetic layers and a tunneling layer in the middle. One of the magnetic layers is a fixed magnetic axis layer (also called a reference layer), and its magnetization direction is fixed; the other layer is a free magnetic axis layer (also called a storage layer), and its magnetization direction can be changed under the action of an external magnetic field or spin transfer torque or spin-orbit torque to store different data. When the magnetization directions of the free magnetic axis layer and the fixed magnetic axis layer are parallel, the SOT-MTJ is in a low resistance state, representing a logic "1"; when they are anti-parallel, it is in a high resistance state, representing a logic "0".

[0061] It can be understood that the memory wafer 10 also includes peripheral circuits, such as word lines, bit lines, data lines, and programming lines. The word line is used to select the row where the memory cell is located. When a word line is activated, all memory cells on the row are selected for read and write operations. The bit line is connected to the free magnetic axis layer of the memory cell and is used to transmit data. During a read operation, the resistance state of the memory cell is detected by the bit line to determine the stored data; during a write operation, the bit line is used to provide a write current. The data line is connected to the fixed magnetic axis layer of the memory cell and cooperates with the bit line to complete the reading and writing of data. For example, during writing, the data line and the bit line work together to cause current to flow through the MTJ, generating a magnetic field to change the magnetization direction of the free magnetic axis layer. The programming line is used to provide a programming current. When the switching device is turned on, the programming current flows through the data line, and the generated magnetic field changes the magnetic axis direction of the free magnetic axis layer, thereby achieving data writing.

[0062] The transistors in the traditional control wafer 20 are generally silicon-based transistors, which face dual challenges in practical applications: on the one hand, the Si-Si chemical bond binding energy is low (327kJ / mol), which easily causes structural failure under strong radiation environment; on the other hand, its manufacturing process requires high-temperature process, resulting in poor compatibility with three-dimensional heterogeneous integration process. In contrast, new semiconductor devices represented by carbon nanotubes and two-dimensional materials have shown significant advantages. This type of material not only has stronger chemical bond binding energy (such as C-C bond up to 607kJ / mol), but its nanometer-scale thickness more effectively shortens the action path of high-energy particles and significantly improves radiation tolerance. In terms of manufacturing process, carbon nanotube transistors can be processed at low temperature through solution deposition, which is highly compatible with chip back-end processes. At the same time, its high on-state current density characteristics are particularly suitable for driving transistor scenarios. Two-dimensional material transistors have similar advantages. Therefore, the present application sets the control unit 21 to include at least one of carbon nanotube transistors and transistors based on two-dimensional materials, which not only breaks through the performance limitations of traditional silicon-based devices, but also solves the technical bottleneck of complex integration processes.

[0063] In addition, the erasure and writing endurance of the magnetoresistive random access memory is infinite. The present application will three-dimensionally heterogeneously integrate a control wafer 20 including at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials and a storage wafer 10 including a magnetoresistive random access memory to obtain a new type of memory chip. The memory chip has fast data transmission, low power consumption, and infinite erasure and writing endurance, and can be applied to a variety of usage scenarios, such as AI model training.

[0064] The control wafer 20 includes a second substrate 201 and a plurality of control units 21, and the plurality of control units 21 are arranged on the second substrate 201. The control unit 21 is connected to the storage unit 11 and controls the storage unit 11 to perform read and write operations. The control unit 21 includes at least one of a carbon nanotube transistor and a transistor based on a two-dimensional material. Specifically, this embodiment is described by taking the storage wafer 10 including SOT-MRAM and the control unit 21 including a carbon nanotube transistor as an example, and combining Figure 3Each control unit 21 includes a read control unit for controlling data reading and a write control unit for controlling data writing. The read control unit is a carbon nanotube transistor and / or the write control unit is a carbon nanotube transistor. In one specific embodiment, the read control unit includes a first carbon nanotube transistor Read Tx, and the write control unit includes a second carbon nanotube transistor Write Tx. The first carbon nanotube transistor Read Tx has a control terminal connected to a word line WL, a first channel terminal of the first carbon nanotube transistor Read Tx is connected to a bit line BL, and a second channel terminal of the first carbon nanotube transistor Read Tx is connected to a corresponding memory cell 11. The control terminal of the second carbon nanotube transistor Write Tx is connected to a word line WL, a first channel terminal of the second carbon nanotube transistor Write Tx is connected to a bit line BL, and a second channel terminal of the second carbon nanotube transistor Write Tx is connected to a corresponding memory cell 11. Specifically, the first carbon nanotube transistor Read Tx and the second carbon nanotube transistor Write Tx are used to control the gating and read and write operations of the memory cells. For example, during the reading and writing process, a specific memory cell is selected by controlling the on and off of the transistor, and current is passed through the MTJ to read or write data.

[0065] It can be understood that the second carbon nanotube transistor Write Tx is used to control the storage unit 11 to write data, and the first carbon nanotube transistor Read Tx is used to control the storage unit 11 to read data. In one embodiment, only the transistor that controls data writing can be set to a carbon nanotube transistor, that is, the transistor that controls data writing in the control unit is the second carbon nanotube transistor. In another embodiment, only the transistor that controls data reading can be set to a carbon nanotube transistor, that is, the transistor that controls data reading in the control unit is the first carbon nanotube transistor. Of course, in order to simplify the process, the transistor that controls data writing and the transistor that controls data reading can both be set to carbon nanotube transistors, that is, the transistor that controls data writing in the control unit is the second carbon nanotube transistor, and the transistor that controls data reading in the control unit is the first carbon nanotube transistor.

[0066] In another embodiment of the present application, a memory wafer including a spin-transfer torque magnetoresistive random access memory (STT-MRAM) is used as an example for illustration. The STT-MRAM is a two-terminal device that can be controlled by only one transistor. In this embodiment, each control unit includes a read / write control unit for controlling data reading and writing, and the read / write control unit is a carbon nanotube transistor. The transistor is configured as a carbon nanotube transistor, and read / write control is performed through the carbon nanotube transistor.

[0067] For further information, see Figure 1 The memory chip of the present application also includes a dielectric layer 30, which is arranged between the memory wafer 10 and the control wafer 20. The dielectric layer 30 is used to isolate the memory wafer 10 from the control wafer 20 to prevent short circuits, ensure that the current flows along the designed path, and avoid electrical interference between different components.

[0068] The memory wafer 10 and the control wafer 20 can be bonded face to face. When bonding face to face, the first substrate 101 of the memory wafer 10 and the second substrate 201 of the control wafer 20 are located on the upper and lower surfaces of the memory chip. Figure 1 As shown, the storage wafer 10 also includes a first bonding layer 102 arranged on the side of the multiple storage units 11 away from the first substrate 101; the control wafer 20 also includes a second bonding layer 202 arranged on the side of the multiple control units 21 away from the second substrate 201; wherein, the first bonding layer 102 and the second bonding layer 202 are bonded to form a three-dimensional heterogeneous integrated structure, bonding the storage wafer 10 and the control wafer 20.

[0069] In another embodiment, the memory wafer 10 and the control wafer 20 can also be bonded face to back, for example, the side of the memory wafer 10 away from the first substrate 101 is arranged opposite to the second substrate 201 of the control wafer 20, with a dielectric layer 30 in between. Figure 2a The storage wafer 10 also includes a first bonding layer 102 arranged on the side of the multiple storage units 11 away from the first substrate 101; the control wafer 20 also includes a second bonding layer 202 arranged on the side of the second substrate 201 away from the multiple control units 21; wherein the first bonding layer 102 and the second bonding layer 202 are bonded to form a three-dimensional heterogeneous integrated structure, bonding the storage wafer 10 and the control wafer 20.

[0070] In another embodiment, the memory wafer 10 and the control wafer 20 can also be bonded face to back, for example, the first substrate 101 of the memory wafer 10 and the side of the control wafer 20 away from the second substrate 201 are arranged opposite to each other, with a dielectric layer 30 in between. Figure 2b The storage wafer 10 also includes a first bonding layer 102 arranged on the side of the first substrate 101 away from the multiple storage units 11; the control wafer 20 also includes a second bonding layer 202 arranged on the side of the multiple control units 21 away from the second substrate 201; the first bonding layer 102 and the second bonding layer 202 are bonded to form a three-dimensional heterogeneous integrated structure, bonding the storage wafer 10 and the control wafer 20.

[0071] In another embodiment, the memory wafer 10 and the control wafer 20 can also be bonded back to back. When bonding back to back, the first substrate 101 of the memory wafer 10 and the second substrate 201 of the control wafer 20 are arranged opposite to each other with a dielectric layer 30 in between. Figure 2cThe storage wafer 10 also includes a first bonding layer 102 arranged on the side of the first substrate 101 away from the multiple storage units 11; the control wafer 20 also includes a second bonding layer 202 arranged on the side of the second substrate 201 away from the multiple control units 21; wherein the first bonding layer 102 and the second bonding layer 202 are bonded to form a three-dimensional heterogeneous integrated structure, bonding the storage wafer 10 and the control wafer 20.

[0072] It should be noted that when the first substrate 101 / the second substrate 201 is used as the bonding surface, the first substrate 101 / the second substrate 201 needs to be thinned.

[0073] The dielectric layer 30 of the present application fills the gaps in the three-dimensional heterogeneous integrated structure and isolates the three-dimensional heterogeneous integrated structure. The control unit 21 is electrically connected to the storage unit 11 through the three-dimensional heterogeneous integrated structure in the dielectric layer 30 for signal transmission, thereby realizing chip integration in three-dimensional space and effectively improving integration density and system performance.

[0074] In this embodiment, the storage wafer 10 and the control wafer 20 are both single-layer structures, and the storage wafer 10 is arranged on one side of the control wafer 20. The structure of the entire storage chip includes the storage wafer 10, the dielectric layer 30 and the control wafer 20 from bottom to top.

[0075] In another embodiment of the present application, in order to expand the storage space, the number of storage wafers 10 is at least two. At least two storage wafers 10 are stacked and bonded, and are arranged on the same side of the control wafer 20, such as Figure 4 As shown, Figure 4 The embodiment shown is similar to the above Figure 1 Compared with the embodiment shown, the difference is that: in this embodiment, the storage wafer 10 is 2-layered, and in other embodiments, the storage wafer 10 can also be 3-layered, 4-layered, and so on, which is not specifically limited. It can be understood that in this embodiment, a dielectric layer 30 is provided between the storage wafer 10 and the storage wafer 10, and between the storage wafer 10 and the control wafer 20. In order to achieve interconnection, the storage wafer 10 in the middle includes a first bonding layer 102 provided on the side of the plurality of storage units 11 away from the first substrate 101, and a third bonding layer 103 provided on the side of the first substrate 101 away from the plurality of storage units 11, that is, the first bonding layer 102 and the third bonding layer 103 are provided on both surfaces of the storage wafer 10, respectively. The storage wafer 10 away from the control wafer 20 has the first bonding layer 102 provided on only one surface, and the side where the first bonding layer 102 is provided can be the side of the storage unit 11 away from the first substrate 101, such as Figure 4As shown, it can also be the side of the first substrate 101 away from the plurality of storage units 11, and there is no specific limitation. The control wafer 20 also has only one surface on which the second bonding layer 202 is provided. The side on which the second bonding layer 202 is provided can be the side of the control unit 21 away from the second substrate 201, such as Figure 4 As shown, it can also be the side of the second substrate 201 away from the control units 21, and the specific details are not limited. In this embodiment, the third bonding layer 103 of the storage wafer 10 in the middle position and the first bonding layer 102 of the storage wafer 10 away from the control wafer 20 are bonded to form a three-dimensional heterogeneous integrated structure, and the first bonding layer 102 of the storage wafer 10 in the middle position and the second bonding layer 202 of the control wafer 20 are bonded to form a three-dimensional heterogeneous integrated structure.

[0076] It should be noted that in the present application, the same control wafer 20 controls the read and write operations of two layers of storage wafers 10. Therefore, reasonable wiring is required to interconnect the control unit 21 in the control wafer 20 with the storage unit 11 in the closest storage wafer 10. It is also necessary to interconnect the control unit 21 in the control wafer 20 with the storage unit 11 in the storage wafer 10 that is farther away across layers. In this way, when reading and writing, a specific storage unit 11 can be selected for access based on the read and write address. Alternatively, a gating structure can be set on the path interconnecting the control unit 21 and the storage unit 11, and the gating structure can be selectively turned on based on the read and write address, so as to select a specific storage unit 11 for access based on the read and write address. The gating structure can be, for example, a switch element or a multiplexer, etc.

[0077] Furthermore, part of the storage wafers 10 in this embodiment can be used as redundant storage. When the main storage is damaged, the redundant storage replaces the main storage.

[0078] In another embodiment, part of the storage wafer 10 is disposed on one side of the control wafer 20, and the remaining part of the storage wafer 10 is disposed on the other side of the control wafer 20. Figure 5 , Figure 5 Also take the 2-layer storage wafer 10 as an example for explanation. Figure 5 The embodiment shown is similar to the above Figure 4 Compared with the embodiment shown in FIG, the difference is that in this embodiment, the control wafer 20 is set between the two storage wafers 10. In the layout of this embodiment, the control unit 21 in the control wafer 20 and the storage unit 11 do not need to be connected across layers. Figure 4 In the embodiment shown, the interconnection distance between the control wafer 20 and the storage wafer 10 is closer, the data access speed is faster, and the power consumption is lower.

[0079] In this embodiment, the control wafer 20 further includes a second bonding layer 202 disposed on a side of the plurality of control units 21 away from the second substrate 201, and a fourth bonding layer 203 disposed on a side of the second substrate 201 away from the plurality of control units 21. The control wafer 20 is connected to the storage wafers 10 on both sides via the second bonding layer 202 and the fourth bonding layer 203. In one embodiment, the storage wafer 10 further includes a first bonding layer 102 disposed on a side of the plurality of storage units 11 away from the first substrate 101; the first bonding layer 102 of one storage wafer 10 is bonded to the second bonding layer 202, and the first bonding layer 102 of another storage wafer 10 is bonded to the fourth bonding layer 203. It is understandable that in this embodiment, the first bonding layer 102 of the storage wafer 10 can also be disposed on a side of the first substrate 101 away from the storage units 11. Furthermore, in this embodiment, the first bonding layer 102 of one storage wafer 10 can be set on the side of the first substrate 101 away from the storage unit 11, and the first bonding layer 102 of another storage wafer 10 can be set on the side of the storage unit 11 away from the first substrate 101, without specific limitation.

[0080] Figure 1 、 Figure 4 and Figure 5 In the embodiment shown, n storage wafers 10 and one control wafer 20 are regarded as a storage component. A plurality of such storage components can be stacked and interconnected in a first direction, which will not be described in detail. The first direction is perpendicular to the wafer surface.

[0081] In the above embodiment, in order for the control unit 21 to drive the memory cell 11, the driving current density of the transistors of the control unit 21 (e.g., the first carbon nanotube transistor and the second carbon nanotube transistor) must meet a certain standard. If the driving current density is insufficient, then the reading and writing of the memory cell 11 will not be sufficient.

[0082] Based on this, the present application further provides a control unit 21 including at least two first carbon nanotube transistors and / or at least two second carbon nanotube transistors, wherein the at least two first carbon nanotube transistors are connected in parallel; and the at least two second carbon nanotube transistors are connected in parallel. Connecting the at least two carbon nanotube transistors in parallel increases the driving current density.

[0083] In another embodiment of the present application, in order to reduce wiring complexity, the number of control wafers 20 is further set to at least two. Figure 6 At least two control wafers 20 are stacked and bonded, and are arranged on the same side of the memory wafer 10. Figure 1Compared with the embodiment shown, the difference is that in this embodiment, there are two control wafers 20, and in other embodiments, the control wafer 20 can be 3-layer, 4-layer, etc., which is not specifically limited. Adjacent control wafers 20 are bonded and connected through a three-dimensional heterogeneous integrated structure. It can be understood that in this embodiment, a dielectric layer 30 is provided between the control wafer 20 and the control wafer 20, and between the control wafer 10 and the control wafer 20. In order to achieve interconnection, the control wafer 20 located in the middle includes a second bonding layer 202 provided on the side of the control units 21 away from the second substrate 201, and a fourth bonding layer 203 provided on the side of the second substrate 201 away from the control units 21, that is, the two surfaces of the control wafer 20 are respectively provided with the second bonding layer 202 and the fourth bonding layer 203. The control wafer 10 away from the storage wafer 10 is provided with the second bonding layer 202 on only one surface, and the side where the second bonding layer 202 is provided can be the side of the control unit 21 away from the second substrate 201, such as Figure 6 As shown, it can also be the side of the second substrate 201 away from the plurality of control units 21, and there is no specific limitation. The storage wafer 10 also has only one surface on which the first bonding layer 102 is provided, and the side on which the first bonding layer 102 is provided can be the side of the storage unit 11 away from the first substrate 101, such as Figure 6 As shown, it may also be the side of the first substrate 101 away from the plurality of memory cells 11, and the specific embodiment is not limited thereto. In this embodiment, the second bonding layer 202 of the control wafer 20 at the middle position is bonded to the first bonding layer 102 of the memory wafer 10 to form a three-dimensional heterogeneous integrated structure, and the fourth bonding layer 203 of the control wafer 20 at the middle position is bonded to the second bonding layer 202 of another control wafer 20 to form a three-dimensional heterogeneous integrated structure.

[0084] It should be noted that, in order to provide a higher driving current density, the present application sets the control units 21 on different control wafers 20 in parallel. Specifically, it is assumed that the at least two layers of control wafers 20 in this embodiment include a first control wafer and a second control wafer. The second carbon nanotube transistor on the first control wafer is connected in parallel with the second carbon nanotube transistor on the second control wafer; and / or the first carbon nanotube transistor on the first control wafer is connected in parallel with the first carbon nanotube transistor on the second control wafer. Furthermore, in order to rationally utilize the wiring space, the two second carbon nanotube transistors corresponding to the positions in the direction perpendicular to the wafer can be connected in parallel, and the two first carbon nanotube transistors corresponding to the positions in the direction perpendicular to the wafer can be connected in parallel. The two second carbon nanotube transistors in parallel jointly drive a storage unit to perform a write operation, and the two first carbon nanotube transistors in parallel jointly drive a storage unit to perform a read operation.

[0085] In another embodiment of the present application, part of the control wafer 20 is arranged on one side of the storage wafer 10, and the rest of the control wafer 20 is arranged on the other side of the storage wafer 10. Also, two layers of control wafers 20 are used as an example for explanation. In this embodiment, one layer of control wafer 20 is located on the upper side of the storage wafer 10, and the other layer of control wafer 20 is arranged on the lower side of the storage wafer 10. For details, see Figure 7 Thus, the overall structure of the memory chip includes, from bottom to top, the control wafer 20 , the dielectric layer 30 , the memory wafer 10 , the dielectric layer 30 , and the control wafer 20 .

[0086] In this embodiment, the storage wafer 20 further includes a first bonding layer 102 disposed on a side of the plurality of storage units 11 away from the first substrate 201, and a third bonding layer 103 disposed on a side of the first substrate 101 away from the plurality of storage units 11. The storage wafer 10 is connected to the control wafers 20 on both sides via the first bonding layer 102 and the third bonding layer 103. In one embodiment, the control wafer 20 further includes a second bonding layer 202 disposed on a side of the plurality of control units 11 away from the second substrate 201; the second bonding layer 202 of one control wafer 20 is bonded to the first bonding layer 102, and the second bonding layer 202 of the other control wafer 20 is bonded to the third bonding layer 103. It is understandable that in this embodiment, the second bonding layer 202 of the control wafer 20 can also be disposed on a side of the second substrate 201 away from the control unit 21. Furthermore, in this embodiment, the second bonding layer 202 of one control wafer 20 can be set on the side of the second substrate 201 away from the control unit 21, and the second bonding layer 202 of another control wafer 20 can be set on the side of the control unit 21 away from the second substrate 201, without specific limitation.

[0087] In the above embodiment, one storage wafer 10 and n control wafers 20 are regarded as one storage component. In the same wafer, multiple storage components can be stacked and interconnected in the first direction, and the details are not repeated here.

[0088] Furthermore, taking the above embodiment as an example, n storage wafers 10 and m control wafers 20 form a storage component 50, then the storage chip includes multiple storage components 50, and the multiple storage components 50 are arranged along a direction perpendicular to the wafer (i.e., a first direction), wherein n and m are positive integers. In one embodiment, multiple storage components 50 are stacked and arranged along the first direction, such as Figure 9 As shown, this can not only expand the storage space of the memory chip, but also reduce the area of ​​the memory chip. In another embodiment, multiple storage components 50 can also be set on a substrate 40 and laid flat on the substrate 40, such as Figure 8 As shown, this can not only expand the storage space of the memory chip, but also reduce the thickness of the memory chip.

[0089] Furthermore, in one embodiment of the present application, there are multiple control wafers, with the control units 21 in some control wafers 20 acting as slave control units, and the control units 21 in the remaining control wafers 20 acting as master control units. The master and slave control units are each connected to the same storage unit 11, with the slave control units performing read and write operations on the storage unit 11 on behalf of the master control unit. For example, the control wafer 20 may be configured as three layers, including a first control wafer, a second control wafer, and a third control wafer. The control units 21 in corresponding positions in the three layers of control wafers 20 are connected in parallel, specifically: the second carbon nanotube transistor on the first control wafer, the second carbon nanotube transistor on the second control wafer, and the second carbon nanotube transistor on the third control wafer are connected in parallel; and / or the first carbon nanotube transistor on the first control wafer, the first carbon nanotube transistor on the second control wafer, and the first carbon nanotube transistor on the third control wafer are connected in parallel. In this case, at least one of the three parallel transistors acts as a slave transistor, replacing the master transistor when the master transistor is unavailable. It is understood that a switch element can be provided on the path between the slave transistor and the master transistor. When the master transistor is available, the slave transistor is disconnected from the control path (the path for controlling the reading and writing of the storage unit) through the switch element. When the master transistor is unavailable, the slave transistor is electrically connected to the control path (the path for controlling the reading and writing of the storage unit) through the switch element. Of course, the control wafer 20 provided with the slave control unit can also be provided in multiple layers, depending on specific needs and is not limited to this.

[0090] Furthermore, the memory chip of the present application expands the space and control of the memory chip in the longitudinal direction (first direction), so that the memory chip has a multi-layer structure. Under this structure, the memory chip will generate a lot of heat, so the heat dissipation of the memory chip is a problem that needs to be solved. Based on this, see Figure 10 , the memory chip of the present application further provides a heat dissipation layer 32 between the control wafer 20 and the memory wafer 10. Specifically, the heat dissipation layer 32 includes a carbon nanotube material. In order to prevent the heat dissipation layer 32 from affecting the electrical effect between the control wafer 20 and the memory wafer 10, the heat dissipation layer 32 is wrapped with a dielectric layer 30 to isolate the heat dissipation layer 32 from the control wafer 20 and the memory wafer 10. Furthermore, the dielectric layer 30 also needs to separate the three-dimensional heterogeneous bonding structure from the heat dissipation layer 32. In one embodiment, the carbon nanotubes can form a mesh heat dissipation layer 32, and the three-dimensional heterogeneous integrated structure is located in the grid of the mesh heat dissipation layer 32. In one embodiment, the carbon nanotubes can be directly laid in strips to form the heat dissipation layer 32.

[0091] It is understandable that if the heat dissipation layer 32 is made of other insulating materials, the heat dissipation layer 32 can also be in contact with the control wafer 20 or the memory wafer 10 as long as it does not affect the electrical effect between the control wafer 20 and the memory wafer 10.

[0092] In the memory chip of this embodiment, the heat dissipation layer 32 is provided between the memory wafer 10 and the control wafer 20 for exemplary purposes only. If multiple layers of memory wafers 10 are present, a heat dissipation layer 32 may also be provided between adjacent memory wafers 10. Similarly, if multiple layers of control wafers 20 are present, a heat dissipation layer 32 may also be provided between adjacent control wafers 20.

[0093] Furthermore, since the control unit 21 in the control wafer 20 and the storage unit 11 in the storage wafer 10 are interconnected one-to-one through a three-dimensional heterogeneous integrated structure, the density is relatively high and bonding alignment is difficult during three-dimensional bonding. Figure 7 The memory chip shown is Figure 7 The memory chip shown in the figure is used as an example to illustrate. Figure 7 In the illustrated embodiment, multiple control wafers 20 jointly control one storage wafer 10. This allows for increased spacing between control units 21 within the control wafers 20 and reduced density of the control units 21. For example, if a storage wafer 10 contains 100 storage cells 11, then one control wafer 20 may be provided with 50 control units 21, each controlling 50 storage cells 11 within the storage wafer 10. Another control wafer 20 may be provided with 50 control units 21, each controlling another 50 storage cells 11 within the storage wafer 10. In this manner, control units 21 located in odd columns of one control wafer 20 can be connected to storage cells 11 located in odd columns of the storage wafer 10, while control units 21 located in even columns of another control wafer 20 can be connected to storage cells 11 located in even columns of the storage wafer 10. This allows for a larger bonding area between two adjacent bonded wafers, reducing the difficulty of bonding alignment.

[0094] In addition, since the control unit 21 is a carbon nanotube transistor, in this transistor, the carbon nanotube is used as a channel. Carbon nanotubes have a good heat dissipation effect. When multiple wafers are stacked in three dimensions, the chip will generate a lot of heat, so the heat dissipation problem needs to be solved. In one embodiment, when preparing the control unit 21, a heat dissipation layer 32 can be prepared in the gap of the control unit 21. Alternatively, when preparing the control unit 21, 100 control units can still be prepared in the control wafer 20, but other control units 21 that are not used to control the storage unit 11 can be used as heat dissipation layers. When these control units 21 serve as heat dissipation layers, they are not powered and only conduct heat, and the heat dissipation layer does not interfere with the control unit 21 and the storage unit 11. For details, please refer to Figure 12a In the preparation of the memory chip, the channel of the carbon nanotube transistor of the control unit 21 is prepared using a normal process, and carbon nanotubes are placed at predetermined positions. When further preparing the source S and drain D, only the carbon nanotubes corresponding to the odd-numbered columns (or even-numbered columns) are prepared, while the carbon nanotubes in the even-numbered columns (or odd-numbered columns) are only used as heat dissipation layers and are not prepared as electrodes. Figure 12a As shown, the control units 21 in the even-numbered columns of the control wafer 20 on the upper layer are connected to the storage units 11 in the even-numbered columns of the memory wafer 10 via signal holes 35 and the three-dimensional heterogeneous integrated structure 31. Meanwhile, the control units 21 in the odd-numbered columns of the control wafer 20 on the lower layer are connected to the storage units 11 in the even-numbered columns of the memory wafer 10 via signal holes 35 and the three-dimensional heterogeneous integrated structure 31. The carbon nanotubes in the odd-numbered columns of the control wafer 20 on the upper layer serve as a heat sink, while the carbon nanotubes in the even-numbered columns of the control wafer 20 on the lower layer serve as a heat sink.

[0095] Further, such as Figure 12b As shown, the bit line BL (or other signal transmission lines extending in the same direction as the bit line) and the carbon nanotubes (channel layer of the carbon nanotube transistor) are in the same metal layer. In order to avoid the bit line BL, the carbon nanotubes in the same column as the heat dissipation layer 32 can be set to be continuous along the extension direction of the bit line BL, but disconnected along the word line WL direction.

[0096] In another embodiment, Figure 13a As shown, this embodiment is different from the above Figure 12a The difference between the embodiment shown is that in this embodiment, the word lines WL and the bit lines BL are not in the same metal layer as the carbon nanotubes (channel layer of the carbon nanotube transistor). In this case, the carbon nanotubes used as the heat dissipation layer 32 can be arranged in a grid shape, that is, the carbon nanotubes do not need to avoid the bit lines BL and can be arranged to be continuous along the extending direction of the bit lines BL and also continuous along the word lines WL. Figure 13b It should be noted that, in this embodiment, the gate G and the word line WL can be provided in the same layer.

[0097] If the word lines WL (or other signal transmission lines extending in the same direction as the word lines) and the carbon nanotubes (channel layer of carbon nanotube transistors) are in the same metal layer, then the carbon nanotubes in the same column of the heat dissipation layer 32 can be discontinuous.

[0098] Further, if Figure 5 In the memory chip shown, one control wafer 20 controls multiple memory wafers 10. At this time, the density of the memory cells 11 of the memory wafer 10 can be reduced, and a heat dissipation layer can be further provided in the gaps between the memory cells 11. The setting of the heat dissipation layer is as described above and will not be described in detail.

[0099] Furthermore, the memory chip of the present application further includes a sensor component 60, which can be disposed in the memory wafer 10 or the control wafer 20, as long as the process is compatible. In another embodiment, see Figure 11 The sensing component 60 can be independently set in a sensing wafer, and the sensing wafer is stacked with the storage wafer 10 and the control wafer 20 and bonded together through a three-dimensional heterogeneous integrated structure. The specific connection method is the same as that in the above embodiment and will not be repeated here.

[0100] In one embodiment, the sensor component 60 may be disposed on a side of the control wafer 20 away from the memory wafer 10. In other embodiments, the sensor component 60 may also be disposed on a side of the memory wafer 10 away from the control wafer 20, which is not specifically limited.

[0101] It should be noted that the sensor component 60 is, for example, a CNTFET biosensor device, a two-dimensional material optical signal sensor device, etc.

[0102] The memory chip of this embodiment can realize sensing, storage, and computing in one, and can be applied in fields such as artificial intelligence and the Internet of Things.

[0103] The memory chip of the present application performs three-dimensional heterogeneous integration of a control wafer and a memory wafer, and the memory wafer is a magnetoresistive random access memory, and the control wafer is at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials. It has the characteristics of low power consumption and fast data transmission.

[0104] See also Figure 14 , Figure 14 This is a flow chart of an embodiment of a method for preparing a memory chip of the present application, which specifically includes:

[0105] Step S111: providing a storage wafer and a control wafer.

[0106] Among them, the storage wafer includes a first substrate and several storage units, and the control wafer includes a second substrate and several control units; the storage unit includes a magnetoresistive random access memory; the control unit includes at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials.

[0107] Step S112: stacking the memory wafer and the control wafer, and forming a three-dimensional heterogeneous integrated structure to bond the memory wafer and the control wafer.

[0108] The storage wafer includes a plurality of storage units, and the control wafer includes a plurality of control units, and the control units are used to control the storage units to perform read and write operations.

[0109] Furthermore, after the control wafer and the storage wafer are prepared and bonded, cutting is further performed on the prepared wafer to obtain multiple crystal grains, and the obtained crystal grains are packaged to obtain multiple chips.

[0110] The preparation method of the memory chip of the present application performs three-dimensional heterogeneous integration of the control wafer and the memory wafer, and the memory wafer is a magnetoresistive random access memory, and the control wafer is at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials, which has the characteristics of low power consumption and fast data transmission.

[0111] The above are merely embodiments of the present invention and are not intended to limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present invention.

Claims

1. A memory chip, characterized in that: include: A storage wafer and a control wafer, wherein the storage wafer and the control wafer are stacked and bonded via a three-dimensional heterogeneous integrated structure; The storage wafer includes a first substrate and a plurality of storage units, and the control wafer includes a second substrate and a plurality of control units, wherein the control units are connected to the storage units and control the storage units to perform read and write operations; The storage wafer includes a magnetoresistive random access memory; the control wafer includes at least one of a carbon nanotube transistor and a transistor based on two-dimensional materials.

2. The memory chip according to claim 1, wherein: The memory wafer further comprises a first bonding layer provided on a side of the plurality of memory units away from the first substrate; the control wafer further comprises a second bonding layer provided on a side of the plurality of control units away from the second substrate; wherein the first bonding layer and the second bonding layer are bonded to form the three-dimensional heterogeneous integrated structure; or The memory wafer further comprises a first bonding layer provided on a side of the plurality of memory units away from the first substrate; the control wafer further comprises a second bonding layer provided on a side of the second substrate away from the plurality of control units; wherein the first bonding layer and the second bonding layer are bonded to form the three-dimensional heterogeneous integrated structure; or The storage wafer further comprises a first bonding layer provided on a side of the first substrate away from the plurality of storage units; the control wafer further comprises a second bonding layer provided on a side of the plurality of control units away from the second substrate; wherein the first bonding layer and the second bonding layer are bonded to form the three-dimensional heterogeneous integrated structure; or The storage wafer also includes a first bonding layer arranged on a side of the first substrate away from the plurality of storage units; the control wafer also includes a second bonding layer arranged on a side of the second substrate away from the plurality of control units; wherein the first bonding layer and the second bonding layer are bonded to form the three-dimensional heterogeneous integrated structure.

3. The memory chip according to claim 1, wherein: The memory wafer further includes a first bonding layer provided on a side of the plurality of memory cells away from the first substrate, and a third bonding layer provided on a side of the first substrate away from the plurality of memory cells; The control wafer also includes a second bonding layer arranged on the side of the control units away from the second substrate; the second bonding layer of one control wafer is bonded to the first bonding layer, and the second bonding layer of another control wafer is bonded to the third bonding layer.

4. The memory chip according to claim 1, wherein: The control wafer further includes a second bonding layer provided on a side of the plurality of control units away from the second substrate, and a fourth bonding layer provided on a side of the second substrate away from the plurality of control units; The storage wafer also includes a first bonding layer arranged on a side of the plurality of storage units away from the first substrate; the first bonding layer of one storage wafer is bonded to the second bonding layer, and the first bonding layer of another storage wafer is bonded to the fourth bonding layer.

5. The memory chip according to claim 1, wherein: At least two of the memory wafers are stacked and bonded, and are arranged on the same side of the control wafer; or At least two control wafers are stacked and bonded, and are arranged on the same side of the memory wafer.

6. The memory chip according to any one of claims 1 to 5, wherein: Each of the control units includes: a read control unit for controlling data reading and a write control unit for controlling data writing, the read control unit is a carbon nanotube transistor, and / or the write control unit is a carbon nanotube transistor; or Each of the control units includes a read / write control unit for controlling data reading and writing, and the read / write control unit is a carbon nanotube transistor.

7. The memory chip according to claim 1, wherein: There are multiple control wafers, the control units in some of the control wafers serve as slave control units, and the control units in the remaining control wafers serve as master control units; The master control unit and the slave control unit are respectively connected to the same storage unit, and the slave control unit is used to perform read and write operations on the storage unit instead of the master control unit.

8. The memory chip according to any one of claims 1 to 5, wherein: The memory chip further includes a heat dissipation layer disposed between the control wafer and the memory wafer; The heat dissipation layer includes carbon nanotubes.

9. The memory chip according to any one of claims 1 to 5, wherein: The storage chip also includes: a sensing component; the sensing component is arranged in the storage wafer or the control wafer; or, the sensing component is independently arranged in a sensing wafer, and the sensing wafer, the storage wafer and the control wafer are stacked and bonded to each other through a three-dimensional heterogeneous integrated structure.

10. A method for preparing a memory chip, characterized in that: include: A memory wafer and a control wafer are provided; the memory wafer includes a first substrate and a plurality of memory cells, and the control wafer includes a second substrate and a plurality of control cells; the memory cells include magnetoresistive random access memories; and the control cells include at least one of carbon nanotube transistors and transistors based on two-dimensional materials; The memory wafer and the control wafer are stacked and a three-dimensional heterogeneous integrated structure is provided to bond the memory wafer and the control wafer together; The control unit is connected to the storage unit and controls the storage unit to perform read and write operations.

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