Memory with test function and test method

Abstract

The invention discloses a memory with a test function and a test method, the memory comprises a plurality of columns of memory modules and a test circuit, the test circuit at least utilizes n + 1 columns of adjacent target memory modules, n is greater than or equal to 1, at least one row of first memory units and three rows of second memory units are multiplexed in each column of target memory modules, and a NOR gate is arranged in each column of target memory modules. Each NOR gate and the first storage unit and the second storage unit which are multiplexed in the target storage module in the same column form a local XOR module; when the test circuit is used in the test process, the first n columns of local XOR modules in the first direction are used as D triggers in a linear feedback shift register or a multi-input signature register when the test circuit is used for testing. And when the input end of the evaluation circuit in the memory is not provided with a trigger, a linear feedback shift register does not need to be added, so that the hardware overhead is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of SRAM in-memory computing circuit testing, and in particular to a memory with testing function and a testing method. Background Art

[0002] In order to effectively break the von Neumann bottleneck and improve the performance and energy efficiency of computing devices in data-intensive computing, the emerging computing paradigm based on the digital domain SRAM storage and computing architecture of static random access memory (SRAM) has been widely used due to its high memory access speed, mature manufacturing process and good compatibility with CMOS logic circuits. Figure 1 As shown, Figure 1 This is a block diagram of the digital domain SRAM storage and computation architecture. It consists primarily of three main components: a storage module, peripheral circuits, and an evaluation circuit. The evaluation circuit is a combinational logic and sequential logic circuit embedded within the storage module. It further processes the logical operation results output by the storage module to implement complex arithmetic operations. However, to obtain accurate calculation results, the evaluation circuit must be tested. Common testing methods for this circuit include those based on Design for Testability (DFT).

[0003] While design-for-testability (DFT) testing methods can test evaluation circuits, indirect testing methods require repeated test vector generation due to the significant differences in test vectors required for different evaluation circuits, reducing test efficiency. For evaluation circuits with flip-flops at their inputs, DFT testing methods require modifying the flip-flops into scan flip-flops to form a scan chain. Through the scan chain, test vectors generated externally using an ATPG (Automatic Test Pattern Generation) algorithm are directly applied to the original inputs of the evaluation circuit. This requires a long time to apply the test vectors, reducing test efficiency. Therefore, in some tests, flip-flops are configured as linear feedback shift registers (LFSRs). Compared to forming a scan chain, this method is faster, and the additional area overhead introduced by modifying the flip-flops into LFSRs is negligible. However, for evaluation circuits without flip-flops at their inputs, directly adding LFSRs introduces significant hardware overhead. Summary of the Invention

[0004] The main technical problem solved by the present invention is that for an evaluation circuit without a trigger at the input end, directly adding a linear feedback shift register will introduce a large hardware overhead.

[0005] According to the first aspect, an embodiment provides a memory having a test function, comprising:

[0006] A plurality of columns of memory modules, each column of the memory modules comprising at least one row of first memory cells, at least three rows of second memory cells, a first read bit line, a second read bit line, a first write bit line, and a second write bit line, wherein the first memory cell and the second memory cell are connected to the first read bit line, the second memory cell is further connected to the second read bit line, and at least two second memory cells are further connected to the first write bit line and the second write bit line, respectively;

[0007] A test circuit, wherein the test circuit utilizes at least n+1 columns of adjacent target memory modules, where n≥1, and wherein at least one row of first memory cells and three rows of second memory cells are reused in each column of the target memory modules. A NOR gate is provided in each column of the target memory modules, wherein one input of the NOR gate is connected to a first read bit line in the target memory modules in the same column, another input of the NOR gate is connected to a second read bit line in the target memory modules in the same column, and an output of the NOR gate is connected to the first memory cell in the target memory modules in the same column, so that each NOR gate and the reused first and second memory cells in the target memory modules in the same column form a local XOR module for performing an XOR operation.

[0008] In which, during the test process of the test circuit: the reused first storage unit is used to store the XOR operation result, the reused second storage unit is used to store data, and the first n columns of local XOR modules along the first direction are used as D flip-flops in a linear feedback shift register or a multi-input signature register when testing the test circuit, the local XOR module is used to calculate the highest bit response compression result of the multi-input signature register, and the local XOR module in the n+1th column along the first direction is used to temporarily store the highest bit data of the linear feedback shift register and the multi-input signature register.

[0009] In a further aspect of the present invention, the memory further comprises a sense amplifier having n+1 input terminals and an output terminal, each input terminal of the sense amplifier being connected to a first read bit line in a target memory module, the sense amplifier being configured to sense a voltage change on the connected first read bit line and output a sensed signal;

[0010] Sorting along the first direction starting from zero, all second storage cells in a row of local XOR modules located at odd bits share a read word line and a write word line, all second storage cells in a row of local XOR modules located at even bits share a read word line and a write word line, all first storage cells in local XOR modules located at odd bits share a read word line and a write word line, and all first storage cells in local XOR modules located at even bits share a read word line and a write word line;

[0011] The test circuit further includes:

[0012] a chain XOR circuit connected to the output terminals of the sense amplifiers corresponding to the first n columns of local XOR modules along the first direction, the chain XOR circuit being configured to receive the sensing signals output by the sense amplifiers and perform a multi-input XOR operation to output an XOR operation result;

[0013] A shift driving module, wherein one shift driving module is provided for each local XOR module. The shift driving modules corresponding to the first n columns of target storage modules along the first direction are connected to the output end of the sense amplifier corresponding to the local XOR module adjacent to the left. The shift driving module is also connected to the circuit to be tested. The shift driving module corresponding to the local XOR module in the (n+1)th column along the first direction is also connected to the chain XOR circuit. In addition, among any two adjacent local XOR modules, the shift driving module corresponding to the local XOR module on the right is connected to the local XOR module on the left.

[0014] Wherein, when the test circuit serves as the linear feedback shift register, the shift driving modules corresponding to the first n columns of local XOR modules along the first direction are used to access the immediate data and write it into the first n columns of local XOR modules along the first direction;

[0015] When the test circuit serves as a multi-input signature register, the shift drive module is used to receive the test response of the circuit to be tested and output it to the local XOR module. The shift drive modules in the last n columns along the first direction are used to access the immediate value and write it into the local XOR modules in the last n columns along the first direction. The shift drive module corresponding to the local XOR module in the (n+1)th column is also used to receive the XOR operation result.

[0016] According to a further configuration of the present invention, the first storage unit is a 11T NOR-cell unit, and / or the second storage unit is a 10T SRAM unit.

[0017] According to a further configuration of the present invention, the 10T SRAM cell includes: a first inverter, a second inverter, a transistor N1, a transistor N2, a transistor N3, a transistor N4, a transistor N5, and a transistor N6;

[0018] The control end of the transistor N1 and the control end of the transistor N2 are respectively connected to a write word line, the first end of the transistor N1 is connected to the input end of the first inverter, the output end of the second inverter, and the control end of the transistor N3, and the second end of the transistor N1 in the 10T SRAM cell connected to the first write bit line is connected to the first write bit line in the memory module in the same column;

[0019] The first end of the transistor N2 is connected to the output end of the first inverter, the input end of the second inverter, and the control end of the transistor N4, and the second end of the transistor N2 in the 10T SRAM cell connected to the second write bit line is connected to the second write bit line in the memory module in the same column;

[0020] The first end of the transistor N3 and the first end of the transistor N4 are grounded respectively, the second end of the transistor N3 is connected to the first end of the transistor N5, the second end of the transistor N5 is connected to the second read bit line in the storage module in the same column, the second end of the transistor N4 is connected to the first end of the transistor N6, the second end of the transistor N6 is connected to the first read bit line in the target storage module in the same column, and the control end of the transistor N5 and the control end of the transistor N6 are respectively connected to a read word line.

[0021] According to a further configuration of the present invention, the 11T NOR-cell unit includes: a transistor N7, a transistor N8, a transistor N9, a transistor N10, a transistor N11, a transistor N12, a transistor N13, a third inverter, and a fourth inverter;

[0022] The control end of the transistor N7 and the control end of the transistor N9 are respectively connected to another write word line, the first end of the transistor N7 is grounded, and the second end of the transistor N7 is connected to the first end of the transistor N8;

[0023] The second end of the transistor N8 is connected to the output end of the third inverter, the input end of the fourth inverter, and the control end of the transistor N10, and the control end of the transistor N8 is connected to the first end of the transistor N9;

[0024] The second end of the transistor N9 is connected to the input end of the third inverter, the output end of the fourth inverter and the control end of the transistor N11;

[0025] The first end of the transistor N11 and the first end of the transistor N10 are commonly grounded, the second end of the transistor N11 is connected to the first end of the transistor N12, and the second end of the transistor N10 is connected to the first end of the transistor N13;

[0026] The second end of the transistor N12 and the second end of the transistor N13 are connected and connected to the first read bit line in the same column of target memory modules, and the control end of the transistor N12 and the control end of the transistor N13 are respectively connected to another read word line.

[0027] In a further arrangement of the present invention, the chain XOR circuit comprises: a chain of n columns of inverters, a transistor N14 and a fifth inverter;

[0028] The inverter chain includes a first transmission gate, a second transmission gate, a third transmission gate, a transistor N15 and a sixth inverter;

[0029] The input terminal of the first transmission gate is connected to the sense amplifier, the output terminal of the first transmission gate is connected to one control terminal of the second transmission gate, the output terminal of the second transmission gate is connected to the input terminal of the sixth inverter, the other control terminal of the second transmission gate is connected to one control terminal of the third transmission gate, the input terminal of the second transmission gate is connected to the input terminal of the third transmission gate, the output terminal of the third transmission gate is connected to the output terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the input terminal of the second transmission gate in the inverter chain adjacent to the left. The control terminal of the transistor N15 is used to receive an enable signal, the first terminal of the transistor N15 is grounded, and the second terminal of the transistor N15 is connected to the output terminal of the first transmission gate.

[0030] The control terminal of the transistor N14 is used to receive an enable signal, a first terminal of the transistor N14 is connected to a first power supply, and a second terminal of the transistor N14 is connected to an input terminal of a second transmission gate in the inverter chain arranged along the first direction and located at a start position;

[0031] a fifth inverter, wherein the input end of the fifth inverter is connected to the output end of the sixth inverter in the inverter chain arranged along the first direction and located at the end, and the output end of the fifth inverter is connected to the shift driving module corresponding to the local XOR module in the (n+1)th column.

[0032] According to a further configuration of the present invention, the transistor N14 is a P-channel metal oxide semiconductor field effect transistor.

[0033] According to a further configuration of the present invention, the shift driving module includes: a multiplexer, a seventh inverter, a first buffer, and a second buffer;

[0034] The first buffer includes a ninth terminal, a tenth terminal for receiving an enable signal, and an eleventh terminal, wherein the eleventh terminal of the first buffer is connected to a first write bit line in a same column of memory modules;

[0035] The second buffer includes a twelfth terminal, a thirteenth terminal for receiving an enable signal, and a fourteenth terminal, the twelfth terminal of the second buffer is connected to the output terminal of the seventh inverter, and the fourteenth terminal of the second buffer is connected to the second write bit line in the same column of memory modules;

[0036] The multiplexer includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is connected to the input end of the seventh inverter and the ninth end of the first buffer. The second pin is connected to the circuit to be tested. The third pin is used to receive an enable signal. The fourth pin of the multiplexer corresponding to the local XOR module in the n+1th column along the first direction is connected to the output end of the chain XOR circuit. The fourth pin of the multiplexer of the first n columns of local XOR modules along the first direction is connected to the output end of the sense amplifier 102 corresponding to the local XOR module adjacent to the left.

[0037] According to a second aspect, an embodiment provides a method for testing an evaluation circuit in the memory as described above. When the test circuit in the memory serves as a linear feedback shift register, the test method includes:

[0038] The first writing step: writing an n-bit immediate value into the first n columns of local XOR modules along the first direction, and outputting the immediate value as a set of test vectors;

[0039] A first XOR calculation step: after a set of test vectors are output, performing a multi-input XOR calculation on the data in the first n columns of the local XOR modules, and transmitting the XOR calculation results to the local XOR module in the (n+1)th column along the first direction;

[0040] First shifting step: after the multi-input XOR calculation is completed, inter-column shifting is performed starting from the local XOR module of the n+1th column;

[0041] Test vector output step: after inter-column shifting, storing the inter-column shifted data into the first n columns of the local XOR module, and outputting the inter-column shifted data as a set of test vectors;

[0042] Repeating the first XOR calculation step to the test vector output step, so that the test circuit generates multiple groups of test vectors;

[0043] When the test circuit in the memory serves as a multi-input signature register, the test method includes:

[0044] The second writing step: writing the n-bit immediate number into the next n columns of storage modules along the first direction;

[0045] Test response capturing step: after writing the immediate value, capturing the test response output by the circuit under test, and writing the test response into the last n columns of the storage module;

[0046] Second XOR calculation step: after the test response is written, performing multi-input XOR calculation on the data in the first n columns of local XOR modules, and transmitting the XOR calculation result to the local XOR module in the (n+1)th column along the first direction;

[0047] In-memory XOR calculation step: after the multi-input XOR calculation, performing an in-memory XOR operation on the last n columns of storage modules;

[0048] A second inter-column shifting step: after the in-memory XOR operation, performing an inter-column shift starting from the local XOR module in the (n+1)th column, wherein the inter-column shifting occurs between the first storage unit and the second storage unit;

[0049] Response compression output step: compress and output the data after inter-column shifting as a set of responses;

[0050] Repeating the test response capturing step to the response compression outputting step, so that the test circuit outputs multiple groups of response compressions.

[0051] The present application discloses a memory and a testing method having a test function. When the memory is tested, at least two columns of target storage modules can be used, and each target storage module forms a local XOR module, wherein the first n columns of local XOR modules along the first direction can be used as a linear feedback shift register or a D trigger of a multi-input signature register when testing a test circuit in the memory, and the local XOR module in the n+1th column along the first direction is used to calculate the response compression result of the highest bit of the multi-input signature register, so that the test circuit in the memory can output a test vector and complete the test response compression. When no test is required, the target storage module can still be used as a storage module in the memory. It can be seen that when there is no trigger at the input end of the evaluation circuit in the memory, there is no need to add a linear feedback shift register, which reduces hardware overhead. At the same time, when no test is performed, the reused storage module can perform normal storage or calculation operations, thereby improving the storage density of the storage and computing architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a structural diagram of the digital domain SRAM storage structure;

[0053] Figure 2 An indirect testing method for an evaluation circuit of a memory;

[0054] Figure 3 A test method for an evaluation circuit of a scan chain-based memory;

[0055] Figure 4 It is a test method for the priority encoder of TCAM based on scan chain;

[0056] Figure 5 It is the circuit structure of a linear feedback shift register;

[0057] Figure 6 It is the circuit structure of a multi-input signature register;

[0058] Figure 7 It is a circuit structure diagram of a memory having a test function;

[0059] Figure 8 is a schematic diagram of the circuit structure of a local XOR module in an embodiment;

[0060] Figure 9 is a schematic diagram of the circuit structure of a 10T SRAM in an embodiment;

[0061] Figure 10 is a schematic diagram of the circuit structure of an 11T NOR-cell unit in an embodiment;

[0062] Figure 11 is a circuit structure diagram of a chain XOR circuit in an embodiment;

[0063] Figure 12 is a circuit structure diagram of a shift drive module in an embodiment;

[0064] Figure 13 is a working waveform diagram of the test circuit as a fourth-order linear feedback shift register in one embodiment;

[0065] Figure 14 is a waveform diagram of the operation of the test circuit as a fourth-order multi-input signature register in one embodiment;

[0066] Figure 15 This is a flow chart for testing the evaluation circuit when the test circuit is used as a linear feedback shift register.

[0067] Figure 16 This is a flow chart of the test circuit when it is used as a multi-input signature register test evaluation circuit. DETAILED DESCRIPTION

[0068] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments use associated similar element numbers. In the following embodiments, many detailed descriptions are intended to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions, and for those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0069] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0070] The serial numbers assigned to components herein, such as "first," "second," etc., are used solely to distinguish the objects being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" herein, unless otherwise specified, include both direct and indirect connections (couplings).

[0071] In data-intensive computing tasks such as neural network inference and training, data movement between the CPU (Central Processing Unit) / GPU (Graphics Processing Unit) and memory becomes a significant performance shortcoming. The data movement operation itself also introduces a large amount of unnecessary power consumption, which leads to the von Neumann bottleneck when computers process data-intensive tasks. In-memory computing architecture is considered an emerging computing paradigm that can effectively break the von Neumann bottleneck and improve the performance and energy efficiency of computing devices in data-intensive operations. Among them, the digital domain SRAM (Static Random-Access Memory) memory computing architecture based on static random access memory has been widely used due to its high memory access speed, mature manufacturing process, and good compatibility with CMOS (Complementary Metal Oxide Semiconductor) logic circuits.

[0072] As an extension of traditional storage, please refer to Figure 1 , Figure 1 It is the basic architecture of digital domain SRAM storage and computing architecture. Figure 1 In the figure, Address Decoder represents the address decoder; CellArray represents the cell array, that is, an array composed of multiple storage modules; Read / Write Circuit represents the read / write circuit; Evaluation Circuit represents the evaluation circuit; wherein, the digital domain SRAM storage and computing architecture can operate in both storage mode and computing mode. In storage mode, the digital domain SRAM storage and computing architecture can be regarded as a traditional memory. In computing mode, the digital domain SRAM storage and computing architecture usually needs to activate multiple rows of cells of the storage module at the same time to perform logical and arithmetic operations. In addition, the readout circuit used for computing operations is also different from the read of traditional memory, and the read circuit used for computing operations has a smaller sensing margin. Therefore, the computing operations of the digital domain SRAM storage and computing architecture are more sensitive to process, voltage and temperature changes. These reasons make the testing and reliability of the digital domain SRAM storage and computing architecture more challenging than traditional memory.

[0073] The digital domain SRAM storage and computing architecture is primarily composed of three parts: a storage module, peripheral circuits, and an evaluation circuit. The evaluation circuit is a combinational logic and sequential logic circuit embedded in the periphery of the storage module, such as an XOR gate, adder tree, multiplexer, and shift register. These circuit modules further process the logical operation results output by the storage module to implement complex arithmetic operations. Generally speaking, test vectors for combinational logic circuits can be generated using an automatic test vector generation algorithm. However, the input ports of the evaluation circuit are only connected to the computational output ports of the storage and computing array. The closed nature of its input ports prevents externally generated test vectors from reaching the original inputs of the evaluation circuit through conventional means. Considering this limitation, existing research has proposed a test method for the evaluation circuit of the digital domain SRAM storage and computing architecture: an indirect test method and a test method based on testability design.

[0074] Please refer to Figure 2 , Figure 2 Indirect testing method for memory evaluation circuit, Figure 2In the above, Row Decoder represents row decoder; ROW represents row; Erase represents erase; Priority Address Encoder & Hit Generator represents priority address encoder and access address generation device; Hit represents selected address; Matched Address represents matched address; Valid Bits represents data valid bit; Column Decoder represents column decoder; I / O Circuitry represents input / output circuit; Comparand Register represents comparison word register; Comparand represents comparison word of comparison register. Among them, "indirect" means that the externally generated test vector is input to the port of the evaluation circuit through the storage module in the memory, or the storage module uses its computing function to directly generate the required test vector inside the memory architecture, and then sends it to the evaluation circuit. Assume that there are k test vectors for the evaluation circuit obtained by ATPG (Automatic Test Pattern Generation), which are denoted as (t1, t2,…, t k-1 ,t k ). These test vectors can be generated by performing a combination of different logical functions on different operands. For example, the test vector t1 can be obtained by performing the logical operation f1 on the data X1 and Y1, that is, f1(X1, Y1) = t1. Then the data X1 and Y1 are first written into the storage module, and then the logical operation f1 is performed in the storage module, and the result of the calculation is sent to the evaluation circuit by the calculation output port of the storage module. Similarly, all k test vectors can be calculated by the storage module. The key to using the indirect test method to implement the test of the evaluation circuit is to convert the test vector into the calculation output of the storage module in the storage and computing architecture of the memory. The series of logical functions required by the storage module to generate the test vector constitutes the corresponding test algorithm. Taking into account that the test vectors required by different evaluation circuits are quite different, the indirect test method needs to repeatedly generate test vectors, which reduces the test efficiency to a certain extent.

[0075] Please refer to Figure 3 、 Figure 4 ,exist Figure 3 In the , Address Decode means address decoder; Cell Array means cell array, that is, an array composed of multiple storage modules; Read / Write Circuit means read / write circuit; EvaluationCircuit means evaluation circuit; SI means Scan_In (scan input); SO means Scan_Out (scan output); Figure 4In the figure, WL Decoder&Drivers represents the decoder and driver of the word line; TCAM in TCAM Array stands for Ternary Content Addressable Memory, Array stands for array, and TCAM Array stands for Ternary Content Addressable Memory array; Test Structures stands for test structure; MLSAs stands for Multi-Level Scan Analysis; Scan In (SI1) represents the first group of scan inputs; Scan Chain; SC1 represents the first scan chain; SC2 represents the second scan chain; Scan_Out represents scan output; SO1 represents the first group of scan outputs; SO2 represents the second group of scan outputs; MMR stands for Multiple Mode Register; MAE stands for Mean Absolute Error. Among them, the test method based on DFT (Design for Testability) only needs to modify the trigger into a scan trigger for the evaluation circuit with a trigger at the input end. The test vector generated by the external ATPG can be directly applied to the original input of the evaluation circuit through the scan chain, thereby realizing the test of the evaluation circuit. The test method based on the scan chain takes a long time to apply the test vector, which reduces the test efficiency. Of course, the trigger at the input end of the evaluation circuit can also be configured as a linear feedback shift register in the test mode. Figure 5 As shown in the figure, it is the basic structure diagram of the linear feedback shift register (LFSR). Figure 6 The figure shows the basic structure of the Multiple Input Signature Register (MISR), where an n-order linear feedback shift register can output up to 2 n -1 random, non-repeating n-bit sequences, thus enabling the use of linear feedback shift registers to generate pseudo-random test vectors for the evaluation circuits of digital-domain SRAM memory-computation architectures. Compared to scan chains, testing methods based on linear feedback shift registers are faster, and the additional area overhead introduced by converting flip-flops to linear feedback shift registers is negligible. However, for evaluation circuit designs without flip-flops at input ports, directly adding linear feedback shift registers introduces significant hardware overhead.

[0076] In response to the above problems, the present application provides a memory that also has a testing function. The architecture of the memory can be a digital domain SRAM storage and computing architecture. The testing function in the memory can test the evaluation circuit, that is, the evaluation circuit in the digital domain SRAM storage and computing architecture can be tested, wherein the evaluation circuit also refers to the circuit to be tested mentioned below.

[0077] In some embodiments, please refer to Figure 7 , Figure 7 is a structural schematic diagram of a memory, which may include multiple columns of memory modules 100 and a test circuit.

[0078] Each column storage module 100 includes at least one row of first storage cells 1012, at least three rows of second storage cells 1013, a first read bit line CBL, a second read bit line CBLB, a first write bit line GBL and a second write bit line GBLB, wherein the first storage cell 1012 and the second storage cell 1013 are connected to the first read bit line CBL, the second storage cell 1013 is also connected to the second read bit line CBLB, and at least two second storage cells 1013 are also connected to the first write bit line GBL and the second write bit line GBLB, respectively.

[0079] The test circuit uses at least n+1 columns of adjacent target memory modules 100, where n≥1. Each column of target memory modules 100 uses at least one row of first memory cells 1012 and three rows of second memory cells 1013. Each column of target memory modules 100 is provided with a NOR gate 1011. One input end of the NOR gate 1011 is connected to a first read bit line CBL in the target memory module 100 in the same column, the other input end of the NOR gate 1011 is connected to a second read bit line CBLB in the target memory module 100 in the same column, and the output end of the NOR gate 1011 is connected to the first memory cell 1012 in the target memory module 100 in the same column, so that each NOR gate 1011 and the multiplexed first memory cells 1012 and second memory cells 1013 in the target memory module 100 in the same column form a local XOR module 101 for performing an XOR operation. Figure 7 localXOR module in .

[0080] In which, the test circuit is used in the test process: the reused first storage unit 1012 is used to store the XOR operation result, the reused second storage unit 1013 is used to store data, and the first n columns of local XOR modules 101 along the first direction are used as D triggers in the linear feedback shift register or the multi-input signature register when the test circuit is tested. The local XOR module 101 is used to calculate the highest bit response compression result of the multi-input signature register, and the local XOR module 101 in the n+1th column along the first direction is used to temporarily store the highest bit data of the linear feedback shift register and the multi-input signature register.

[0081] In this embodiment, n can be 1, 3, 7, 8, etc. Those skilled in the art can determine the specific size of n according to actual conditions, and no further limitation is made here.

[0082] When the test circuit is tested, each column of target storage modules 100 forms a local XOR module 101, which can write data into the second storage unit 1013 through the first write bit line GBL and the second write bit line GBLB; the first read bit line CBL and the second read bit line CBLB read the data stored in the first storage unit 1012 and / or the second storage unit 1013, and can also load the logic operation result; the XOR operation is performed through the NOR gate 1011, so that the first n columns of local XOR modules 101 along the first direction can be used as D flip-flops in the linear feedback shift register or the multi-input signature register when the test circuit is tested, and the local XOR module 101 in the n+1th column along the first direction is used to temporarily store the data of the highest bit of the linear feedback shift register and the multi-input signature register.

[0083] In this embodiment, when the test circuit is not being tested, the target memory module 100 can function as a memory module 100 in the same manner as an unused memory module 100, storing and reading and writing data normally, or performing computational operations. Even when the evaluation circuit does not have a trigger at its input, this memory does not require a linear feedback shift register, reducing hardware overhead. Furthermore, when not being tested, the reused memory module 100 can perform normal storage or computational operations, thereby improving the storage density of the storage-computing architecture.

[0084] It should be noted that the target memory modules 100 mentioned above refer to memory modules 100 in a memory that are reused when the test circuit is tested, and each column of target memory modules 100 is a column of reused memory modules 100 .

[0085] In some embodiments, the memory further includes a sense amplifier 102 having n+1 input terminals and n+1 output terminals. Each input terminal of the sense amplifier 102 is connected to a first read bit line CBL in a target memory module 100. The sense amplifier 102 is used to sense a voltage change on the connected first read bit line CBL and output a sensing signal. Sorted starting from zero along the first direction, a row of second storage cells 1013 in all odd-numbered local XOR modules 101 share a read word line RWLo and a write word line WWLo, a row of second storage cells 1013 in all even-numbered local XOR modules 101 share a read word line RWLe and a write word line WWLe, a first storage cell 1012 in all odd-numbered local XOR modules 101 share a read word line RWLo4 and a write word line CWL, and a first storage cell 1012 in all even-numbered local XOR modules 101 share a read word line RWLe4 and a write word line CWL, wherein RWLo4 / RWLe4 are respectively read word lines of the first storage cell 1012, used to control the read port of the first storage cell 1012, and CWL are respectively write word lines of the first storage cell 1012, used to control the write port of the first storage cell 1012.

[0086] The test circuit also includes a chain XOR circuit 300 connected to the output end of the sense amplifier 102 corresponding to the first n columns of local XOR modules 101 along the first direction. The chain XOR circuit 300 is used to receive the sensing signal output by the sense amplifier 102 and perform a multi-input XOR operation to output the XOR operation result. The shift drive module 200, the shift drive module 200 corresponding to the first n columns of target storage modules 100 along the first direction is connected to the output end of the sense amplifier 102 corresponding to the local XOR module 101 adjacent to the left, the shift drive module 200 is also connected to the circuit to be tested, the shift drive module 200 corresponding to the local XOR module 101 in the n+1th column along the first direction is also connected to the chain XOR circuit 300, and in any two adjacent local XOR modules 101, the shift drive module 200 corresponding to the local XOR module 101 on the right is connected to the local XOR module 101 on the left; wherein, in the test circuit as a linear inversion When feeding the shift register, the shift driving module 200 corresponding to the first n columns of local XOR modules 101 along the first direction is used to access the immediate value and write it into the first n columns of local XOR modules 101 along the first direction; when the test circuit is used as a multi-input signature register, the shift driving module 200 is used to receive the test response of the circuit to be tested and output it to the local XOR module 101, the shift driving module 200 in the last n columns along the first direction is used to access the immediate value and write it into the last n columns of local XOR modules 101 along the first direction, and the shift driving module 200 corresponding to the local XOR module 101 in the (n+1)th column is also used to receive the XOR operation result.

[0087] Specifically, when writing an immediate number (the immediate number is used as a seed) into the local XOR module 101, the immediate number can be written into the second storage unit 1013 of the local XOR module 101 through the shift drive module 200, that is, an external circuit writes the immediate number into the corresponding shift drive module 200, and writes the immediate number into the second storage unit 1013 of the local XOR module 101 through the corresponding shift drive module 200, wherein the external circuit is any circuit that can write an immediate number into the shift drive module 200, and will not be elaborated on here.

[0088] For example, when it is necessary to write an immediate number into the first n columns of local XOR modules 101, an n-bit immediate number can be written into the shift driving module 200 corresponding to the first n columns of local XOR modules 101 along the first direction through an external circuit, and further, the immediate number is written into the second storage unit 1013 of the local XOR module 101 corresponding to each shift driving module 200 through the shift driving module 200 corresponding to the first n columns of local XOR modules 101 along the first direction. That is, each shift driving module 200 in the shift driving module 200 corresponding to the first n columns of local XOR modules 101 writes each bit into the local XOR module 101 corresponding to the shift driving module 200.

[0089] When the chain XOR circuit 300 performs a multi-input XOR calculation, the multiple inputs of the chain XOR circuit 300 are sensed by the sense amplifier 102, which then outputs a sensed signal to the chain XOR circuit 300 after sensing voltage changes on the first read bit line CBL in the first n columns of target memory modules 100 along the first direction. During inter-column shifting, the result of the multi-input XOR calculation by the chain XOR circuit 300 is output to the shift driver module 200 corresponding to the target memory module 100 in the (n+1)th column along the first direction. The shift driver module 200 then writes the result of the multi-input XOR calculation back to the corresponding target memory module 100. Furthermore, the shift driver module 200 corresponding to the first n columns of target memory modules 100 along the first direction obtains the shifted data through the output of the sense amplifier corresponding to the left-adjacent target memory module 100 and writes the shifted data into the corresponding target memory module 100. The shifted data is then sequentially written to the first n columns of target memory modules 100 along the first direction, thereby performing inter-column shifting.

[0090] In this embodiment, the sense amplifier 102 is also reused in the memory during testing, and there is no need to set up a separate sense amplifier 102, which further reduces hardware overhead.

[0091] In some embodiments, please refer to Figure 8The first storage unit 1012 is a 11T NOR-cell unit, and / or the second storage unit 1013 is a 10T SRAM unit.

[0092] In this embodiment, the first storage unit 1012 is a 11T NOR-cell unit, and the second storage unit is a 10T SRAM unit.

[0093] In some embodiments, please refer to Figure 9 The 10T SRAM cell may include a first inverter M1, a second inverter M2, a transistor N1, a transistor N2, a transistor N3, a transistor N4, a transistor N5, and a transistor N6.

[0094] The control terminal of transistor N1 and the control terminal of transistor N2 are each connected to a write word line. The first terminal of transistor N1 is connected to the input terminal of the first inverter M1, the output terminal of the second inverter M2, and the control terminal of transistor N3. The second terminal of transistor N1 in the 10T SRAM cell connected to the first write bit line GBL is connected to the first write bit line GBL in the same column of the target memory module 100. The first terminal of transistor N2 is connected to the output terminal of the first inverter M1, the input terminal of the second inverter M2, and the control terminal of transistor N4. The second terminal of transistor N2 in the 10T SRAM cell connected to the second write bit line GBLB is connected to the second write bit line GBLB in the same column of the target memory module 100. The first end of transistor N3 and the first end of transistor N4 are grounded respectively, the second end of transistor N3 is connected to the first end of transistor N5, the second end of transistor N5 is connected to the second read bit line CBLB in the target memory module 100 in the same column, the second end of transistor N4 is connected to the first end of transistor N6, the second end of transistor N6 is connected to the first read bit line CBL in the target memory module 100 in the same column, and the control end of transistor N5 and the control end of transistor N6 are respectively connected to a read word line.

[0095] In this embodiment, the control terminals of transistors N5 and N6 serve as read ports, and the control signals on the read word lines to which transistors N5 and N6 are connected can control the on / off switching of transistors N5 and N6. Similarly, the control terminals of transistors N1 and N2 serve as write ports, and the control signals on the write word lines to which transistors N1 and N2 are connected can control the on / off switching of transistors N1 and N2. A row of 10T SRAM cells in the target memory module 100 can be configured with a corresponding read word line and a corresponding write word line, and along the first direction, all 10T SRAM cells in a row of local XOR modules 101 located at odd bits share a write word line and a read word line, while all 10T SRAM cells in a row of local XOR modules 101 located at even bits share a write word line and a read word line.

[0096] In some embodiments, please refer to Figure 10 The 11T NOR-cell unit may include a transistor N7, a transistor N8, a transistor N9, a transistor N10, a transistor N11, a transistor N12, a transistor N13, a third inverter M3, and a fourth inverter M4.

[0097] The control terminal of transistor N7 and the control terminal of transistor N9 are each connected to another write word line. The first terminal of transistor N7 is grounded, and the second terminal of transistor N7 is connected to the first terminal of transistor N8. The second terminal of transistor N8 is connected to the output terminal of the third inverter M3, the input terminal of the fourth inverter M4, and the control terminal of transistor N10. The control terminal of transistor N8 is connected to the first terminal of transistor N9. The second terminal of transistor N9 is connected to the input terminal of the third inverter M3, the output terminal of the fourth inverter M4, and the control terminal of transistor N11. The first terminal of transistor N11 and the first terminal of transistor N10 are commonly grounded. The second terminal of transistor N11 is connected to the first terminal of transistor N12, and the second terminal of transistor N10 is connected to the first terminal of transistor N13. The second terminal of transistor N12 and the second terminal of transistor N13 are connected and connected to the first read bit line CBL in the same column of target memory module 100. The control terminal of transistor N12 and the control terminal of transistor N13 are each connected to another read word line.

[0098] In this embodiment, the control terminals of transistors N7 and N9 serve as write ports, and the on / off switching of transistors N7 and N9 can be controlled by a control signal on a write word line to which transistors N7 and N9 are connected. Similarly, the control terminals of transistors N12 and N13 serve as read ports, and the on / off switching of transistors N12 and N13 can be controlled by a control signal on a read word line to which the control terminals of transistors N12 and N13 are connected.

[0099] In some embodiments, please refer to Figure 11 The chain XOR circuit 300 may include an n-column inverter chain 301, a transistor N14, and a fifth inverter M5.

[0100] The inverter chain 301 includes a first transmission gate Q1, a second transmission gate Q2, a third transmission gate Q2, a transistor N15, and a sixth inverter M6. The input terminal of the first transmission gate Q1 is connected to the sense amplifier 102, the output terminal of the first transmission gate Q1 is connected to a control terminal of the second transmission gate Q2, the output terminal of the second transmission gate Q2 is connected to the input terminal of the sixth inverter M6, the other control terminal of the second transmission gate Q2 is connected to a control terminal of the third transmission gate Q2, the input terminal of the second transmission gate Q2 is connected to the input terminal of the third transmission gate Q2, the output terminal of the third transmission gate Q2 is connected to the output terminal of the sixth inverter M6, and the output terminal of the sixth inverter M6 is connected to the second transmission gate Q2 in the inverter chain 301 adjacent to the left. The control end of the transistor N15 is connected to the input end of the first transmission gate Q1, the first end of the transistor N15 is grounded, and the second end of the transistor N15 is connected to the output end of the first transmission gate Q1; the control end of the transistor N14 is connected to the enable signal, the first end of the transistor N14 is connected to the first power supply, and the second end of the transistor N14 is connected to the input end of the second transmission gate Q2 in the inverter chain 301 arranged along the first direction and located at the starting position; the input end of the fifth inverter M5 is connected to the output end of the sixth inverter M6 in the inverter chain 301 arranged along the first direction and located at the last position, and the output end of the fifth inverter M5 is connected to the shift driving module 200 corresponding to the target storage module 100 in the n+1th column along the first direction.

[0101] Specifically, transistor N14 is a P-MOS (Positive channel Metal Oxide Semiconductor) transistor. Transistor N15 is an N-MOS (Negative channel Metal-Oxide-Semiconductor) transistor. The chain XOR circuit 300 is deployed on the periphery of the storage module 100 during specific applications. It is a chain XOR circuit 300 composed of n+1 inverters (the sixth inverter M6 and the fifth inverter M5 in the n transmission chains) connected in sequence.

[0102] In the chain XOR circuit 300, the control signal of the P-MOS is the global low-level enable signal EN of the chain XOR circuit 300. That is, when the enable signal EN at the control end of the P-MOS is at a low level, the chain XOR circuit 300 performs a multi-input XOR calculation. When the enable signal EN is at a high level, the chain XOR circuit 300 does not perform a multi-input XOR calculation.

[0103] Each inverter chain 301 can be referred to as a "stage" in the chained XOR circuit. Each stage in the chained XOR circuit 300 receives the output of the previous stage. That is, the second transmission gate Q2 in each inverter chain 301 in the chained XOR circuit 300 receives the output of the sixth inverter M6 connected to the previous adjacent stage. The chained XOR circuit 300 implements a multi-input XOR operation. The logical expression for the XOR operation of n inputs is x0⊕x1…⊕x n-2 ⊕x n-1 ; Among them, x0, x1...x n-2 、x n-1 Each represents an input, that is, each represents an output of the n local XOR modules 101 connected to the chain XOR circuit 300.

[0104] Each stage of the chain XOR circuit 300 also receives the output of the connected local XOR module 101. The local XOR module 101 can control the two transmission gates (the second transmission gate Q2 and the third transmission gate Q2) on the corresponding inverter chain 301. When the signal provided by the local XOR module 101 is "1", the second transmission gate Q2 on the inverter chain 301 is opened and the third transmission gate Q2 on the bypass path is closed, which is equivalent to executing , where A is the output of the sixth inverter M6 connected adjacently before.

[0105] When the signal provided by the local XOR module 101 is "0", the third transmission gate Q2 is turned on and the second transmission gate Q2 is turned off, which is equivalent to executing A⊕0=A. In this way, by the output of the last stage (the transmission chain corresponding to the local XOR module in the nth column along the first direction), all inputs can be XORed, which is equivalent to executing the following logical expression: 1⊕(x0⊕x1…⊕x n-2 ⊕x n-1 ), and then passes through the fifth inverter M5 and is output to the shift driving module 200 corresponding to the local XOR module 101 of the n+1th column along the first direction to provide a shift signal.

[0106] In addition, for a linear feedback shift register or a multi-input signature register, not all inputs of the n local XOR modules 101 connected to the chain XOR circuit 300 need to participate in the multi-input XOR calculation. Therefore, it is necessary to control the state of the transistor N15 on the transmission chain to shield the inputs that do not need to participate in the multi-input XOR calculation. Specifically, when the enable signal at the control terminal of the transistor N15 is When the voltage is set to a high level, the transistor N15 is turned on to force the input signal to 0, and the signal increased by the local XOR module 101 connected to the transmission chain where the transistor N15 is located will be turned off by the first transmission gate Q1. For example, for a 4-stage linear feedback shift register or a multi-input signature register (reusing five columns of target storage modules, in which the first four columns of target storage modules along the first direction are respectively connected to the input end of the first transmission gate Q1 of a transmission chain), only the inputs of the 0th stage (the first column of target storage modules along the first direction) and the 1st stage (the second column of target storage modules along the first direction) need to perform multi-input XOR calculation. Therefore, the enable signal of the transistor N15 on the transmission chain corresponding to the local XOR module 101 in the first column along the first direction and the enable signal of the transistor N15 on the transmission chain corresponding to the local XOR module 101 in the second column are set to ( and ENT1) is low, the enable signals of transistors N15 on the other two transmission chains The output signal of the local XOR module corresponding to the transmission chain in which the enable signal of the transistor N15 is set to a high level is shielded and does not participate in the multi-input XOR calculation.

[0107] Based on the above description, it can be seen that when the chain XOR circuit 300 performs a multi-input XOR calculation, it counts the "0" and "1" in the data by using the data as the enable signal of the bypass path in the chain XOR circuit 300, and can obtain a multi-level XOR result in one step. Therefore, it is more efficient in multi-input XOR operations and inter-column shifting, so that the test circuit has a higher test speed.

[0108] In this embodiment, the primitive polynomials of linear feedback shift registers of different orders are different. As the order of the linear feedback shift register changes, the position of the latched data subjected to XOR also changes. The chain XOR circuit 300 can flexibly generate different XOR logics by configuring the inverter chain 301 and the control signals of each transmission gate (the first transmission gate Q1, the second transmission gate Q2, and the third transmission gate Q3) on the bypass path. Therefore, it can be seen that the linear feedback shift register implemented by the test circuit in the memory is easy to expand in order.

[0109] In some embodiments, please refer to Figure 12 The shift driving module 200 may include a multiplexer, a seventh inverter, a first buffer, and a second buffer.

[0110] Among them, the first buffer includes a ninth terminal, a tenth terminal for receiving an enable signal, and an eleventh terminal, and the eleventh terminal of the first buffer is connected to the first write bit line GBL in the target memory module 100 in the same column; the second buffer includes a twelfth terminal, a thirteenth terminal for receiving an enable signal, and a fourteenth terminal, the twelfth terminal of the second buffer is connected to the output terminal of the seventh inverter, and the fourteenth terminal of the second buffer is connected to the second write bit line GBLB in the target memory module 100 in the same column; the multiplexer includes a first pin, a second pin, a third pin, and a fourth pin, the first pin is connected to the input terminal of the seventh inverter and the ninth terminal of the first buffer, the second pin is connected to the circuit to be tested, and the third pin is used to receive the enable signal. The fourth pin of the multiplexer corresponding to the local XOR module 101 in the n+1th column along the first direction is connected to the output terminal of the chain XOR circuit 300, and the fourth pin of the multiplexer of the local XOR modules 101 in the first n columns along the first direction is connected to the output terminal of the sense amplifier 102 corresponding to the local XOR module 101 adjacent to the left.

[0111] In this embodiment, the second pin of the multiplexer is used to receive external data (i.e., an immediate value is written or the output of the capture evaluation circuit is captured via the second pin of the multiplexer), and the fourth pin of the multiplexer is used to receive internal data (the internal data is the result of the multi-input XOR calculation or the shifted data output by the fifth inverter M5 of the chained XOR circuit 300). When the enable signal ENM at the third pin of the multiplexer is high, the multiplexer receives the shifted data. When ENM is low, the multiplexer receives the external data. When the enable signal END connected to the tenth terminal of the first buffer and the thirteenth terminal of the second buffer is high, the data received by the multiplexer (external data or internal data) is written into the second storage cell 1013 in the same column of the target storage module 100. When the multiplexer is connected to the local XOR module 101 adjacent to the left in the first direction, the fourth pin of the multiplexer is connected to the first read bit line CBL of the local XOR module 101 adjacent to the left in the first direction.

[0112] In a specific embodiment, the multiplexer may be but is not limited to a 2-1 multiplexer, one signal input end of the 2-1 multiplexer is the fourth pin mentioned above, another signal input end of the 2-1 multiplexer is the second pin mentioned above, the signal output end of the 2-1 multiplexer is the first pin mentioned above, and the enable signal input end of the 2-1 multiplexer is the third pin mentioned above.

[0113] When writing data to the target storage module 100, the multiplexer can write data to the target storage module 100 in the same column through the first write bit line GBL and the second write bit line GBLB. When performing inter-column shifting, the shift signal can be obtained from the first read bit line CBL in the local XOR module 101 adjacent to the left along the first direction through the fourth pin of the multiplexer to perform inter-column shifting.

[0114] To further illustrate the test function of the memory, an example is given in which the target memory module 100 has five columns (equivalent to a fourth-order linear feedback shift register). Each column of the target memory module 100 multiplexes one row of 11T NOR-cell units and three rows of 10T SRAM units.

[0115] Specifically, the second pin of the multiplexer is connected to the evaluation circuit, the fourth pin of the multiplexer corresponding to the local XOR modules 101 of the first n columns along the first direction is connected to the first read bit line CBL in the adjacent left local XOR module 101, the eleventh terminal of the first buffer in each shift driving module 200 is connected to the first write bit line GBL in the target memory module 100 in the same column, the fourteenth terminal of the second buffer in each shift driving module 200 is connected to the second write bit line GBLB in the target memory module 100 in the same column, and the first read bit lines CBL in the local XOR modules 101 of the first n columns along the first direction are connected to the sense amplifiers 101 and 101, respectively. The sense amplifier 102 is connected to the input end of the sense amplifier 102, the output end of the sense amplifier 102 is connected to the input end of the first transmission gate Q1 in the chain XOR circuit 300 (the sense amplifier 102 has n input ends and n output ends, each input end of the sense amplifier 102 is correspondingly connected to the first read bit line CBL of a local XOR module 101 in the first n columns of local XOR modules 101 along the first direction, and each output end of the sense amplifier 102 is correspondingly connected to the input end of the first transmission gate Q1). The output end of the fifth inverter M5 in the chain XOR circuit 300 is connected to the fourth pin of the multiplexer corresponding to the local XOR module 101 located at the last position along the first direction.

[0116] When testing the circuit as a linear feedback shift register, please refer to Figure 15 , the specific test includes the following steps:

[0117] S1, first writing step: writing n-bit immediate data into the first n columns of local XOR modules along the first direction, and outputting the immediate data as a set of test vectors;

[0118] S2, first XOR calculation step: after a set of test vectors are output, multi-input XOR calculation is performed on the data in the first n columns of local XOR modules, and the XOR calculation results are transmitted to the local XOR module in the (n+1)th column along the first direction;

[0119] S3, first shift step: after the multi-input XOR calculation is completed, inter-column shift is performed starting from the local XOR module in the n+1th column;

[0120] S4, test vector output step: After the inter-column shift, the inter-column shifted data is stored in the first n columns of local XOR modules, and the inter-column shifted data is output as a group of test vectors.

[0121] Repeat the above steps S2-S4 to enable the test circuit to generate multiple groups of test vectors.

[0122] Specifically, in the first write step, a 4-bit immediate value is written into the local XOR modules of the first four columns along the first direction via a multiplexer. At this point, the enable signal ENM of the multiplexer's third pin is configured to a low level, the enable signals END of the first and second buffers are activated (END is high), and both word lines WWLe1 and WWLo1 of the first row of 10T SRAM cells in each column of the target memory module are activated. After both word lines WWLe1 and WWLo1 of the first row of 10T SRAM cells are activated, the first and second read bit lines in each column of the target memory module are precharged. After precharging, the read word lines RWLo1 and RWLe1 are activated. Thereafter, the seed number (i.e., the written immediate value) is read from the target memory module into which the immediate value is written and output as the first set of test vectors for the test circuit to the evaluation circuit.

[0123] In the first XOR calculation step, an enable signal EN of the chain XOR circuit is activated. The chain XOR circuit reads the data in the current test circuit (the data in each first row of 10T SRAM cells in the first n columns of the target memory modules along the first direction) through a sense amplifier and performs XOR according to the configuration of the linear feedback shift register. For a fourth-order linear feedback shift register, the inverse function of its m-sequence is x0⊕x3. In this case, ENT0 and ENT3 are activated, while ENT1 and ENT2 are maintained at a low level. After the chain XOR circuit obtains the XOR calculation result, the XOR calculation result is written into the first row of 10T SRAM cells in the target memory module in the (n+1)th column along the first direction.

[0124] In the first shift step, a two-clock-cycle inter-column shift operation is performed, completing the shift operations on the even and odd bits of the latched data in two clock cycles. In the first clock cycle, the even bits of the 4-bit data starting from the target memory module in the n+1th column along the first direction are shifted by the shift driver module to the two odd-numbered 10T SRAM cells in the second row, from the MSB (Most Significant Bit) column to the LSB (Least Significant Bit) column. At this time, the read word line RWLe1 of the even bits in the first row (including redundant bits, i.e., the target memory module in the n+1th column along the first direction) is activated, the write word line WWLo2 of the odd bits in the second row is activated, and the ENM1, ENM3, END1, and END3 of the shift driver module for the odd bits are activated. In the second clock cycle, the odd bits of the 4-bit data starting with the redundant column to the left of the MSB are shifted by the shift driver module to the two storage cells in the second row, from the MSB column to the LSB column. At this time, the read word line RWLo1 for the odd bits in the first row is activated, the write word line WWLe2 for the even bits in the second row is activated, and the ENM0, ENM2, END0, and END2 of the shift driver module for the even bits are activated. ENM0 indicates that the ENM signal of the multiplexer at position zero is activated (i.e., high level) in the sorting from zero in the first direction, ENM1 indicates that the ENM signal of the multiplexer at position one is activated, ENM2 indicates that the ENM signal of the multiplexer at position two is activated, and ENM3 indicates that the ENM signal of the multiplexer at position three is activated. END0 indicates that the enable signal END in the first buffer and the second buffer at the zero position is high; END1 indicates that the enable signal END in the first buffer and the second buffer at the one position is high; END2 indicates that the enable signal END in the first buffer and the second buffer at the two positions is high; END3 indicates that the enable signal END in the first buffer and the second buffer at the three positions is high.

[0125] In the test vector output step, the data in the second row of 10TSRAM cells in the first n columns of the target storage module along the first direction are read out as the second group of test vectors output of the linear feedback shift register, and the process is continued from the first XOR calculation step to input multiple groups of test vectors.

[0126] Please refer to Figure 13 , Figure 13 This is a waveform diagram of the test vector output by the linear feedback shift register with the immediate number 1101 as the seed. The output pseudo-random sequence (test vector) is "1101, 0110, 0011..."

[0127] It should be noted that, in the process of repeatedly executing steps S2-S4, the 10T SRAM cells in the first row and the 10T SRAM cells in the second row are performed alternately. For example, in one cycle, the shifted data is stored in the 10T SRAM cells in the first row, and in the next cycle, the shifted data is stored in the 10T SRAM cells in the second row.

[0128] In this embodiment, the test vector output of the linear feedback shift register is spaced apart by four clock cycles (not considering the pre-charge cycle).

[0129] When testing a circuit as a multi-input signature register, please refer to Figure 16 , the specific test includes the following steps:

[0130] S100, second writing step: writing an n-bit immediate number into the next n columns of storage modules along the first direction;

[0131] S101, test response capturing step: after writing the immediate value, capturing the test response output by the circuit under test, and writing the test response into the last n columns of storage modules;

[0132] S102, second XOR calculation step: after the test response is written, perform multi-input XOR calculation on the data in the first n columns of local XOR modules, and transmit the XOR calculation result to the local XOR module in the (n+1)th column along the first direction;

[0133] S103, in-memory XOR calculation step: after multi-input XOR calculation, perform in-memory XOR operation on the last n columns of storage modules;

[0134] S104, a second inter-column shifting step: after the in-memory XOR operation, performing an inter-column shift starting from the local XOR module in the (n+1)th column, wherein the inter-column shifting occurs between the first storage unit and the second storage unit;

[0135] S105, response compression and output step: compressing and outputting the data after inter-column shifting as a group of responses;

[0136] Repeat the above steps S101-S105 to enable the test circuit to output multiple groups of response compressions.

[0137] Specifically, please refer to Figure 5 、 Figure 6 , Figure 5 The circuit structure diagram of the linear feedback shift register is shown in Figure 2. Figure 5 The D in it represents a D flip-flop; Figure 6 This is the circuit structure diagram of the multi-input signature register. Figure 6The D in the figure also represents a D flip-flop. The circuit structure of a multi-input signature register differs from that of a linear feedback shift register only in that an adder module is added before each D flip-flop (in practice, a storage module can also be reused as an adder module). This allows each data bit to be XORed with an external test response d before entering the subsequent flip-flop, thus compressing the test response data.

[0138] In the second writing step, the 4-bit immediate number is written into the next n columns of storage modules along the first direction. For details, please refer to the process of writing immediate numbers when the test circuit serves as a linear feedback shift register, which will not be described in detail here.

[0139] In the test response capture step, after writing the immediate value, the first set of test responses (the first set of outputs from the evaluation circuit) is written to the next n columns of target memory modules along the first direction via the shift driver module. Considering the structure of the multi-input signature register, each bit of the test response is written to the third row of 10T SRAM cells in each of the next n columns of target memory modules along the first direction. At this point, the ENM4-ENM1 signals are configured to a low level, END4-END1 are activated, and both write word lines WWLe3 and WWLo3 of the third row of 10T SRAM cells are activated. The explanations for ENM4-ENM1 refer to those for ENM0-ENM3 above and are omitted here. The explanations for END4-END1 refer to those for END0-END3 above and are omitted here.

[0140] In the second XOR calculation step, after the test response is captured and written, the enable signal EN of the chain XOR circuit is activated. The chain XOR circuit reads the data within the current test circuit (the data within each first row of 10T SRAM cells in the first n columns of target memory modules along the first direction) through a sense amplifier, performs XOR calculations according to the configuration of the linear feedback shift register, and writes the XOR calculation results into the first row of 10T SRAM cells in the n+1th column of target memory modules along the first direction. Simultaneously, to improve the throughput of the test circuit, the second set of test response data output by the evaluation circuit is written in a pipelined manner into the second row of 10T SRAM cells in the four columns of target memory modules starting with the redundant column to the left of the MSB. At this time, the ENM4-ENM1 signals are configured to a low level, END4-END1 are activated, and the two write word lines of the second row of standard 10T cells are activated.

[0141] In the in-memory XOR calculation step, after WWLe2 and WWLo2 are activated, an in-memory XOR operation is performed in parallel within the four columns of target memory modules, starting with the redundant column to the left of the MSB. After precharging the first and second read bit lines of each column, the read word lines RWLe1, RWLe3, RWLo1, and RWLo3 of the first row of 10T SRAM cells in each column of target memory modules are simultaneously activated, and the write word line CWL of the 11T NOR cells in each column of target memory modules is also activated. Because the read word lines of two rows of 10T SRAM cells (the first row of 10T SRAM cells and the third row of 10T SRAM cells) are simultaneously activated, data-dependent discharges occur on the first and second read bit lines in each column of target memory modules. The bitwise AND and bitwise NOR calculations are performed on each bit of the test response, respectively, based on the seed numbers read by the first and second read bit lines. Furthermore, the write word line CWL of the 11T NOR-cell is also activated, and the bitwise AND and bitwise NOR results are further NORed to obtain a per-bit XOR result, which is then written to the storage node Q4 of the 11T NOR-cell in the corresponding target memory module.

[0142] In the second inter-column shift step, after the XOR result is written to the storage node Q4 of the 11T NOR-cell, an inter-column shift operation is performed for two clock cycles. The multi-input signature register performs the inter-column shift operation between the 11T NOR-cell and the first row of 10T SRAM cells. The specific process can be referred to as the specific shift process when the above-mentioned test circuit is used as a linear feedback shift register, and will not be repeated here. After the inter-column shift is completed, the seed number stored in the first row of 10T SRAM cells is overwritten by the first round of 4-bit compression results. Finally, the data stored in the first row of 10T SRAM cells is output as the first round of compression results. Simultaneously, starting with step S101, steps S101-S105 are repeatedly executed. The pipelined writing of test responses alternates between the second row of 10T SRAM cells and the third row of 10T SRAM cells. In-memory XOR calculations in the target memory module alternate between the data in the first row of 10T SRAM cells, the data in the second row of 10T SRAM cells, and the data in the third row of 10T SRAM cells. The data stored in each row of 10T SRAM cells during the operation of the multi-input signature register is shown in Table 1.

[0143] Table 1. Data stored in each row of 10T SRAM cells during the operation of the multi-input signature register

[0144] Compression result round 10T unit in row 1 10T unit in row 2 10T unit in row 3 1 Count seeds immediately Group 2 responses Group 1 responses 2 Results of the first round of compression Group 2 responses Group 3 responses 3 Second round of compression results Group 4 Response Group 3 responses 4 Results of the third round of compression Group 4 Response Group 5 Response 5 Results of the 4th round of compression Group 6 Response Group 5 Response 6 … … …

[0145] Please refer to Figure 14 , Figure 14 This is a waveform diagram of a multi-input signature register with the immediate number 0001 as the seed and 1111 as the first set of test responses. The compression result sequence is “0111, 1011, …”.

[0146] In this embodiment, the target storage module performs an in-memory XOR operation based on data-dependent discharge, and can realize the bit-by-bit XOR operation of the latched data in the multi-input signature register and the test response through a one-step operation. The time for the multi-input signature register to perform one compression is six clock cycles (excluding the pre-charge cycle).

[0147] In this memory, the test of the test circuit itself is relatively simple, and the test of each functional module in the test circuit can be covered by the test of the entire memory module. Therefore, there is no need to develop a separate test algorithm when the test circuit is used.

[0148] In some embodiments, the present invention further provides a method for testing the evaluation circuit in the memory as described above. When the test circuit in the memory is used as a linear feedback shift register, please refer to Figure 15 , the test method comprises the following steps:

[0149] S1, first writing step: writing n-bit immediate data into the first n columns of local XOR modules along the first direction, and outputting the immediate data as a set of test vectors;

[0150] S2, first XOR calculation step: after a set of test vectors are output, multi-input XOR calculation is performed on the data in the first n columns of local XOR modules, and the XOR calculation results are transmitted to the local XOR module in the (n+1)th column along the first direction;

[0151] S3, first shift step: after the multi-input XOR calculation is completed, inter-column shift is performed starting from the local XOR module in the n+1th column;

[0152] S4, test vector output step: After the inter-column shift, the inter-column shifted data is stored in the first n columns of local XOR modules, and the inter-column shifted data is output as a group of test vectors.

[0153] Repeat the above steps S2-S4 to enable the test circuit to generate multiple test vectors. The details are as described in the above embodiment of a memory with a test function, and will not be repeated here.

[0154] Please refer to Figure 16 , when the test circuit in the memory serves as a multi-input signature register, the test method comprises the following steps:

[0155] S100, second writing step: writing an n-bit immediate number into the next n columns of storage modules along the first direction;

[0156] S101, test response capturing step: after writing the immediate value, capturing the test response output by the circuit under test, and writing the test response into the last n columns of storage modules;

[0157] S102, second XOR calculation step: after the test response is written, perform multi-input XOR calculation on the data in the first n columns of local XOR modules, and transmit the XOR calculation result to the local XOR module in the (n+1)th column along the first direction;

[0158] S103, in-memory XOR calculation step: after multi-input XOR calculation, perform in-memory XOR operation on the last n columns of storage modules;

[0159] S104, a second inter-column shifting step: after the in-memory XOR operation, performing an inter-column shift starting from the local XOR module in the (n+1)th column, wherein the inter-column shifting occurs between the first storage unit and the second storage unit;

[0160] S105, response compression and output step: compressing and outputting the data after inter-column shifting as a group of responses;

[0161] Repeat the above steps S101-S105 to enable the test circuit to output multiple groups of response compressions. The details are as described in the above embodiment of a memory with a test function, and will not be repeated here.

[0162] In summary, the present application provides a memory and a testing method with testing functions, which have the following beneficial effects:

[0163] When there is no trigger at the input of the evaluation circuit in the memory, there is no need to add a linear feedback shift register, which reduces hardware overhead. At the same time, when not being tested, the reused storage module can perform normal storage or computing operations, thereby improving the storage density of the storage and computing architecture.

[0164] The above examples are used to illustrate the present invention, which are only used to help understand the present invention and are not intended to limit the present invention. Those skilled in the art can make several simple deductions, modifications or substitutions based on the concept of the present invention.

Claims

1. A memory having a test function, characterized in that: include: A plurality of columns of memory modules, each column of the memory modules comprising at least one row of first memory cells, at least three rows of second memory cells, a first read bit line, a second read bit line, a first write bit line, and a second write bit line, wherein the first memory cell and the second memory cell are connected to the first read bit line, the second memory cell is further connected to the second read bit line, and at least two second memory cells are further connected to the first write bit line and the second write bit line, respectively; A test circuit, wherein the test circuit utilizes at least n+1 columns of adjacent target memory modules, where n≥1, and wherein at least one row of first memory cells and three rows of second memory cells are reused in each column of the target memory modules. A NOR gate is provided in each column of the target memory modules, wherein one input of the NOR gate is connected to a first read bit line in the target memory modules in the same column, another input of the NOR gate is connected to a second read bit line in the target memory modules in the same column, and an output of the NOR gate is connected to the first memory cell in the target memory modules in the same column, so that each NOR gate and the reused first and second memory cells in the target memory modules in the same column form a local XOR module for performing an XOR operation. In which, during the test process of the test circuit: the reused first storage unit is used to store the XOR operation result, the reused second storage unit is used to store data, and the first n columns of local XOR modules along the first direction are used as D flip-flops in a linear feedback shift register or a multi-input signature register when testing the test circuit, the local XOR module is used to calculate the highest bit response compression result of the multi-input signature register, and the local XOR module in the n+1th column along the first direction is used to temporarily store the highest bit data of the linear feedback shift register and the multi-input signature register.

2. The memory according to claim 1, wherein The memory further includes a sense amplifier having n+1 input terminals and an output terminal, each input terminal of the sense amplifier being connected to a first read bit line in a target memory module, and the sense amplifier being configured to sense a voltage change on the connected first read bit line and output a sensed signal; Sorting along the first direction starting from zero, all second storage cells in a row of local XOR modules located at odd bits share a read word line and a write word line, all second storage cells in a row of local XOR modules located at even bits share a read word line and a write word line, all first storage cells in local XOR modules located at odd bits share a read word line and a write word line, and all first storage cells in local XOR modules located at even bits share a read word line and a write word line; The test circuit further includes: a chain XOR circuit connected to the output terminals of the sense amplifiers corresponding to the first n columns of local XOR modules along the first direction, the chain XOR circuit being configured to receive the sensing signals output by the sense amplifiers and perform a multi-input XOR operation to output an XOR operation result; A shift driving module, wherein one shift driving module is provided for each local XOR module. The shift driving modules corresponding to the first n columns of target storage modules along the first direction are connected to the output end of the sense amplifier corresponding to the local XOR module adjacent to the left. The shift driving module is also connected to the circuit to be tested. The shift driving module corresponding to the local XOR module in the (n+1)th column along the first direction is also connected to the chain XOR circuit. In addition, among any two adjacent local XOR modules, the shift driving module corresponding to the local XOR module on the right is connected to the local XOR module on the left. Wherein, when the test circuit serves as the linear feedback shift register, the shift driving modules corresponding to the first n columns of local XOR modules along the first direction are used to access the immediate data and write it into the first n columns of local XOR modules along the first direction; When the test circuit serves as a multi-input signature register, the shift drive module is used to receive the test response of the circuit to be tested and output it to the local XOR module. The shift drive modules in the last n columns along the first direction are used to access the immediate value and write it into the local XOR modules in the last n columns along the first direction. The shift drive module corresponding to the local XOR module in the (n+1)th column is also used to receive the XOR operation result.

3. The memory according to claim 2, wherein: The first storage unit is a 11T NOR-cell unit, and / or the second storage unit is a 10T SRAM unit.

4. The memory according to claim 3, wherein: The 10T SRAM cell includes: a first inverter, a second inverter, a transistor N1, a transistor N2, a transistor N3, a transistor N4, a transistor N5 and a transistor N6; The control end of the transistor N1 and the control end of the transistor N2 are respectively connected to a write word line, the first end of the transistor N1 is connected to the input end of the first inverter, the output end of the second inverter, and the control end of the transistor N3, and the second end of the transistor N1 in the 10T SRAM cell connected to the first write bit line is connected to the first write bit line in the memory module in the same column; The first end of the transistor N2 is connected to the output end of the first inverter, the input end of the second inverter, and the control end of the transistor N4, and the second end of the transistor N2 in the 10T SRAM cell connected to the second write bit line is connected to the second write bit line in the memory module in the same column; The first end of the transistor N3 and the first end of the transistor N4 are grounded respectively, the second end of the transistor N3 is connected to the first end of the transistor N5, the second end of the transistor N5 is connected to the second read bit line in the storage module in the same column, the second end of the transistor N4 is connected to the first end of the transistor N6, the second end of the transistor N6 is connected to the first read bit line in the target storage module in the same column, and the control end of the transistor N5 and the control end of the transistor N6 are respectively connected to a read word line.

5. The memory according to claim 3, wherein: The 11T NOR-cell unit includes: a transistor N7, a transistor N8, a transistor N9, a transistor N10, a transistor N11, a transistor N12, a transistor N13, a third inverter, and a fourth inverter; The control end of the transistor N7 and the control end of the transistor N9 are respectively connected to another write word line, the first end of the transistor N7 is grounded, and the second end of the transistor N7 is connected to the first end of the transistor N8; The second end of the transistor N8 is connected to the output end of the third inverter, the input end of the fourth inverter, and the control end of the transistor N10, and the control end of the transistor N8 is connected to the first end of the transistor N9; The second end of the transistor N9 is connected to the input end of the third inverter, the output end of the fourth inverter and the control end of the transistor N11; The first end of the transistor N11 and the first end of the transistor N10 are commonly grounded, the second end of the transistor N11 is connected to the first end of the transistor N12, and the second end of the transistor N10 is connected to the first end of the transistor N13; The second end of the transistor N12 and the second end of the transistor N13 are connected and connected to the first read bit line in the same column of target memory modules, and the control end of the transistor N12 and the control end of the transistor N13 are respectively connected to another read word line.

6. The memory according to any one of claims 2 to 5, wherein: The chain XOR circuit includes: n columns of inverter chains, a transistor N14 and a fifth inverter; The inverter chain includes a first transmission gate, a second transmission gate, a third transmission gate, a transistor N15 and a sixth inverter; The input terminal of the first transmission gate is connected to the sense amplifier, the output terminal of the first transmission gate is connected to one control terminal of the second transmission gate, the output terminal of the second transmission gate is connected to the input terminal of the sixth inverter, the other control terminal of the second transmission gate is connected to one control terminal of the third transmission gate, the input terminal of the second transmission gate is connected to the input terminal of the third transmission gate, the output terminal of the third transmission gate is connected to the output terminal of the sixth inverter, and the output terminal of the sixth inverter is connected to the input terminal of the second transmission gate in the inverter chain adjacent to the left. The control terminal of the transistor N15 is used to receive an enable signal, the first terminal of the transistor N15 is grounded, and the second terminal of the transistor N15 is connected to the output terminal of the first transmission gate. The control terminal of the transistor N14 is used to receive an enable signal, a first terminal of the transistor N14 is connected to a first power supply, and a second terminal of the transistor N14 is connected to an input terminal of a second transmission gate in the inverter chain arranged along the first direction and located at a start position; a fifth inverter, wherein the input end of the fifth inverter is connected to the output end of the sixth inverter in the inverter chain arranged along the first direction and located at the end, and the output end of the fifth inverter is connected to the shift driving module corresponding to the local XOR module in the (n+1)th column.

7. The memory according to claim 6, wherein: The transistor N14 is a P-channel metal oxide semiconductor field effect transistor.

8. The memory according to claim 2, wherein: The shift driving module includes: a multiplexer, a seventh inverter, a first buffer and a second buffer; The first buffer includes a ninth terminal, a tenth terminal for receiving an enable signal, and an eleventh terminal, wherein the eleventh terminal of the first buffer is connected to a first write bit line in a same column of memory modules; The second buffer includes a twelfth terminal, a thirteenth terminal for receiving an enable signal, and a fourteenth terminal, the twelfth terminal of the second buffer is connected to the output terminal of the seventh inverter, and the fourteenth terminal of the second buffer is connected to the second write bit line in the same column of memory modules; The multiplexer includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is connected to the input end of the seventh inverter and the ninth end of the first buffer. The second pin is connected to the circuit to be tested. The third pin is used to receive an enable signal. The fourth pin of the multiplexer corresponding to the local XOR module in the n+1th column along the first direction is connected to the output end of the chain XOR circuit. The fourth pin of the multiplexer of the first n columns of local XOR modules along the first direction is connected to the output end of the sense amplifier 102 corresponding to the local XOR module adjacent to the left.

9. A method for testing an evaluation circuit in a memory according to any one of claims 1 to 8, characterized in that: When the test circuit in the memory serves as a linear feedback shift register, the test method includes: The first writing step: writing an n-bit immediate value into the first n columns of local XOR modules along the first direction, and outputting the immediate value as a set of test vectors; A first XOR calculation step: after a set of test vectors are output, performing a multi-input XOR calculation on the data in the first n columns of the local XOR modules, and transmitting the XOR calculation results to the local XOR module in the (n+1)th column along the first direction; First shifting step: after the multi-input XOR calculation is completed, inter-column shifting is performed starting from the local XOR module of the n+1th column; Test vector output step: after inter-column shifting, storing the inter-column shifted data into the first n columns of the local XOR module, and outputting the inter-column shifted data as a set of test vectors; Repeating the first XOR calculation step to the test vector output step, so that the test circuit generates multiple groups of test vectors; When the test circuit in the memory serves as a multi-input signature register, the test method includes: The second writing step: writing the n-bit immediate number into the next n columns of storage modules along the first direction; Test response capturing step: after writing the immediate value, capturing the test response output by the circuit under test, and writing the test response into the last n columns of the storage module; Second XOR calculation step: after the test response is written, performing multi-input XOR calculation on the data in the first n columns of local XOR modules, and transmitting the XOR calculation result to the local XOR module in the (n+1)th column along the first direction; In-memory XOR calculation step: after the multi-input XOR calculation, performing an in-memory XOR operation on the last n columns of storage modules; A second inter-column shifting step: after the in-memory XOR operation, performing an inter-column shift starting from the local XOR module in the (n+1)th column, wherein the inter-column shifting occurs between the first storage unit and the second storage unit; Response compression output step: compress and output the data after inter-column shifting as a set of responses; Repeating the test response capturing step to the response compression outputting step, so that the test circuit outputs multiple groups of response compressions.

Images