Register renaming device, processor and method for maintaining register mapping table

Abstract

The invention discloses a register renaming device, a processor and a method for maintaining a register mapping table, and belongs to the technical field of computers. The register renaming device comprises a mapping table caching module, a control module, a recovery module and a reordering caching ROB module, and the recovery module is configured to rename a renamed register when a speculative path of a branch instruction is wrong and a copy distributed for the branch instruction is covered. And if the number of the program instructions between the program instruction pointed by the retirement pointer of the ROB module and the branch instruction in the ROB module is greater than the number of the program instructions on the speculative path, restoring the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module. According to the register renaming device provided by the invention, unexpected modifications in the first register mapping table can be recovered by combining the copies and the ROB module under the condition that the number of the copies is smaller than the number of the branch instructions, the recovery efficiency is high, and the resource overhead is low.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a register renaming device, a processor, and a method for maintaining a register mapping table. Background Art

[0002] A branch instruction is a special program instruction that can point to different execution directions based on different branch conditions, thereby changing the execution path of the program instructions. Branch prediction technology can predict the execution direction of branch instructions in advance, reducing pipeline stalls caused by waiting for branch conditions. In processors that use register renaming technology, the program instructions obtained after branch prediction will modify the register renaming map. If the branch prediction is incorrect, the program instructions' modifications to the register renaming map must be reverted as soon as possible.

[0003] In the related art, methods for restoring a register renaming mapping table generally include: restoring based on a mapping table copy, restoring based on a reorder cache, and restoring after waiting for a branch instruction to be submitted.

[0004] However, in the above methods, recovery based on a mapping table copy will increase the area cost of the processor, and recovery based on a reorder cache and recovery after waiting for a branch instruction to be submitted will result in a slow recovery speed. Summary of the Invention

[0005] The present application provides a register renaming device, a processor, and a method for maintaining a register mapping table to solve the technical problems existing in the related art. Specifically, the present application includes the following technical solutions.

[0006] In a first aspect, the present application provides a register renaming device, the device comprising: a mapping table cache module configured to store a first register mapping table, the first register mapping table being used to indicate a reorder cache ROB (reorder a first mapping relationship between a program instruction in a buffer) module; a control module configured to write the program instruction into the ROB module in a semantic order of the program instruction and modify the first register mapping table according to the program instruction; if the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, recording the first register mapping table through a copy allocated to the branch instruction; the ROB module configured to manage the program instructions in the semantic order and record the modification of the first register mapping table based on the program instruction; and a recovery module configured to, if a speculation path of the branch instruction is incorrect and the copy allocated to the branch instruction is overwritten, recover the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module if the number of program instructions between the program instruction pointed to by the retired pointer of the ROB module in the ROB module and the branch instruction is greater than the number of program instructions on the speculation path; wherein the number of copies is less than the number of branch instructions, and the speculation path indicates a speculation of an execution path of the program instruction following the branch instruction.

[0007] In some possible embodiments, the branch instruction includes a first branch instruction and a second branch instruction, the time when the first branch instruction is written to the ROB module is after the time when the second branch instruction is written to the ROB module, and the time interval between the first branch instruction and the second branch instruction being written to the ROB module is less than a first time threshold; the copy includes a first copy allocated for the first branch instruction and a second copy allocated for the second branch instruction; the recovery module is configured to: when the speculation path of the branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, restore the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module, when the speculation path of the first branch instruction is incorrect and the first copy is overwritten, restore the modification of the first register mapping table based on the first branch instruction according to the second copy and the ROB module.

[0008] In some possible implementations, the recovery module is further configured to: when the speculation path of the branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module in the ROB module and the branch instruction is less than the number of program instructions on the speculation path, restore the modification of the first register mapping table based on the branch instruction according to the second register mapping table and the ROB module; wherein the second register mapping table is used to indicate a second mapping relationship of the committed program instructions in the ROB module.

[0009] In some possible embodiments, the branch instruction includes a third branch instruction and multiple fourth branch instructions, the time when the third branch instruction is written to the ROB module is after the time when the multiple fourth branch instructions are written to the ROB module, and the copy includes multiple copies; before modifying the first register mapping table according to the branch instruction, the control module is configured to record the first register mapping table by the copy allocated to the branch instruction: before modifying the first register mapping table according to the third branch instruction, if the multiple copies have been allocated to the multiple fourth branch instructions, the copy allocated to one of the multiple fourth branch instructions will be reallocated to the third branch instruction, and the content in the copy reallocated to the third branch instruction will be overwritten by the first register mapping table corresponding to the third branch instruction.

[0010] In some possible implementations, the time interval between writing the third branch instruction and the fourth branch instruction into the ROB module is greater than a second time threshold.

[0011] In a second aspect, the present application provides a processor comprising: a branch instruction prediction unit and a register renaming device, wherein the branch instruction prediction unit is used to determine a speculated path of a branch instruction in a program instruction and send the speculated path to the register renaming device, and the register renaming device is such as the device described in any one of the first aspects of the present application.

[0012] In a third aspect, the present application provides a method for maintaining a register mapping table, the method comprising: writing the program instructions into a reordering cache (ROB) module in a semantic order of the program instructions, and modifying a first register mapping table according to the program instructions; if the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, recording the first register mapping table through a copy allocated to the branch instruction; in a case where the speculation path of the branch instruction is incorrect and the copy allocated to the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module in the ROB module and the branch instruction is greater than the number of program instructions on the speculation path, restoring the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module; wherein the first register mapping table is used to indicate a first mapping relationship of the program instructions in the ROB module, the ROB module is used to manage the program instructions in the semantic order and record the modification of the first register mapping table based on the program instructions, the number of copies is less than the number of branch instructions, and the speculation path indicates the speculation of the execution path of the program instruction after the branch instruction.

[0013] In some possible embodiments, the branch instruction includes a first branch instruction and a second branch instruction, the time when the first branch instruction is written to the ROB module is after the time when the second branch instruction is written to the ROB module, and the time interval between the time when the first branch instruction and the second branch instruction are written to the ROB module is less than a first time threshold; the copy includes a first copy allocated for the first branch instruction and a second copy allocated for the second branch instruction; when the speculation path of the branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, the recovery of the modification to the first register mapping table based on the branch instruction according to the copy and the ROB module includes: when the speculation path of the first branch instruction is incorrect and the first copy is overwritten, the recovery of the modification to the first register mapping table based on the first branch instruction according to the second copy and the ROB module.

[0014] In some possible implementations, the method further includes: when the speculation path of the branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module in the ROB module and the branch instruction is less than the number of program instructions on the speculation path, restoring the modification of the first register mapping table based on the branch instruction according to the second register mapping table and the ROB module; wherein the second register mapping table is used to indicate a second mapping relationship of the program instructions submitted in the ROB module.

[0015] In some possible embodiments, the branch instruction includes a third branch instruction and multiple fourth branch instructions, the time when the third branch instruction is written to the ROB module is after the time when the multiple fourth branch instructions are written to the ROB module, and the copy includes multiple copies; before modifying the first register mapping table according to the branch instruction, recording the first register mapping table through the copy allocated to the branch instruction includes: before modifying the first register mapping table according to the third branch instruction, if the multiple copies have been allocated to the multiple fourth branch instructions, reallocating the copy allocated to one of the multiple fourth branch instructions to the third branch instruction, and overwriting the content in the copy reallocated to the third branch instruction through the first register mapping table corresponding to the third branch instruction.

[0016] In some possible implementations, the time interval between writing the third branch instruction and the fourth branch instruction into the ROB module is greater than a second time threshold.

[0017] In a fourth aspect, the present application provides a computer-readable storage medium on which program instructions for maintaining a register mapping table are stored. When the program instructions are executed by one or more processors, the processors implement the method described in any one of the third aspects of the present application.

[0018] In a fifth aspect, the present application provides a computer program product, which includes a computer program, and the computer program is executed by a processor to enable the computer to implement any method described in the third aspect.

[0019] The beneficial effects of the technical solution provided by this application include at least:

[0020] The technical solution provided in the present application can, on the one hand, limit the number of copies used so that the number of copies is less than the number of branch instructions, which is beneficial to reducing the area cost of the device; on the other hand, when the number of copies is less than the number of branch instructions, when the speculation path of the branch instruction is wrong and the copy allocated to the branch instruction is overwritten, the copy and ROB module can be combined to recover the unexpected modifications in the first register mapping table, which is beneficial to improve the recovery speed of the unexpected modifications in the first register mapping table and reduce resource overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 is a structural diagram of a register renaming device provided in an embodiment of the present application;

[0023] Figure 2 This is a schematic diagram of the architecture of a register renaming device provided in an embodiment of the present application;

[0024] Figure 3 is a flow chart of a method for maintaining a register mapping table provided in an embodiment of the present application;

[0025] Figure 4 It is a structural diagram of the processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0028] In traditional scenarios with a low level of hardware abstraction, program instructions are typically executed by directly manipulating logical registers, which have a fixed one-to-one correspondence with physical registers. In this case, data dependencies may arise between program instructions due to accessing the same logical register. For example, one program instruction may need to wait for another program instruction to complete a read or write operation on a logical register before it can access that register. This can cause pauses in the execution of program instructions and reduce processing efficiency.

[0029] Register renaming technology can introduce more physical registers, making the number of physical registers greater than the number of logical registers. Logical registers are dynamically mapped to physical registers through a register renaming mapping table (also called a register mapping table), allowing each logical register to be mapped to multiple physical registers. This eliminates false data dependencies between program instructions, supports out-of-order execution of program instructions, and improves the parallelism of program instructions. The dynamic mapping relationship between logical and physical registers can be adjusted based on the execution of program instructions.

[0030] Data dependencies, also known as data dependence, include read-after-write dependencies, where one program instruction needs to read data written by another; write-after-read dependencies, where one program instruction writes to a register and another instruction needs to read the same register; and write-after-write dependencies, where two program instructions need to write to the same register. Write-after-read dependencies and write-after-write dependencies are false data dependencies because they don't logically exist.

[0031] Branch prediction technology can predict the execution direction of branch instructions in advance. Since the execution of branch instructions usually requires evaluating the branch conditions of the branch instructions to determine the execution direction of the branch instructions, the execution process of program instructions may enter a stalled state. In view of this, branch prediction technology can be used to predict the execution direction of branch instructions and determine the speculated path of the branch instructions, so that program instructions on the speculated path can be processed in advance, reducing pauses in the program instruction processing process. Among them, the speculated path is used to indicate the execution path of the program instructions after the branch instruction.

[0032] In scenarios where branch prediction technology and register renaming technology are used, out-of-order execution of program instructions and speculative execution of branch instructions are supported. To ensure the correctness of the program, it is usually necessary to manage the execution status and submission order of program instructions through the reorder buffer (ROB) module. In addition, when an error occurs in the speculation of the execution direction of the branch instruction, it is necessary to quickly restore to the state before the branch instruction was executed, including restoring the modifications to the register renaming mapping table. Among them, the program is a collection of program instructions arranged in a certain semantic order. The semantic order of program instructions is used to indicate the logical structure and control flow of the program.

[0033] In the related art, when a branch prediction error occurs, common methods for recovering modifications to the register renaming mapping table generally include: recovery based on a mapping table copy, recovery based on a reorder cache, and recovery after the branch instruction is submitted. Among them, the recovery method based on a mapping table copy requires providing a mapping table copy after each branch instruction is speculated to record the register renaming mapping table before the modification. This allows the system to quickly recover to the state before the branch instruction is processed based on the register renaming mapping table recorded in the mapping table copy when a branch prediction error occurs. However, this method has the technical problem of high device area cost. The recovery method based on the reorder cache and recovery method based on waiting for the branch instruction to be submitted have the technical problem of slow recovery speed.

[0034] In view of this, the present application provides a register renaming device. When a branch prediction error occurs and the number of program instructions on the incorrect speculation path meets certain conditions, the modification of the register renaming mapping table can be restored by combining the copy allocated to the branch instruction and the ROB module, thereby greatly improving the recovery speed.

[0035] Figure 1 Schematic diagram of the structure of the register renaming device provided by the embodiment of the present application. Figure 1 The register renaming device provided in the embodiment of the present application includes a control module 110 , a recovery module 120 , a mapping table cache module 130 and a reorder cache module 140 .

[0036] The mapping table cache module 130 is configured to store a first register mapping table, where the first register mapping table is used to indicate a first mapping relationship of program instructions in the reorder cache module 140 .

[0037] Exemplarily, the first mapping relationship is a mapping relationship between logical registers and physical registers corresponding to program instructions in the reorder cache module 140 .

[0038] The control module 110 is configured to write the program instructions into the reorder cache module 140 according to the semantic order of the program instructions and modify the first register mapping table according to the program instructions. If the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, the first register mapping table is recorded using a copy allocated for the branch instruction.

[0039] In some embodiments, a method for modifying a first register mapping table based on a program instruction includes, for example, determining a dependency relationship and required logical registers of the program instruction based on the program instruction; allocating physical registers to the logical registers required by the program instruction, provided that the dependency relationship is satisfied; and modifying the first register mapping table based on a mapping relationship between the logical registers required by the program instruction and the physical registers. The dependency relationship of the program instruction may be, for example, a read-after-write dependency.

[0040] Considering that when the program instruction includes a branch instruction, unexpected modifications may occur in the first register mapping table, such as when the speculated path of the branch instruction is incorrect, the register renaming mapping table may be modified based on the branch instruction, such as the modification of the first register mapping table. In view of this, if the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, the first register mapping table is recorded in a copy allocated to the branch instruction. When the speculated path of the branch instruction is incorrect, the first register mapping table can be quickly restored to the state before the branch instruction is executed based on the content recorded in the copy. The copy is, for example, any structure implemented by hardware and / or software that can be used to record the first register mapping table at different times.

[0041] In the case where the program instructions include branch instructions, the first register mapping table may be, for example, an SRT (speculative register table).

[0042] Considering that when there are a large number of branch instructions, the number of replicas allocated for each branch instruction will also be large, resulting in an increase in the area cost of the device. In view of this, in order to reduce the area cost of the device, the number of replicas can be limited to be less than the number of branch instructions, and new branch instructions can be allocated by overwriting the allocated replicas.

[0043] For example, the branch instruction includes a third branch instruction and multiple fourth branch instructions, and the time when the third branch instruction is written into the reorder cache module 140 is after the time when the multiple fourth branch instructions are written into the reorder cache module 140. In the case where the number of copies is less than the number of branch instructions, when allocating copies for the third branch instruction that enters the reorder cache module 140 later, there may be a situation where all copies have been allocated. In this case, the content of an allocated copy can be overwritten by the first register mapping table corresponding to the third branch instruction. Among them, the first register mapping table corresponding to the third branch instruction is the first register mapping table before the first register mapping table is modified according to the third branch instruction.

[0044] In some embodiments, when the branch instruction includes a third branch instruction and multiple fourth branch instructions, the time when the third branch instruction is written to the reorder cache module 140 is after the time when the multiple fourth branch instructions are written to the reorder cache module 140, and the copy includes multiple copies, the control module 110 is configured to record the first register mapping table by the copy allocated to the branch instruction before modifying the first register mapping table according to the branch instruction: before modifying the first register mapping table according to the third branch instruction, if multiple copies have been allocated to multiple fourth branch instructions, the copy allocated to one of the multiple fourth branch instructions will be reallocated to the third branch instruction, and the first register mapping table corresponding to the third branch instruction will be used to overwrite the content in the copy reallocated to the third branch instruction to record the first register mapping table corresponding to the third branch instruction.

[0045] Since the earlier the time of writing to the reorder cache module 140, the greater the possibility that the branch instruction will be executed, the greater the possibility that the copy corresponding to the branch instruction will be idle. In view of this, in order to improve the efficiency of resource management, when reallocating copies for the third branch instruction, a copy corresponding to a fourth branch instruction with a greater possibility of being executed among multiple fourth branch instructions can be selected for reallocation. For example, a fourth branch instruction from a suitable plurality of fourth branch instructions is selected by the time of writing to the reorder cache module 140. In some embodiments, the time interval between the third branch instruction and a fourth branch instruction from multiple fourth branch instructions being written to the reorder cache module 140 is greater than a second time threshold. The value of the second time threshold can be adjusted according to the actual application situation.

[0046] In some embodiments, a fourth branch instruction whose time interval between the time when the instruction is written into the reorder cache module 140 and the time when the third branch instruction is written into the reorder cache module 140 is greater than the second time threshold is the fourth branch instruction that is written into the reorder cache module 140 earliest among multiple fourth branch instructions.

[0047] The reorder cache module 140 is configured to manage program instructions according to a semantic order and record modifications to the first register mapping table based on the program instructions.

[0048] Optionally, managing program instructions in semantic order includes recording the execution status and execution results of the program instructions in semantic order, and managing the submission order of the program instructions in accordance with the semantic order of the program instructions to ensure program correctness. The submission order of the program instructions is, for example, the order in which the program instructions are submitted to the architectural state. The architectural state is, for example, the execution status of the program instructions visible to the program, indicating the final behavior and result of the program.

[0049] As described above, the mapping relationship in the register mapping table can be dynamically adjusted according to the execution status of the program instructions. When the program instructions in the reorder cache module 140 are executed, the first register mapping table can be modified according to the program instructions in the reorder cache module 140, and the first mapping relationship in the first register mapping table can be adjusted to map the logical registers required by the program instructions in the reorder cache module 140 to the physical registers to eliminate the data correlation between the program instructions in the reorder cache module 140, so that the program instructions in the reorder cache module 140 can be executed out of order and the parallelism of the program instructions in the reorder cache module 140 can be improved.

[0050] When out-of-order execution of program instructions is supported, to ensure program correctness, the program instructions can be written into the reorder cache module 140 according to their semantic order, so that the reorder cache module 140 can manage the program instructions according to the program's semantic order. For example, the reorder cache module 140 submits the program instructions in the reorder cache module 140 to the architectural state according to the program's semantic order, so that the program can complete its objectives according to the expected logical structure and control flow.

[0051] The recovery module 120 is configured to, if a speculation path of a branch instruction is incorrect and the replica allocated for the branch instruction is overwritten, recover the modification of the first register mapping table based on the branch instruction based on the replica and the reorder cache module 140 if the number of program instructions between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction is greater than the number of program instructions on the speculation path. The speculation path indicates a speculation on an execution path of program instructions following the branch instruction.

[0052] Illustratively, the program instruction pointed to by the retirement pointer of the re-order cache module 140 is used to indicate the program instruction in the re-order cache module 140 that is ready to be committed to the architectural state.

[0053] After the program instructions on the speculation path of the branch instruction are written into the reorder cache module 140, the first mapping relationship indicated by the first register mapping table includes the first mapping relationship corresponding to the program instructions between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction, and the first mapping relationship corresponding to the program instructions on the speculation path of the branch instruction.

[0054] When the speculation path of the branch instruction is wrong, the first register mapping table needs to be restored to the target state, that is, the modification of the first register mapping table based on the branch instruction is restored, so that the first mapping relationship indicated by the first register mapping table only includes the first mapping relationship corresponding to the program instruction between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction.

[0055] Considering that branch instructions occur at different times, the number of program instructions between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction may be different, resulting in different resource overheads required to restore the first register mapping table to the target state.

[0056] For example, when the number of program instructions between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction is greater than the number of program instructions on the speculation path, the first register mapping table recorded in the replica and the first register mapping table of the target state are more similar, and the resource overhead required to restore the modification to the first register mapping table based on the branch instruction through the replica and the reorder cache module 140 is smaller. When the number of program instructions between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction is less than the number of program instructions on the speculation path, because the similarity between the first register mapping table recorded in the replica and the first register mapping table of the target state is smaller, the modification to the first register mapping table based on the branch instruction can be restored through the second register mapping table and the reorder cache module 140, thereby reducing resource overhead.

[0057] In some embodiments, the mapping table cache module 130 is further configured to store a second register mapping table, and the recovery module 120 is further configured to: if a speculation path of a branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the reorder cache module 140 and the branch instruction in the reorder cache module 140 is less than the number of program instructions on the speculation path, recover the modification made to the first register mapping table based on the branch instruction according to the second register mapping table and the reorder cache module 140. The second register mapping table is used to indicate a second mapping relationship of program instructions submitted in the reorder cache module 140, and the second mapping relationship is used to indicate a mapping relationship between logical registers and physical registers corresponding to the program instructions submitted by the reorder cache module 140.

[0058] In some embodiments, the second register mapping table may be, for example, an ART (Architecture Register Table, a speculative register mapping table).

[0059] Furthermore, when there are multiple branch instructions, the similarity between the first register mapping table recorded in the replicas allocated to different branch instructions and the first register mapping table of the target state may vary. For example, the closer the time interval between the time when the branch instruction corresponding to the first register mapping table of the target state is written into the reorder cache module 140 and the time when the branch instruction corresponding to the first register mapping table of the target state is written into the reorder cache module 140, the higher the similarity between the first register mapping table recorded in the corresponding replica and the first register mapping table of the target state. In view of this, in order to reduce the resource overhead when restoring the first register mapping table, the first register mapping table recorded in the replica with a higher similarity to the first register mapping table of the target state may be selected for restoration.

[0060] In some embodiments, the branch instruction includes a first branch instruction and a second branch instruction, the first branch instruction is written to the reorder cache module 140 after the second branch instruction is written to the reorder cache module 140, and the time interval between the first branch instruction and the second branch instruction being written to the reorder cache module 140 is less than a first time threshold; the replica includes a first replica allocated for the first branch instruction and a second replica allocated for the second branch instruction; and when the speculation path of the branch instruction is incorrect and the replica allocated for the branch instruction is overwritten, the recovery module 120 is configured to, when recovering the modification to the first register mapping table based on the branch instruction based on the replica and the reorder cache module 140, recover the modification to the first register mapping table based on the first branch instruction based on the second replica and the reorder cache module 140 if the speculation path of the first branch instruction is incorrect and the first replica is overwritten. The value of the second time threshold can be adjusted according to actual application conditions.

[0061] The following will be combined Figure 2 Taking the number of copies being 2 as an example, the method of selecting different recovery methods according to the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction is explained.

[0062] Figure 2 Schematic diagram of the architecture of a register renaming device provided in an embodiment of the present application.

[0063] refer to Figure 2The register renaming device provided in the embodiment of the present application can write program instructions into the ROB module 210 according to the semantic order of the program instructions, and the retirement pointer 211 of the ROB module 210 can submit the executed program instructions to the architectural state according to the semantic order of the program instructions. Among them, ART221 can be used to record the second mapping relationship of the program instructions submitted in the ROB module 210, and SRT222 can be used to record the first mapping relationship of the program instructions in the ROB module 210. Among them, the second mapping relationship recorded in ART221 is different at different times, and the first mapping relationship recorded in SRT222 is also different at different times.

[0064] After the branch instruction branch-0 is written into the ROB module 210, the first mapping relationship between the program instruction pointed to by the retirement pointer 211 and the program instruction of branch-0 is recorded in SRT222, and the first copy 231 records the SRT222 corresponding to the branch instruction branch-0, that is, the SRT222 when branch-0 is written into the ROB module 210.

[0065] After the branch instruction branch-1 is written into the ROB module 210, the first mapping relationship between the program instruction pointed to by the retirement pointer 211 and the program instruction corresponding to branch-1 is recorded in SRT222, and the second copy 232 records the SRT222 corresponding to the branch instruction branch-1, that is, the SRT222 when branch-1 is written into the ROB module 210.

[0066] After branch instruction branch-2 is written to ROB module 210, SRT 222 records the first mapping relationship between the program instruction pointed to by retirement pointer 211 and the program instruction of branch-2. Since both the first copy and the second copy have been allocated, first copy 231 can be reallocated to branch instruction branch-2. SRT 222 corresponding to branch instruction branch-2 overwrites the content of first copy 231. First copy 231 then records SRT 222 corresponding to branch-2, i.e., SRT 222 of branch-2 when it was written to ROB module 210.

[0067] If the speculated path for branch-0 is incorrect, it is necessary to recover the modifications to SRT 222 based on branch-0. That is, to restore SRT 222 to the SRT 222 recorded by first copy 231 when branch-0 was written to ROB module 210. At this point, since SRT 222 recorded by first copy 231 when branch-0 was written to ROB module 210 has been overwritten, different recovery methods can be selected based on the number of program instructions between the program instruction pointed to by retirement pointer 211 and the branch instruction branch-0.

[0068] For example, when the number of program instructions between the program instruction pointed to by the retirement pointer 211 and the branch instruction branch-0 is greater than the number of program instructions between branch-0 and branch-1, the SRT222 corresponding to the branch instruction branch-1 recorded by the second copy 232 is more similar to the SRT222 recorded by the first copy 231 when branch-0 is written into the ROB module 210. The resource overhead required to recover the modification of SRT222 based on branch-0 according to the first copy 231 and the ROB module 210 is relatively small. Therefore, the modification of SRT222 based on branch-0 can be recovered according to the first copy 231 and the ROB module 210.

[0069] When the number of program instructions between the program instruction pointed to by the retirement pointer 211 and the branch instruction branch-0 is less than the number of program instructions between branch-0 and branch-1, the SRT222 corresponding to the branch instruction branch-1 recorded by the second copy 232 is less similar to the SRT222 recorded by the first copy 231 when branch-0 is written to the ROB module 210. The resource overhead required to restore the modification of SRT222 based on branch-0 according to the first copy 231 and the ROB module 210 is large. Therefore, the modification of SRT222 based on branch-0 can be restored according to ART221 and the ROB module 210.

[0070] The technical solution provided in the present application can, on the one hand, limit the number of copies used so that the number of copies is less than the number of branch instructions, which is beneficial to reducing the area cost of the device; on the other hand, when the number of copies is less than the number of branch instructions, when the speculation path of the branch instruction is wrong and the copy allocated to the branch instruction is overwritten, the copy and ROB module can be combined to recover the unexpected modifications in the first register mapping table, which is beneficial to improve the recovery speed of the unexpected modifications in the first register mapping table and reduce resource overhead.

[0071] In another possible implementation, the present application provides a method for maintaining a register mapping table. Figure 3 This is a flow chart of the method for maintaining the register mapping table provided by the embodiment of the present application. Figure 3 The method for maintaining a register mapping table provided in an embodiment of the present application includes the following steps.

[0072] Step S310 : writing the program instructions into the reorder buffer (ROB) module according to the semantic order of the program instructions, and modifying the first register mapping table according to the program instructions.

[0073] Step S320 : If the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, record the first register mapping table through a copy allocated for the branch instruction.

[0074] Step S330, in a case where the speculation path of the branch instruction is incorrect and the replica allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction in the ROB module is greater than the number of program instructions on the speculation path, the modification of the first register mapping table based on the branch instruction is restored according to the replica and the ROB module.

[0075] Among them, the first register mapping table is used to indicate the first mapping relationship of the program instructions in the ROB module, the ROB module is used to manage the program instructions in a semantic order and record the modifications to the first register mapping table based on the program instructions, the number of copies is less than the number of branch instructions, and the speculation path indicates the speculation of the execution path of the program instructions after the branch instruction.

[0076] In some possible embodiments, the branch instruction includes a first branch instruction and a second branch instruction, the time when the first branch instruction is written to the ROB module is after the time when the second branch instruction is written to the ROB module, and the time interval between the time when the first branch instruction and the second branch instruction are written to the ROB module is less than a first time threshold; the copy includes a first copy allocated for the first branch instruction and a second copy allocated for the second branch instruction; in the case that the speculation path of the branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, the modification of the first register mapping table based on the branch instruction is restored according to the copy and the ROB module, including: in the case that the speculation path of the first branch instruction is incorrect and the first copy is overwritten, the modification of the first register mapping table based on the first branch instruction is restored according to the second copy and the ROB module.

[0077] In some possible implementations, the method further includes: in a case where the speculation path of the branch instruction is incorrect and the copy allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction in the ROB module is less than the number of program instructions on the speculation path, recovering the modification of the first register mapping table based on the branch instruction according to the second register mapping table and the ROB module; wherein the second register mapping table is used to indicate a second mapping relationship of the program instructions submitted in the ROB module.

[0078] In some possible embodiments, the branch instruction includes a third branch instruction and multiple fourth branch instructions, the time when the third branch instruction is written to the ROB module is after the time when the multiple fourth branch instructions are written to the ROB module, and the copy includes multiple copies; before modifying the first register mapping table according to the branch instruction, the first register mapping table is recorded through the copy allocated to the branch instruction, including: before modifying the first register mapping table according to the third branch instruction, if the multiple copies have been allocated to multiple fourth branch instructions, the copy allocated to one of the multiple fourth branch instructions will be reallocated to the third branch instruction, and the content in the copy reallocated to the third branch instruction will be overwritten by the first register mapping table corresponding to the third branch instruction.

[0079] In some possible implementations, the time interval between writing the third branch instruction and a fourth branch instruction into the ROB module is greater than the second time threshold.

[0080] above Figure 3 The principle of the method for maintaining the register mapping table shown above can be referred to. Figure 1 The method embodiment for maintaining the register mapping table provided in the above embodiment and the register renaming device embodiment are of the same concept, and their specific implementation process can be found in the register renaming device embodiment.

[0081] In some other possible implementations, the present application also provides a processor. Figure 4 Schematic diagram of the structure of the processor provided in the embodiment of the present application. Figure 4 The processor provided by the embodiment of the present application includes a branch instruction prediction unit 410 and a register renaming device 420. The branch instruction prediction unit 410 is used to determine the speculation path of the branch instruction in the program instruction and send the speculation path to the register renaming device 420. The register renaming device 420 can be the above-mentioned Figure 1 Of course, the processor may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The processor may also include other components for implementing device functions, which will not be described in detail here.

[0082] In some other possible implementations, the present application further provides a computer-readable storage medium having stored thereon program instructions for maintaining a register mapping table, which, when executed by one or more processors, enables the processor to implement the above combination. Figure 3 The described method and steps of multiple embodiments thereof. The computer-readable storage medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0083] The present application also provides a computer program product comprising a computer program, which is executed by a processor to enable the computer to combine Figure 3 The method and steps of various embodiments thereof are described.

[0084] It should also be noted that the terms "first," "second," etc. (if any) in the specification and claims of the present application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way are interchangeable where appropriate so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0085] The term "and / or" in the embodiments of the present application is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B currently exist, and B exists alone.

[0086] The above description is only for the purpose of facilitating the understanding of the technical solution of this application by those skilled in the art and is not intended to limit this application. Any modification, equivalent replacement, improvement, etc. made within the principles of this application shall be included in the scope of protection of this application.

Claims

1. A register renaming device, characterized in that: The device comprises: A mapping table cache module is configured to store a first register mapping table, wherein the first register mapping table is used to indicate a first mapping relationship of program instructions in a reorder cache (ROB) module; a control module configured to write the program instructions into the ROB module in a semantic order of the program instructions and modify the first register mapping table according to the program instructions; if the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, record the first register mapping table through a copy allocated to the branch instruction; The ROB module is configured to manage the program instructions according to the semantic order and record modifications to the first register mapping table based on the program instructions; a recovery module configured to, if a speculation path of the branch instruction is erroneous and the replica allocated for the branch instruction is overwritten, recover the modification of the first register mapping table based on the branch instruction based on the replica and the ROB module if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction in the ROB module is greater than the number of program instructions on the speculation path; The number of the copies is smaller than the number of the branch instructions, and the speculation path indicates speculation on an execution path of the program instructions following the branch instruction.

2. The device according to claim 1, characterized in that The branch instruction includes a first branch instruction and a second branch instruction, the first branch instruction is written into the ROB module after the second branch instruction is written into the ROB module, and the time interval between the first branch instruction and the second branch instruction being written into the ROB module is less than a first time threshold; the copies include a first copy allocated for the first branch instruction and a second copy allocated for the second branch instruction; When the speculation path of the branch instruction is wrong and the replica allocated for the branch instruction is overwritten, the recovery module is configured to: In a case where the speculation path of the first branch instruction is wrong and the first copy is overwritten, the modification of the first register mapping table based on the first branch instruction is restored according to the second copy and the ROB module.

3. The device according to claim 1, characterized in that The recovery module is further configured to: In a case where a speculation path of the branch instruction is erroneous and the copy allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction in the ROB module is less than the number of program instructions on the speculation path, recovering the modification of the first register mapping table based on the branch instruction according to the second register mapping table and the ROB module; The second register mapping table is used to indicate a second mapping relationship of program instructions submitted in the ROB module.

4. The device according to claim 1, characterized in that The branch instruction includes a third branch instruction and a plurality of fourth branch instructions, the third branch instruction is written into the ROB module after the plurality of fourth branch instructions are written into the ROB module, and the copy includes a plurality of copies; Before modifying the first register mapping table according to the branch instruction, the control module is configured to: Before modifying the first register mapping table according to the third branch instruction, if the multiple copies have been allocated to the multiple fourth branch instructions, the copy allocated to one of the multiple fourth branch instructions will be reallocated to the third branch instruction, and the content in the copy reallocated to the third branch instruction will be overwritten by the first register mapping table corresponding to the third branch instruction.

5. The device according to claim 4, characterized in that The time interval between writing the third branch instruction and the fourth branch instruction into the ROB module is greater than a second time threshold.

6. A processor, characterized in that: The processor includes: a branch instruction prediction unit and a register renaming device, wherein the branch instruction prediction unit is used to determine the speculation path of the branch instruction in the program instruction and send the speculation path to the register renaming device, and the register renaming device is a device as described in any one of claims 1-5.

7. A method for maintaining a register mapping table, characterized in that: The method comprises: Writing the program instructions into a reorder buffer (ROB) module according to the semantic order of the program instructions, and modifying the first register mapping table according to the program instructions; If the program instruction is a branch instruction, before modifying the first register mapping table according to the branch instruction, recording the first register mapping table via a copy allocated for the branch instruction; In a case where a speculation path of the branch instruction is incorrect and the replica allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction in the ROB module is greater than the number of program instructions on the speculation path, recovering the modification of the first register mapping table based on the branch instruction according to the replica and the ROB module; The first register mapping table is used to indicate a first mapping relationship of program instructions in the ROB module, the ROB module is used to manage the program instructions in the semantic order and record modifications to the first register mapping table based on the program instructions, the number of copies is less than the number of branch instructions, and the speculation path indicates a speculation on an execution path of the program instructions after the branch instruction.

8. The method according to claim 7, characterized in that The branch instruction includes a first branch instruction and a second branch instruction, the first branch instruction is written into the ROB module after the second branch instruction is written into the ROB module, and a time interval between the first branch instruction and the second branch instruction being written into the ROB module is less than a first time threshold; the copies include a first copy allocated for the first branch instruction and a second copy allocated for the second branch instruction; In a case where the speculation path of the branch instruction is wrong and the copy allocated for the branch instruction is overwritten, the restoring the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module includes: In a case where the speculation path of the first branch instruction is wrong and the first copy is overwritten, the modification of the first register mapping table based on the first branch instruction is restored according to the second copy and the ROB module.

9. The method according to claim 7, characterized in that The method further comprises: In a case where a speculation path of the branch instruction is erroneous and the copy allocated for the branch instruction is overwritten, if the number of program instructions between the program instruction pointed to by the retirement pointer of the ROB module and the branch instruction in the ROB module is less than the number of program instructions on the speculation path, recovering the modification of the first register mapping table based on the branch instruction according to the second register mapping table and the ROB module; The second register mapping table is used to indicate a second mapping relationship of program instructions submitted in the ROB module.

10. The method according to claim 7, characterized in that The branch instruction includes a third branch instruction and a plurality of fourth branch instructions, the third branch instruction is written into the ROB module after the plurality of fourth branch instructions are written into the ROB module, and the copy includes a plurality of copies; Before modifying the first register mapping table according to the branch instruction, recording the first register mapping table through a copy allocated for the branch instruction includes: Before modifying the first register mapping table according to the third branch instruction, if the multiple copies have been allocated to the multiple fourth branch instructions, the copy allocated to one of the multiple fourth branch instructions will be reallocated to the third branch instruction, and the content in the copy reallocated to the third branch instruction will be overwritten by the first register mapping table corresponding to the third branch instruction.

11. The method according to claim 10, characterized in that The time interval between writing the third branch instruction and the fourth branch instruction into the ROB module is greater than a second time threshold.

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