Embedded multimedia card host device and loopback test method thereof
By using the loopback test control circuit and delay-locked loop bypass mechanism within the embedded multimedia card host device, the problems of cumbersome and high cost of existing testing methods are solved, the function of internal rapid verification of sending and receiving channels is realized, the test process is simplified and the cost is reduced.
Patent Information
- Application Number
- CN202510779579.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-10
- Publication Date
- 2025-09-26
AI Technical Summary
Existing testing methods for embedded multimedia card devices rely on external cards and frequency calibration, which is cumbersome and costly, and makes it difficult to complete functional verification of the sending and receiving channels internally.
The loopback test control circuit, transmitter circuit, receiver circuit, delay-locked loop (DLL) and demultiplexer (DM) in the embedded multimedia card host device are used to perform internal verification in the loopback test mode using pseudo-random sequence data and data selection signals. The bypass mechanism of the delay-locked loop is used to output the receiving clock signal, and the data is processed in combination with the DML to generate loopback test data and verify the results.
It realizes internal loopback testing without the need for external cards and frequency correction, simplifies the test process, reduces costs, and can quickly verify the functions of the sending and receiving channels, improving test efficiency and accuracy.
Smart Images
Figure CN120704962A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of embedded multimedia card host devices, and in particular to an embedded multimedia card host device and a loopback test method thereof. Background Art
[0002] Existing testing methods for embedded multimedia card devices often rely on external embedded multimedia cards or software operations to test data transmission, and require procedures such as frequency phase calibration to achieve stable data reception timing. However, this testing method is not only cumbersome but also increases testing costs and time. Furthermore, existing loopback testing often requires physical devices, making it difficult to verify the functionality of the transmit and receive channels within the embedded multimedia card device alone. Therefore, developing a loopback testing mechanism that does not require a physical card and does not involve software operations such as phase calibration has become an urgent technical challenge. Summary of the Invention
[0003] In some embodiments, one of the objectives of the present application, but not limited to, is to provide an embedded multimedia card host device and a loopback test method thereof that can perform a loopback test without using a bit correction mechanism, so as to improve the problems of the prior art.
[0004] In some embodiments, an embedded multimedia card host device includes a loopback test control circuit, a transmitter circuit, a receiver circuit, a delay locked loop (DLN), a first demultiplexer, and a second demultiplexer. The loopback test control circuit generates a first pseudo-random sequence data and a first data strobe signal corresponding to a first transmission mode in a loopback test mode. In the loopback test mode, the transmitter circuit samples the first pseudo-random sequence data according to a transmit clock signal to output a second pseudo-random sequence data, and samples the first data strobe signal according to the transmit clock signal to output a first clock signal. In the loopback test mode, the receiver circuit receives the second pseudo-random sequence data and the first clock signal from the transmitter circuit via an input / output interface, outputs the second pseudo-random sequence data as a third pseudo-random sequence data, and outputs the first clock signal as a second clock signal. In the loopback test mode, the delay locked loop (DLN) outputs the second clock signal as a receive clock signal using a bypass mechanism, wherein the DLN delays an external data strobe signal from an external device in the second transmission mode to generate the receive clock signal. In the loopback test mode, the demultiplexer processes the third pseudo-random sequence data according to the received clock signal to generate loopback test data. In the loopback test mode, the delay circuit delays the received clock signal to generate a third clock signal. In the loopback test mode, the loopback test control circuit also verifies the loopback test data according to the third clock signal to generate a flag signal indicating a loopback test result.
[0005] In some embodiments, a loopback test method is performed by an embedded multimedia card host device, the loopback test method comprising: in a loopback test mode, generating a first pseudo-random sequence data and a first data strobe signal corresponding to a first transmission mode; in the loopback test mode, sampling the first pseudo-random sequence data according to a transmission clock signal to output a second pseudo-random sequence data, and sampling the first data strobe signal according to the transmission clock signal to output a first clock signal; in the loopback test mode, receiving the second pseudo-random sequence data and the first clock signal via an input / output interface, outputting the second pseudo-random sequence data as a third pseudo-random sequence data, and outputting the first clock signal as a second clock signal. signal; in the loopback test mode, the second clock signal is output as a receiving clock signal via a delay locked loop in the embedded multimedia card host device in a bypass mechanism, wherein the delay locked loop delays an external data selection signal from an external device in a second transmission mode to generate the receiving clock signal; in the loopback test mode, the third pseudo-random sequence data is processed according to the receiving clock signal to generate a loopback test data; in the loopback test mode, the receiving clock signal is delayed to generate a third clock signal; and in the loopback test mode, the loopback test data is verified according to the third clock signal to generate a flag signal for indicating a loopback test result.
[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0008] Figure 1 A schematic diagram of an embedded multimedia card host device according to some embodiments of the present application is provided;
[0009] Figure 2A According to some embodiments of the present application Figure 1 Schematic diagram of the received data waveform, received clock signal and output data waveform of the embedded multimedia card host device in HS200 mode;
[0010] Figure 2B According to some embodiments of the present application Figure 1Schematic diagram of the received data waveform, received clock signal and output data waveform of the embedded multimedia card host device in HS400 mode;
[0011] Figure 3 A waveform diagram of the sampling timing adopted by the embedded multimedia card host device under a loopback test in some embodiments of the present application;
[0012] Figure 4 A schematic diagram of an embedded multimedia card host device according to some embodiments of the present application is provided;
[0013] Figure 5 According to some embodiments of the present application Figure 4 Operation waveform diagram of the embedded multimedia card host device in loopback test mode;
[0014] Figure 6 According to some embodiments of the present application Figure 4 Operation waveform diagram of the embedded multimedia card host device in the loopback test mode; and
[0015] Figure 7 A flowchart of a loopback test method according to some embodiments of the present application is drawn.
[0016] Reference numerals:
[0017] 100, 400: embedded multimedia card (eMMC) host device;
[0018] 101: external device;
[0019] 110, 410: phase-locked loop;
[0020] 120, 420: delay-locked loop;
[0021] 130, 430: transmitter circuit;
[0022] 131[0]~131
[11] ,431[8]:transmitter;
[0023] 140, 440: input and output interfaces;
[0024] 150, 450: receiver circuit;
[0025] 151[0]~151
[11] , 451[8]: receiver;
[0026] 152[0]~152
[11] , 460: demultiplexer;
[0027] 201: receiving data waveform;
[0028] 202, 203: output data waveform;
[0029] 405: loopback test control circuit;
[0030] 405A: clock generation circuit;
[0031] 405B: test data generating circuit;
[0032] 405C: data verification circuit;
[0033] 431: transmitter group;
[0034] 441: signal pad group;
[0035] 451: Receiver Group;
[0036] 470: Delay circuit;
[0037] 700: Loopback test method;
[0038] CK1, CK2, CK3, CKR: clock signals;
[0039] D0, D1: data;
[0040] DIN0, DIN1: input data;
[0041] DIN0[0]~DIN0
[11] , DIN1[0]~DIN1
[11] , DIN0[9,7:0], DIN1[9,7:0]: bits;
[0042] DO0, DO1: output data;
[0043] DO0[0]~DO0[1], DO1[0]~DO1[1]: bits;
[0044] DO0[9,7:0]: loop back test data;
[0045] DS1: data select signal;
[0046] DSO: external data strobe signal;
[0047] IO[0]~IO[1]: signal pad;
[0048] P, B, R, S, 7, PT: data value;
[0049] PT1, PT2, PT3: pseudo-random sequence data;
[0050] RXCK1, RXCK2: receive clock signal;
[0051] S710, S720, S730, S740, S750, S760, S770: operation;
[0052] SF, SF[0]~SF[7], SF[9]: flag signal;
[0053] TXCK: transmit clock signal. DETAILED DESCRIPTION
[0054] All terms used in this application have their ordinary meanings. The definitions of the aforementioned terms in commonly used dictionaries, including any examples of their use in this application, are intended to be illustrative only and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments described herein.
[0055] As used herein, the terms "coupled" or "connected" may refer to direct physical or electrical contact between two or more components, or indirect physical or electrical contact between two or more components, or to the mutual operation or action of two or more components. As used herein, the term "circuit" may refer to a device comprised of at least one transistor and / or at least one active or passive component connected in a specific manner to process signals.
[0056] Figure 1 A schematic diagram of an embedded Multimedia Card (eMMC) host device 100 is provided according to some embodiments of the present application. The eMMC host device 100 includes a phase-locked loop (PLL) 110 , a delay-locked loop (DLL) 120 , a transmitter circuit 130 , an input / output interface 140 , and a receiver circuit 150 .
[0057] Phase-locked loop (PLL) 110 provides a transmit clock signal TXCK and a receive clock signal RXCK1 corresponding to a first transmission mode. Delayed phase-locked loop (DLL) 120 performs corrections based on the clock signal CKR provided by PLL 110 and generates a receive clock signal RXCK2 corresponding to a second transmission mode. In some embodiments, the data rate of the first transmission mode is lower than the data rate of the second transmission mode. For example, the first transmission mode may be HS200 mode, and the second transmission mode may be HS400 mode, where the data rate of HS200 mode is approximately half that of HS400 mode.
[0058] The transmitter circuit 130 has a plurality of channels, which correspond to the plurality of bits DIN1[0] to DIN1
[11] of the input data DIN1 and the plurality of bits DIN0[0] to DIN0
[11] of the input data DIN0 in sequence. For example, the transmitter circuit 130 includes a plurality of transmitters 131[0] to 131
[11] , which correspond to the plurality of channels respectively. The transmitter 131[0] receives the bit DIN1[0] of the input data DIN1 and the bit DIN0[0] of the input data DIN0 according to the transmit clock signal TXCK. The transmitter 131[1] receives the bit DIN1[1] of the input data DIN1 and the bit DIN0[1] of the input data DIN0 according to the transmit clock signal TXCK. Similarly, it can be understood that the transmitter 131
[11] receives the bit DIN1
[11] of the input data DIN1 and the bit DIN0
[11] of the input data DIN0 according to the transmit clock signal TXCK.
[0059] The eMMC host device 100 can be coupled to the external device 101 via the input / output interface 140. The input / output interface 140 includes a plurality of signal pads IO[0] to IO
[11] , which respectively correspond to the aforementioned plurality of channels. For example, the signal pad IO[0] is coupled to the transmitter 131[0] to receive the bit DIN1[0] and the bit DIN0[0] sampled by the transmitter 131[0], and transmit these two bits to the external device 101. The signal pad IO[1] is coupled to the transmitter 131[1] to receive the bit DIN1[1] and the bit DIN0[1] sampled by the transmitter 131[1], and transmit these two bits to the external device 101. Similarly, it should be understood that the signal pad IO
[11] is coupled to the transmitter 131
[11] to receive the bit DIN1
[11] and the bit DIN0
[11] sampled by the transmitter 131
[11] , and transmit these two bits to the external device 101. Alternatively, the external device 101 may send data to the receiver circuit 150 via a plurality of signal pads IO[0] to IO
[11] .
[0060] In some embodiments, a plurality of bits DIN0[0] to DIN0[7] and a plurality of bits DIN1[0] to DIN1[7] are valid data, bit DIN0[8] and bit DIN1[8] are data strobe signals, bit DIN0[9] and bit DIN1[9] are command data, bit DIN0
[10] and bit DIN1
[10] are clock signals, and bit DIN0
[11] and bit DIN1
[11] are reset signals. In practical applications, a plurality of bits DIN0[0] to DIN0[7], a plurality of bits DIN1[0] to DIN1[7], and a plurality of bits DIN0[9] and DIN1[9] are main data for interaction between the eMMC host device 100 and the external device 101, and the data rate thereof can be up to 400 megabytes per second (MB / s) (i.e., the data rate of the aforementioned HS400 mode). The data select signal defined by bit DIN0[8] and bit DIN1[8] and the clock signal defined by bit DIN0
[10] and bit DIN1
[10] are sampling clock signals that the eMMC host device 100 and the external device 101 can provide to each other. For example, the eMMC host device 100 provides a sampling clock signal to the external device 101 via bit DIN0
[10] and bit DIN1
[10] , so that the external device 101 can receive data or commands transmitted from the eMMC host device 100 according to the sampling clock signal. Similarly, the eMMC host device 100 can receive data transmitted from the external device 101 according to the external data select signal DSO transmitted from the external device 101 via the signal pad IO[8] in the second transmission mode.
[0061] Similarly, the receiver circuit 150 has a plurality of channels, which correspond to a plurality of signal pads IO[0] to IO
[11] in sequence. For example, the receiver circuit 150 includes a plurality of receivers 151[0] to 151
[11] and a plurality of demultiplexers 152[0] to 152
[11] . The receiver 151[0] receives data provided by the external device 101 from the signal pad IO[0] and transmits the received data to the demultiplexer 152[0]. The receiver 151[1] receives data provided by the external device 101 from the signal pad IO[1] and transmits the received data to the demultiplexer 152[1]. Similarly, it can be seen that the receiver 151
[11] receives data provided by the external device 101 from the signal pad IO
[11] and transmits the received data to the demultiplexer 152
[11] .
[0062] In the first transmission mode, the demultiplexer 152[0] processes the data transmitted from the receiver 151[0] according to the receive clock signal RXCK1 (for example, deserializes it) to generate bit DO0[0] of the output data DO0 and bit DO1[0] of the output data DO1. In the first transmission mode, the demultiplexer 152[1] processes the data transmitted from the receiver 151[1] according to the receive clock signal RXCK1 to generate bit DO0[1] of the output data DO0 and bit DO1[1] of the output data DO1. Similarly, in the first transmission mode, the demultiplexer 152
[11] processes the data transmitted from the receiver 151
[11] according to the receive clock signal RXCK1 to generate bit DO0
[11] of the output data DO0 and bit DO1
[11] of the output data DO1. The receiver 151[8] can receive the external data selection signal DSO transmitted from the external device 101 from the signal pad IO[8] and transmit the external data selection signal DSO to the delay locked loop 120. The delay locked loop 120 can delay the external data strobe signal DSO to generate a receive clock signal RXCK2 corresponding to the second transmission mode. Thus, in the second transmission mode, the plurality of demultiplexers 152[0]-151
[11] can process the data received by the plurality of receivers 151[0]-151
[11] according to the receive clock signal RXCK2 to generate a plurality of bits DO0[0]-DO0
[11] of the output data DO0 and a plurality of bits DO1[0]-DO1
[11] of the output data DO1.
[0063] In other words, when operating in the first transmission mode, the receiver circuit 150 processes the received data mainly according to the receive clock signal RXCK1, wherein the receive clock signal RXCK1 is generated by the phase-locked loop 110. In contrast, when operating in the second transmission mode, the receiver circuit 150 processes the received data mainly according to the receive clock signal RXCK2, wherein the receive clock signal RXCK2 is generated according to the external data strobe signal DSO received from the external device 101 via the signal pad 10[8].
[0064] Figure 2A According to some embodiments of the present application Figure 1 FIG2 is a schematic diagram of the received data waveform, received clock signal RXCK1, and output data waveform of the eMMC host device 100 in HS200 mode. Received data waveform 201 may be the waveform of data sent by the external device 101 to multiple signal pads IO[0] to IO
[11] . Output data waveform 202 may be the waveform of output data DO0 read by the eMMC host device 100 based on the received clock signal RXCK1.
[0065] As previously described, in HS200 mode, the receive clock signal RXCK1 is generated by the phase-locked loop 110. Because the phase difference between the receive clock signal RXCK1 and the data transmitted by the external device 101 is unknown, the eMMC host device 100 can adjust the phase of the receive clock signal RXCK1 through a training procedure so that the rising edge of the receive clock signal RXCK1 aligns with the center of each data entry (e.g., data D0 and data D1) in the received data waveform 201, thereby ensuring that the receiver circuit 150 can correctly sample data D0 and data D1. In this way, the receiver circuit 150 can output data D0 and data D1 as output data DO0. In HS200 mode, the frequency of the receive clock signal RXCK1 is 200 MHz, and the data rate of the received data waveform 201 is 200 Mb / s.
[0066] Figure 2B According to some embodiments of the present application Figure 1 Figure 2 shows a schematic diagram of the received data waveform, received clock signal RXCK2, and output data waveform of the eMMC host device 100 in HS400 mode. In this example, output data waveform 202 may be the waveform of output data DO0 read by the eMMC host device 100 based on received clock signal RXCK2, and output data waveform 203 may be the waveform of output data DO1 read by the eMMC host device 100 based on received clock signal RXCK2. In HS400 mode, the frequency of received clock signal RXCK2 is 200 MHz, and the data rate of received data waveform 201 is increased to 400 Mb / s.
[0067] As previously described, in HS400 mode, receiver circuit 150 primarily processes received data based on receive clock signal RXCK2. DLL 120 calibrates receive clock signal RXCK2 so that its rising and falling edges align with the middle of data D0 and data D1 in data waveform 201, ensuring that receiver circuit 150 correctly samples data D0 and data D1. Consequently, receiver circuit 150 can output data D0 and data D1 as output data DO0.
[0068] Figure 3 The waveform diagram of the sampling timing used by the eMMC host device in some embodiments of the present application under the loopback test. According to the first transmission mode (such as HS200 mode) and the second transmission mode (such as HS400 mode) mentioned above, some embodiments of the present application propose an eMMC host device (such as Figure 4The eMMC host device 400 combines the data rate of the input data of the first transmission mode and the generation path of the sampling clock signal (e.g., the receive clock signal RXCK2) of the second transmission mode to perform a loopback test in a loopback test mode, thereby verifying whether the transceiver function inside the eMMC host device is correct.
[0069] As mentioned above, in the aforementioned HS200 mode, the data rate of the input data DIN0 (or input data DIN1) is set to 200Mhz. The eMMC host device can use the generation path of the sampling clock signal in the HS400 mode to configure a corresponding data selection signal DS1 (such as Figure 4 ), and the delay-locked loop 120 is set to a bypass mode to process the data strobe signal DS1 using a bypass mechanism, i.e., no additional delay processing or phase correction is performed on the data strobe signal DS1. For example, in this bypass mode, the delay-locked loop 120 can directly output the data strobe signal DS1 as the aforementioned receive clock signal RXCK2. This allows the rising edge of the clock signal to be naturally aligned with the center of each data entry in the input data DIN0 (or input data DIN1), ensuring accurate sampling. The detailed operation and configuration are described below.
[0070] Figure 4 A schematic diagram of an eMMC host device 400 according to some embodiments of the present application is provided. The eMMC host device 400 includes a loopback test control circuit 405, a phase-locked loop 410, a delay-locked loop 420, a transmitter circuit 430, an input / output interface 440, a receiver circuit 450, a demultiplexer 460, and a delay circuit 470.
[0071] In the loopback test mode, the loopback test control circuit 405 generates pseudo-random sequence data PT1 and a data strobe signal DS1 corresponding to the first transmission mode, and outputs the pseudo-random sequence data PT1 as input data DIN0 and input data DIN1, respectively. That is, in this example, each of the input data DIN0 and the input data DIN1 is identical to the pseudo-random sequence data PT1. In some embodiments, the pseudo-random sequence data PT1 may be, but is not limited to, pseudo-random binary sequence (PRBS) data.
[0072] The phase-locked loop 410 corresponds to Figure 1 The phase-locked loop 110 can be used to generate a transmit clock signal TXCK. The transmitter circuit 430 corresponds to Figure 1The transmitter circuit 130 samples the pseudo-random sequence data PT1 according to the transmission clock signal TXCK to output the pseudo-random sequence data PT2 in the loopback test mode, and samples the data selection signal DS1 according to the transmission clock signal TXCK to output the clock signal CK1.
[0073] For convenience and simplification, Figure 4 Only the circuit part related to the loopback test mode is shown. The detailed overall setting can be referred to Figure 1 In some embodiments, the transmitter circuit 430 includes a transmitter group 431 and a transmitter 431[8], and the transmitter group 431 corresponds to Figure 1 The multiple transmitters 131[0] to 131[7] and 131[9] in the transmitter group 431. The multiple transmitters (not shown) in the transmitter group 431 can sample the pseudo-random sequence PT1 according to the transmission clock signal TXCK (i.e., sample the multiple bits DIN0[0] to DIN0[7] and DIN0[9] (labeled as DIN0[9, 7:0]) in the input data DIN0 and the multiple bits DIN1[0] to DIN1[7] and DIN1[9] (labeled as DIN1[9, 7:0]) in the input data DIN1), and output the sampled data values as the pseudo-random sequence PT2 to the input-output interface 440. The transmitter 431[8] samples the data selection signal DS1 according to the transmission clock signal TXCK in the loopback test mode to output the clock signal CK1. Similarly, the input-output interface 440 includes a signal pad group 441 and a signal pad IO[8], wherein the signal pad group 441 corresponds to Figure 1 Multiple signal pads IO[0]~IO[7] and IO[9].
[0074] In some embodiments, the loopback test control circuit 405 sets the first specific bit and the second specific bit to complementary first logic values and second logic values in the loopback test mode to generate a data selection signal DS1, wherein the first specific bit and the second specific bit are transmitted to a signal pad in the input-output interface 440 for receiving an external data selection signal transmitted from the external device 101. For example, the loopback test control circuit 405 may set the bit DIN0[8] to a logic value of 0 and the bit DIN1[8] to a logic value of 1 in the loopback test mode to generate the data selection signal DS1. As previously described, the bit DIN0[8] and the bit DIN1[8] are transmitted to the signal pad IO[8] in the input-output interface 440, which is used to receive the external data selection signal DSO transmitted from the external device 101.
[0075] The receiver circuit 450 receives the pseudo-random sequence data PT2 and the receiver circuit 450 via the input / output interface 440 in the loopback test mode. For example, the receiver circuit 450 may include a receiver group 451 and a receiver 451[8], wherein the receiver group 451 corresponds to Figure 1 The plurality of receivers 151[0] to 151[7] and 151[9] can receive the pseudo-random sequence data PT2 and output it as pseudo-random sequence data PT3, and the receiver 451[8] can receive the clock signal CK1 and output it as the clock signal CK2. The delay locked loop 420 corresponds to Figure 1 The delay locked loop 120 is configured to output the clock signal CK1 as the received clock signal RXCK2 in the loopback test mode. That is, in the loopback test mode, the delay locked loop 420 can be configured to be in bypass mode, and output the clock signal CK1 as the received clock signal RXCK2 by a bypass mechanism, that is, the clock signal CK1 is directly output as the received clock signal RXCK2 without adjusting the clock signal CK1. In the loopback test mode, the demultiplexer 460 processes the pseudo-random sequence data PT3 according to the received clock signal RXCK2 (for example, by deserializing the pseudo-random sequence data PT3) to generate the loopback test data (for example, multiple bits DO0[0] to DO0[7] and DO[9] in the output data DO0; labeled as DO0[9,7:0]). The delay circuit 470 can delay the received clock signal RXCK2 in the loopback test mode to generate the clock signal CK3.
[0076] Thus, in the loopback test mode, the loopback test control circuit 405 can verify the loopback test data DO0[9,7:0] according to the clock signal CK3 to generate a flag signal SF that can be used to indicate the loopback test result. In some embodiments, the loopback test control circuit 405 can verify whether at least a portion of the bits in the loopback test data DO0[9,7:0] conform to a pseudo-random sequence according to the clock signal CK3 to verify the loopback test data DO0[9,7:0]. In other embodiments, the loopback test control circuit 405 can verify whether the loopback test data DO0[9,7:0] is identical to the pseudo-random sequence data PT1 according to the clock signal CK3 to verify the loopback test data DO0[9,7:0]. In some embodiments, the loopback test control circuit 405 can be implemented by multiple digital circuits, wherein the timing of the digital circuit portion (e.g., the data verification circuit 405C) used to verify the loopback data DO0[9,7:0] can be set by the clock signal CK3.
[0077] For example, if the loopback test control circuit 405 determines that the loopback test data DO0[9,7:0] is not pseudo-random sequence data or is different from the pseudo-random sequence data PT1, it indicates that the received loopback test data DO0[9,7:0] contains an error. In this case, the loopback test control circuit 405 can generate a flag signal SF with a logic value of 0 to indicate that the loopback test result is a failure. Alternatively, if the loopback test control circuit 405 determines that the loopback test data DO0[9,7:0] is pseudo-random sequence data or is the same as the pseudo-random sequence data PT1, it indicates that the received loopback test data DO0[9,7:0] is correct. In this case, the loopback test control circuit 405 can generate a flag signal SF with a logic value of 1 to indicate that the loopback test result is a failure.
[0078] In some embodiments, the loopback control circuit 405 includes a clock generation circuit 405A, a test data generation circuit 405B, and a data verification circuit 405C. The clock generation circuit 405A generates a data selection signal DS1 in the loopback test mode (for example, to set bits DIN0[8] and DIN1[8] to logic values 0 and 1, respectively). The test data generation circuit 405B generates pseudo-random sequence data PT1 in the loopback test mode. In some embodiments, the test data generation circuit 405B can be implemented by a pseudo-random sequence generator circuit. The data verification circuit 405C verifies the loopback test data DO0[9,7:0] according to the clock signal CK2 in the loopback test mode to generate a flag signal SF. In some embodiments, the data verification circuit 405C can be implemented by a pseudo-random sequence detector circuit.
[0079] In some embodiments, in the loopback test mode, the eMMC host device 400 may generate a sufficient number (for example, but not limited to, 50) of pseudo-random sequence data PT1 via the aforementioned multiple circuits, and collect a corresponding number of loopback test data DO0[9, 7:0] accordingly, and generate a flag signal SF for the corresponding number of loopback test data DO0[9, 7:0], thereby obtaining a more reliable loopback test result.
[0080] In some embodiments, the pseudo-random sequence data PT1 may be a PRBS7 sequence, which may include, in sequence, a pattern sign bit, a PRBS7 sequence, and a pattern end bit. The pattern sign bit may be low-speed identifier data, the PRBS7 sequence may be the main body of a high-speed (e.g., 200 Mbps) PRBS7 sequence, and the pattern end bit may be a logic 0. The above configuration of the pseudo-random sequence data PT1 is merely an example and is not intended to be limiting.
[0081] Figure 5 According to some embodiments of the present application Figure 4 The operation waveform of the eMMC host device in the loopback test mode. The input-output interface 440 may include multiple channels corresponding to multiple signal pads IO[0] to IO
[11] , and the receiver circuit 450 may receive the pseudo-random sequence data PT1 via multiple channels corresponding to multiple signal pads IO[0] to IO[7] and IO[9]. In some embodiments, the transmitter circuit 405 simultaneously transmits the pseudo-random sequence data PT2 to the receiver circuit 450 via all channels corresponding to multiple signal pads IO[0] to IO[7] and IO[9] in the loopback test mode. For example, Figure 5 As shown, the multiple bits DIN1[9, 7:0] of the input data DIN1 and the multiple bits DIN0[9, 7:0] of the input data DIN0 are set to multiple bits in the pseudo-random sequence data PT1, so that the multiple bits DIN1[9, 7:0] and the multiple bits DIN0[9, 7:0] have multiple data values P, R, B, S, 7 and PT, etc. of the pseudo-random sequence data PT1. Through sampling by the transmitter circuit 430, the pseudo-random sequence data PT2 (i.e., the signals on the multiple signal pads IO[0] to IO[7] and IO[9]) also sequentially have multiple data values P, R, B, S, 7 and PT. In this way, the transmitter circuit 430 can simultaneously transmit the pseudo-random sequence data PT2 to the receiver circuit 450 via all channels corresponding to the multiple signal pads IO[0] to IO[7] and IO[9].
[0082] Furthermore, if Figure 5 As shown, the loopback control circuit 405 can set the bit DIN1[8] to a logic value of 1 and the bit DIN0[8] to a logic value of 0, thereby defining the data selection signal DS1. The transmitter circuit 430 alternately samples the bit DIN0[8] and the bit DIN1[8] (the sampling result is equivalent to the data selection signal DS1), and the transmitter circuit 430 can generate a clock signal CK1 to the signal pad IO[8]. The phase of the clock signal CK1 is opposite to the phase of the transmission clock signal TXCK. In this way, it can be seen that the rising edge of the clock signal CK1 can naturally align with the middle of the multiple data values P, R, B, S, 7 and PT of the pseudo-random sequence data PT2.
[0083] Similarly, the receiver circuit 450 can receive the pseudo-random sequence data PT2 and output it as pseudo-random sequence data PT3 (the transmission delay of which is negligible, so the timing relationship can be the same as that of the pseudo-random sequence data PT2). Meanwhile, the receiver circuit 450 can receive the data strobe signal DS1 and output it as the clock signal CK1. The delay-locked loop 420 can operate in bypass mode and directly output the clock signal CK1 as the receive clock signal RXCK2, so that the demultiplexer 460 can deserialize the pseudo-random sequence data PT2 according to the receive clock signal RXCK2 to generate the loopback test data DO0[9,7:0]. Meanwhile, the delay circuit 470 can delay the receive clock signal RXCK2 to generate the clock signal CK3. In this way, the loopback test control circuit 405 can verify the loopback test data DO0[9,7:0] according to the clock signal CK3, thereby generating the flag signal SF. In this example, the loopback test control circuit 405 confirms that the loopback test data DO0[9,7:0] conforms to the pseudo-random sequence or is the same as the pseudo-random sequence data PT1, and thus generates a flag signal SF having a logic value of 1, indicating that the loopback test result is passed.
[0084] The above test is to perform loopback tests on multiple channels simultaneously to quickly confirm whether the transceiver functions between the multiple channels are operating correctly. In other embodiments, the eMMC host device 400 can also perform loopback tests on each channel to more accurately identify transmission channels that may have errors.
[0085] Figure 6 According to some embodiments of the present application Figure 4 In some embodiments, the transmitter circuit 430 transmits pseudo-random sequence data PT2 to the receiver circuit 450 in the loopback test mode in sequence via one of the multiple channels corresponding to the multiple signal pads IO[0] to IO[7] and IO[9]. For example, Figure 6As shown, the loopback test control circuit 405 can perform a loopback test on a channel-by-channel basis (i.e., bit-by-bit, from low bit to high bit). For example, in the loopback test mode, the loopback test control circuit 405 can set both bit DIN1[0] of the input data DIN1 and bit DIN0[0] of the input data DIN0 to the pseudo-random sequence data PT1, and set the remaining bits DIN1[1] to DIN1[7] and DIN1[9] of the input data DIN1 and the remaining bits DIN0[1] to DIN0[7] and DIN0[9] of the input data DIN0 to logic values 0. In this way, the transmitter circuit 430 will transmit the pseudo-random sequence data PT2 to the receiver circuit 450 via the channel corresponding to the signal pad IO[0] in the loopback test mode. Under this condition, the loopback test control circuit 405 can obtain the corresponding loopback test data DO0[0] (at this time, the other bits DO0[0] to DO0[7] and DO0[9] are logic values 0), and can verify the loopback test data DO0[0] according to the clock signal CK3 to generate the flag signal SF[0] corresponding to the first bit.
[0086] Then, in the loopback test mode, the loopback test control circuit 405 may set both the bit DIN1[1] of the input data DIN1 and the bit DIN0[1] of the input data DIN0 to a plurality of bits of the pseudo-random sequence data PT1 (denoted as a PBRS7 sample), and set the remaining bits DIN1[0], DIN1[2] to DIN1[7], and DIN1[9] of the input data DIN1 and the remaining bits DIN0[0], DIN0[2] to DIN0[7], and DIN0[9] of the input data DIN0 to logic values 0. In this way, the transmitter circuit 430 transmits the pseudo-random sequence data PT2 to the receiver circuit 450 via the channel corresponding to the signal pad IO[1] in the loopback test mode. Under this condition, the loopback test control circuit 405 can obtain the corresponding loopback test data DO0[1] (at this time, the other bits DO0[0], DO[2] to DO0[7] and DO0[9] are logic values 0), and can verify the loopback test data DO0[1] according to the clock signal CK3 to generate the flag signal SF[1] corresponding to the second bit.
[0087] Similarly, the loopback test control circuit 405 can provide pseudo-random sequence data PT1 channel by channel, so that the transmitter circuit 430 also transmits pseudo-random sequence data PT2 to the receiver circuit 450 in sequence channel by channel. In this way, the loopback test control circuit 405 can generate multiple flag signals SF[0]~SF[7] and SF[9] that can indicate the loopback test results channel by channel. Among the multiple flag signals SF[0]~SF[7] and SF[9], if a signal is a logic value 0, it means that the loopback test result of the channel is failed; conversely, if a signal is a logic value 1, it means that the loopback test result of the channel is passed. In the above manner, loopback testing can be performed quickly channel by channel. In addition, Figure 6 In the test mode, the generation method of the receiving clock signal RXCK2 and the clock signal CK3 is the same as Figure 5 The examples are the same, so I will not repeat them here.
[0088] Figure 7 A flow chart of a loopback test method 700 is drawn according to some embodiments of the present application. In some embodiments, the loopback test method 700 may be, but is not limited to, Figure 4 The eMMC host device 400 executes.
[0089] In operation S710, in a loopback test mode, first pseudo-random sequence data and a first data strobe signal corresponding to a first transmission mode are generated. In operation S720, in the loopback test mode, the first pseudo-random sequence data is sampled according to a transmit clock signal to output second pseudo-random sequence data, and the first data strobe signal is sampled according to the transmit clock signal to output a first clock signal. In operation S730, in the loopback test mode, the second pseudo-random sequence data and the first clock signal are received via an input / output interface, the second pseudo-random sequence data is output as third pseudo-random sequence data, and the first clock signal is output as a second clock signal. In operation S740, in the loopback test mode, the second clock signal is output as a receive clock signal via a delay-locked loop (DLL) in the embedded multimedia card host device using a bypass mechanism, wherein the DLL delays an external data strobe signal from an external device in the second transmission mode to generate the receive clock signal. In operation S750, in the loopback test mode, the third pseudo-random sequence data is processed according to the received clock signal to generate loopback test data. In operation S760, in the loopback test mode, the received clock signal is delayed to generate a third clock signal. In operation S770, in the loopback test mode, the loopback test data is verified according to the third clock signal to generate a flag signal indicating a loopback test result.
[0090] The description of the various operations of the loopback test method 700 can be found in the aforementioned embodiments and will not be repeated here. The aforementioned operations are merely examples and are not intended to limit the order in which they must be performed. Without departing from the operational manner and scope of the various embodiments of this application, the various operations of the loopback test method 700 may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, one or more operations of the loopback test method 700 may be performed simultaneously or partially simultaneously.
[0091] In summary, the eMMC host device and its loopback test method provided in some embodiments of the present application utilize the data rate of the first transmission mode and the sampling clock signal generation path of the second transmission mode to configure test input data and generate a sampling clock signal with an optimal sampling point. This allows loopback testing to be performed directly using the aforementioned test input data and sampling clock signal without requiring additional phase adjustment mechanisms, resulting in highly reliable test results. Furthermore, the aforementioned testing process does not require the insertion of a physical memory card, thereby enhancing testing convenience.
[0092] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit content of the present application. All such changes may fall within the scope of patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be based on the scope of the patent application defined in this specification.
Claims
1. An embedded multimedia card host device, characterized in that: include: A loopback test control circuit generates a first pseudo-random sequence data and a first data strobe signal corresponding to a first transmission mode in a loopback test mode; a transmitter circuit, in the loopback test mode, sampling the first pseudo-random sequence data according to a transmit clock signal to output a second pseudo-random sequence data, and sampling the first data strobe signal according to the transmit clock signal to output a first clock signal; a receiver circuit, in the loopback test mode, receiving the second pseudo-random sequence data and the first clock signal from the transmitter circuit via an input / output interface, outputting the second pseudo-random sequence data as a third pseudo-random sequence data, and outputting the first clock signal as a second clock signal; a delay locked loop (DLL) configured to output the second clock signal as a reception clock signal using a bypass mechanism in the loopback test mode, wherein the DLL delays an external data strobe signal from an external device in a second transmission mode to generate the reception clock signal; a demultiplexer, in the loopback test mode, processing the third pseudo-random sequence data according to the received clock signal to generate loopback test data; as well as a delay circuit, in the loopback test mode, delaying the received clock signal to generate a third clock signal; In the loopback test mode, the loopback test control circuit further verifies the loopback test data according to the third clock signal to generate a flag signal indicating a loopback test result.
2. The embedded multimedia card host device according to claim 1, wherein: A data rate of the first transmission mode is lower than a data rate of the second transmission mode.
3. The embedded multimedia card host device according to claim 1, wherein: The first transmission mode is the HS200 mode, and the second transmission mode is the HS400 mode.
4. The embedded multimedia card host device according to claim 1, wherein: The loopback test control circuit sets a first specific bit and a second specific bit to a complementary first logic value and a second logic value, respectively, in the loopback test mode to generate the first data selection signal, and the first specific bit and the second specific bit are transmitted to a signal pad in the input / output interface for receiving the external data selection signal.
5. The embedded multimedia card host device according to claim 1, wherein: The loopback test control circuit includes: a clock generating circuit, generating the first data strobe signal in the loopback test mode; a test data generating circuit, generating the first pseudo-random sequence data in the loopback test mode; and A data verification circuit verifies the loopback test data according to the third clock signal in the loopback test mode to generate the flag signal.
6. The embedded multimedia card host device according to claim 5, wherein: The data verification circuit confirms whether at least a portion of bits in the loopback test data conforms to a pseudo-random sequence according to the third clock signal, so as to verify the loopback test data.
7. The embedded multimedia card host device according to claim 5, wherein: The data verification circuit confirms whether the loopback test data is identical to the first pseudo-random sequence data according to the third clock signal, so as to verify the loopback test data.
8. The embedded multimedia card host device according to claim 1, wherein: The transmitter circuit simultaneously transmits the second pseudo-random sequence data to the receiver circuit via multiple channels in the loopback test mode.
9. The embedded multimedia card host device according to claim 1, wherein: The transmitter circuit sequentially transmits the second pseudo-random sequence data to the receiver circuit via one of a plurality of channels in the loopback test mode.
10. A loopback test method, characterized in that: Executed by an embedded multimedia card host device, the loopback test method includes: In a loopback test mode, generating a first pseudo-random sequence data and a first data strobe signal corresponding to a first transmission mode; In the loopback test mode, sampling the first pseudo-random sequence data according to a transmission clock signal to output a second pseudo-random sequence data, and sampling the first data strobe signal according to the transmission clock signal to output a first clock signal; In the loopback test mode, receiving the second pseudo-random sequence data and the first clock signal via an input / output interface, outputting the second pseudo-random sequence data as a third pseudo-random sequence data, and outputting the first clock signal as a second clock signal; In the loopback test mode, a delay locked loop (DLL) in the embedded multimedia card host device outputs the second clock signal as a receiving clock signal using a bypass mechanism, wherein the DLL delays an external data strobe signal from an external device in a second transmission mode to generate the receiving clock signal; In the loopback test mode, processing the third pseudo-random sequence data according to the received clock signal to generate a loopback test data; In the loopback test mode, delaying the received clock signal to generate a third clock signal; and In the loopback test mode, the loopback test data is verified according to the third clock signal to generate a flag signal indicating a loopback test result.