Method for fabricating inductor on integrated circuit chip and inductor increasing structure

Abstract

The application discloses a method for manufacturing an inductor on an integrated circuit chip and an inductor increasing structure of the integrated circuit chip manufactured by the method. The method is used for increasing an inductor between target metal layers of the integrated circuit chip. The method comprises the following steps: positioning target metal layers, which need to increase the inductor, in the integrated circuit chip, wherein the target metal layers comprise a first metal layer and a second metal layer; etching the integrated circuit chip to expose the first metal layer; etching the integrated circuit chip to expose the second metal layer; and forming a metal coil with the same inductance value as the target inductor on the surface of the integrated circuit chip, wherein the metal coil is electrically connected to the first metal layer and the second metal layer. The method for manufacturing the inductor on the integrated circuit chip and the inductor increasing structure of the integrated circuit chip can greatly improve the chip verification efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit chip technology, specifically relating to a method for fabricating inductors on integrated circuit chips and an inductance-enhancing structure for integrated circuit chips. Background Technology

[0002] With the development of integrated circuits, people's requirements for product quality and reliability are constantly increasing, making failure analysis increasingly important. Engineers may need to add inductors to the circuitry of integrated circuit chips during the failure verification process to achieve testing and verification requirements.

[0003] The current solution is to grow probe pads inside the chip and then connect external inductors by inserting probes on a probe station. This method is cumbersome and results in low chip verification efficiency for integrated circuits.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating inductors on integrated circuit chips and an inductance-enhancing structure for integrated circuit chips, which can greatly improve chip verification efficiency.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A method for fabricating an inductor on an integrated circuit chip, comprising adding an inductor between target metal layers of the integrated circuit chip, the method comprising:

[0008] In an integrated circuit chip, a target metal layer for which inductance needs to be increased is located, the target metal layer comprising a first metal layer and a second metal layer;

[0009] The integrated circuit chip is first etched to expose the first metal layer;

[0010] The integrated circuit chip is subjected to a second etching to expose the second metal layer;

[0011] A metal coil with the same inductance value as the target inductor is formed on the surface of the integrated circuit chip by chemical vapor deposition induced by a first ion beam, and the metal coil is electrically connected to the first metal layer and the second metal layer;

[0012] The first etching and / or the second etching are: preheated to 20°C-50°C and the angle between the jet direction of the ion beam and the upper surface of the sample to be etched is between 95°-105°, using a gallium ion source, accelerating voltage of 20-30keV, ion beam current of 50-300pA, and residence time of 5-15μs.

[0013] The first ion beam induced chemical vapor deposition is performed as follows: the temperature is preheated to 20°C-50°C and the angle between the jet direction of the ion beam and the upper surface of the sample to be etched is between 90°-95°. The source is gallium ion, the precursor gas is 5-20 sccm of hexacarbonyl tungsten W(CO)6, the accelerating voltage is 20-30 keV, the ion beam current is 15-30 pA, and the residence time is 5-10 μs.

[0014] In one or more embodiments of the present invention, while locating the target metal layer in the integrated circuit chip to which the inductance needs to be increased, the target region on the target metal layer is also located.

[0015] Performing a first etching on the integrated circuit chip to expose the first metal layer includes:

[0016] A first etching is performed on the target area corresponding to the first metal layer on the integrated circuit chip to expose the first metal layer;

[0017] Performing a second etching on the integrated circuit chip to expose the second metal layer includes:

[0018] A second etching is performed on the target area corresponding to the second metal layer on the integrated circuit chip to expose the second metal layer.

[0019] In one or more embodiments of the present invention, a metal material is deposited by chemical vapor deposition induced by a second ion beam in a target area corresponding to the first metal layer to form a first wire that electrically connects the first metal layer to the surface of the integrated circuit chip.

[0020] In the target area corresponding to the second metal layer, a third ion beam is used to induce chemical vapor deposition of metal material to form a second wire that electrically connects the second metal layer to the surface of the integrated circuit chip.

[0021] The metal coil is electrically connected to the first metal layer and the second metal layer through the first wire and the second wire;

[0022] The second or third ion beam induced chemical vapor deposition is performed as follows: the temperature is preheated to 20°C-50°C and the angle between the jet direction of the ion beam and the upper surface of the sample to be etched is between 88°-95°. The source is gallium ion, the precursor gas is 5-20 sccm of hexacarbonyl tungsten W(CO)6, the accelerating voltage is 20-30 keV, the ion beam current is 10-50 pA, and the residence time is 10-20 μs.

[0023] In one or more embodiments of the present invention, the size of the target region of the first metal layer is the same as the linewidth of the first conductor; and / or,

[0024] The line width of the first conductor is the same as the line width of the metal coil; and / or,

[0025] The size of the target area of ​​the second metal layer is the same as the linewidth of the second conductor; and / or,

[0026] The line width of the second conductor is the same as the line width of the metal coil.

[0027] In one or more embodiments of the present invention, the integrated circuit chip is etched using a focused ion beam; and / or,

[0028] The first wire is formed using a focused ion beam; and / or,

[0029] The second wire is formed using a focused ion beam; and / or,

[0030] The metal coil is formed using a focused ion beam.

[0031] In one or more embodiments of the present invention, prior to the step of forming a metal coil with the same inductance value as the target inductor on the surface of the integrated circuit chip, the method further includes:

[0032] The parameters of the metal coil to be formed are preset, including at least the cross-sectional area S of a single turn of the metal coil, the length I of the metal coil, the number of turns N of the metal coil, and the radius r of the metal coil;

[0033] According to the inductance calculation formula L=(k*μ0*μ s *N 2 *S) / I calculates the inductance value of the metal coil under preset parameters and compares it with the inductance value of the target inductance, where L is the inductance value; k is a coefficient; μ0 is the free permeability; μ s N represents the relative permeability of the magnetic core inside the coil. 2 S is the square of the number of turns in the coil; S is the cross-sectional area of ​​a single turn of the coil; I is the length of the coil.

[0034] Adjust the preset parameters of the metal coil to be formed based on the inductance value of the target inductor.

[0035] In one or more embodiments of the present invention, the coefficient k corresponds to the ratio of the radius r of the metal coil to the length I of the metal coil;

[0036] Based on the preset radius r and length I of the metal coil, the coefficient k is obtained by referring to the k value table;

[0037] The table of k values ​​is as follows:

[0038]

[0039] In one or more embodiments of the present invention, the metal coil is formed on the surface of the integrated circuit chip according to various parameters of the metal coil corresponding to the inductance value of the target inductor.

[0040] In one or more embodiments of the present invention, the metal coil is a planar helical winding.

[0041] In one or more embodiments of the present invention, the metal wire spacing value of the metal coil ranges from 0.06 μm to 1 μm.

[0042] In one or more embodiments of the present invention, the spacing of the metal wire gaps of the metal coils is alternately varied, wherein: the first spacing is 0.06μm-0.25μm; the second spacing is 0.6μm-0.95μm, and the spacing of the outermost gap satisfies the limitation of the second spacing.

[0043] In one or more embodiments of the present invention, the metal coil comprises a hollow coil; and / or,

[0044] The metal coil is made of tungsten.

[0045] In one or more embodiments of the present invention, after the step of forming the metal coil, the method further includes:

[0046] Assist gas is used to remove sputtered metal contaminants outside the metal coil. The removal process is as follows: preheating to 50℃-70℃, with the angle between the ion beam jet direction and the upper surface of the sample between 60°-85°, using a gallium ion source, accelerating voltage of 5-15keV, ion beam current of 1-10pA, residence time of 10-20μs, and xenon difluoride at 15-40sccm.

[0047] An inductor enhancement structure for an integrated circuit chip is fabricated using the aforementioned method for fabricating an inductor on an integrated circuit chip. The inductor enhancement structure includes a chip body and an inductor.

[0048] The chip body includes a first metal layer, a second metal layer, a first conductive line, and a second conductive line, and the chip body has a chip surface;

[0049] The inductor is located on the surface of the chip, and the inductor includes a metal coil;

[0050] The first wire extends from the surface of the chip to the first metal layer and is electrically connected to one end of both the first metal layer and the metal coil.

[0051] The second wire extends from the surface of the chip to the second metal layer and is electrically connected to the second metal layer and the other end of the metal coil, respectively.

[0052] Compared with the prior art, the method for fabricating inductors on integrated circuit chips and the inductance-enhancing structure of integrated circuit chips of the present invention achieve the purpose of increasing inductance in the circuit of integrated circuit chips by etching the integrated circuit chip to expose the target metal layer and forming a metal coil electrically connected to the target metal layer on the surface of the integrated circuit chip. After fabrication, it can be directly tested, which is more efficient and cost-effective. It eliminates the need to grow probe pads inside the chip and then connect external inductors by inserting pins with a probe station, thus solving the problem of low chip verification efficiency of existing integrated circuit chips. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a flowchart of a method for fabricating an inductor on an integrated circuit chip according to the present invention;

[0055] Figure 2 This is a schematic diagram of the inductance-enhancing structure of an integrated circuit chip in one embodiment of the present invention. Detailed Implementation

[0056] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0057] As mentioned in the background section, engineers often need to add inductors to the circuitry of integrated circuit chips during failure analysis and verification to meet verification requirements. Existing solutions involve growing probe pads at fixed points inside the chip and then connecting external inductors via a probe station. This approach is cumbersome, requiring multiple steps and more personnel; more steps mean longer processing times and a higher probability of chip damage during the process; more personnel also mean higher costs and lower efficiency.

[0058] To address the aforementioned technical problems, this invention proposes a method for fabricating inductors on integrated circuit chips and an inductance-enhancing structure for integrated circuit chips. This method allows inductors to be fabricated directly on integrated circuit chips without the need for long probe pads inside the integrated circuit chip and external inductors connected via probe stations. After the inductor is fabricated, it can be tested directly, resulting in higher efficiency and cost savings.

[0059] like Figure 1 As shown, the method for fabricating an inductor on an integrated circuit chip according to the present invention is used to add inductance between target metal layers of an integrated circuit chip. The method specifically includes the following steps:

[0060] S1, Locate the target metal layer in the integrated circuit chip where the inductance needs to be increased. The target metal layer includes a first metal layer and a second metal layer.

[0061] S2, etching the integrated circuit chip to expose the first metal layer.

[0062] S3, etching the integrated circuit chip to expose the second metal layer.

[0063] S4, a metal coil with the same inductance value as the target inductor is formed on the surface of the integrated circuit chip, and the metal coil is electrically connected to the first metal layer and the second metal layer.

[0064] During failure analysis and verification, engineers often need to add inductors to the circuitry of integrated circuit chips to meet verification requirements. Therefore, the first metal layer and the second metal layer in step S1 refer to the metal layer portion of the integrated circuit chip. Depending on the location where the inductor needs to be added, the locations represented by the first metal layer and the second metal layer will also be different. Thus, the specific locations and structures of the first metal layer and the second metal layer will change according to the specific failure analysis and verification situation, and are not specifically limited here.

[0065] Specifically, the target metal layer that needs to be increased inductance can be located in an integrated circuit chip using FIB (Focused Ion Beam) technology.

[0066] When adding an inductor to an integrated circuit chip, the two ends of the inductor need to be electrically connected to two different metal layers of the circuit in the integrated circuit chip, respectively, to add the inductor to the circuit. The first metal layer and the second metal layer represent the metal layers that need to be electrically connected to the two ends of the inductor when adding the inductor. Therefore, in steps S2 and S3, after locating the first metal layer and the second metal layer to which the inductor needs to be added, the integrated circuit chip can be etched using a focused ion beam device to remove the oxide layer, thereby exposing the first metal layer and the second metal layer, respectively.

[0067] Metal materials are deposited on the exposed first and second metal layers respectively, so that the first and second metal layers are electrically led out to the surface of the integrated circuit chip. Finally, a metal coil with the same inductance value as the target inductor is formed on the surface of the integrated circuit chip, and the two ends of the metal coil are respectively in contact with metal materials electrically connected to different target metal layers.

[0068] In an optional embodiment of the present invention, in the method for fabricating an inductor on an integrated circuit chip, while locating the target metal layer on the integrated circuit chip to which the inductance needs to be increased, a target region on the target metal layer can also be located simultaneously. This target region is the target window location on the integrated circuit chip where the inductance needs to be increased.

[0069] Understandably, as the inductance increases, it typically requires electrical connection to two locations within the integrated circuit chip's circuitry. Therefore, there are two target regions, corresponding to the first and second metal layers respectively. During subsequent etching, the layer structure located within the target region and above the target metal layer is completely etched away, exposing the target metal layer.

[0070] Specifically, a target region corresponding to the first metal layer is located using a focused ion beam (FIB) device. This FIB device is then used to etch the target region on the integrated circuit chip to remove the oxide layer, exposing the first metal layer within the target region. Next, a metal material is deposited within the target region corresponding to the first metal layer to form a first conductive line that electrically connects the first metal layer to the surface of the integrated circuit chip. The size of the target region of the first metal layer is the same as the linewidth of the first conductive line. By making the size of the target region of the first metal layer the same as the linewidth of the first conductive line, the etched target region is minimized, saving etching time, and sputtering contamination generated during the deposition of the first conductive line can be prevented from being difficult to clean in the gaps of the etched region.

[0071] Specifically, a target region corresponding to the second metal layer is located using a focused ion beam (FIB) device. This FIB device is then used to etch the target region on the integrated circuit chip to remove the oxide layer, exposing the second metal layer within the target region. Next, a metal material is deposited within the target region to form a second conductive line that electrically connects the second metal layer to the surface of the integrated circuit chip. The size of the target region of the second metal layer is the same as the linewidth of the second conductive line. By making the size of the target region of the second metal layer the same as the linewidth of the second conductive line, the etched target region is minimized, saving etching time, and sputtering contamination generated during the deposition of the second conductive line can be prevented from being difficult to clean in the gaps of the etched region.

[0072] The metal coil is electrically connected to the first metal layer and the second metal layer via a first conductor and a second conductor. To achieve good electrical contact, the linewidths of the first and second conductors are preferably the same as the linewidth of the first metal coil formed on the surface of the integrated circuit chip.

[0073] In step S4, in order to form a metal coil with the same inductance value as the target inductor on the surface of the integrated circuit chip, the parameters of the metal coil to be formed can be preset first. These parameters include at least the cross-sectional area S of a single turn of the metal coil, the length I of the metal coil, the number of turns N of the metal coil, and the radius r of the metal coil. According to the inductance calculation formula L=(k*μ0*μ s *N 2 *S) / I calculates the inductance value of the metal coil under preset parameters and compares it with the inductance value of the target inductance, where L is the inductance value; k is a coefficient; μ0 is the free permeability; μ s N represents the relative permeability of the magnetic core inside the coil. 2 S is the square of the number of turns in the coil; S is the cross-sectional area of ​​a single turn of the coil; I is the length of the coil; based on the inductance value of the target inductance, adjust the preset parameters of the metal coil to be formed, and finally obtain the parameters of the metal coil with the same inductance value as the target inductance.

[0074] Wherein, coefficient k corresponds to the ratio of the radius r of the metal coil to the length I of the metal coil. Specifically, coefficient k corresponds to 2r / I. The coefficient k is obtained by referring to the k-value table based on the preset radius r and length I of the metal coil; the k-value table is as follows:

[0075]

[0076] It is understandable that the cross-sectional area S of a single turn of a metal coil is the product of the width W and the thickness D of the metal coil. Therefore, the width W and thickness D of the metal coil can be obtained from the cross-sectional area S of a single turn of the metal coil.

[0077] Finally, based on the parameters of the metal coil corresponding to the inductance value of the target inductor, a metal coil electrically connecting the first and second wires is formed on the surface of the integrated circuit chip using a focused ion beam device.

[0078] Preferably, the metal coil may include an air-core coil, in which case the relative permeability μ of the magnetic core inside the coil is... s The value is 1.

[0079] In an optional embodiment of the present invention, at least one of the first conductor, the second conductor, and the metal coil is formed by deposition of W. W is tungsten, a chemical element. Tungsten has a high melting point, high hardness, high density, low price, and good corrosion resistance. Therefore, by depositing one or more of the first conductor, the second conductor, and the metal coil with W, the properties are more stable and the accuracy of failure analysis is higher after increasing the inductance.

[0080] The present invention discloses a method for fabricating inductors on integrated circuit chips. By etching the integrated circuit chip to expose the target metal layer, and forming a metal coil electrically connected to the target metal layer on the surface of the integrated circuit chip, the method achieves the purpose of adding inductors to the circuit of the integrated circuit chip. After fabrication, the inductors can be tested directly, which is more efficient and cost-effective. It eliminates the need to grow probe pads inside the chip and then connect external inductors by inserting pins with a probe station, thus solving the problem of low chip verification efficiency of existing integrated circuit chips.

[0081] Example 1:

[0082] This embodiment 1 provides a specific example of a method for fabricating an inductor on an integrated circuit chip. In this embodiment, the integrated circuit chip is manufactured using a 0.25μm aluminum process, comprising six metal layers. In this embodiment, it is required to create an inductor with an inductance value of approximately 20μH between two fourth and fifth metal layers spaced 100μm apart. In this case, the first metal layer is the fourth metal layer, and the second metal layer is the fifth metal layer, or vice versa. The specific operation steps are as follows:

[0083] The location where additional inductance needs to be added for the fourth metal layer was identified, corresponding to the target area of ​​the fourth metal layer. This target area was then etched using an ion beam to remove the oxide layer until the fourth metal layer was exposed. The size of the etched target area was consistent with the linewidth of the subsequently deposited first conductive line. The etching process involved preheating (to the surface to be etched or deposited) to 23°C, maintaining an angle of 98° between the ion beam jet direction and the upper surface of the sample to be etched, using a gallium ion source, accelerating voltage of 25 keV, ion beam current of 80 pA, and a residence time of 9 μs.

[0084] The first conductive line is deposited onto the surface of an integrated circuit chip on the etched fourth metal layer using focused ion beam induced chemical vapor deposition (FCVD). The FCVD process is as follows: preheating to 30°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 89° and the target temperature; using a gallium ion source; a precursor gas of 12 sccm of tungsten hexacarbonyl W(CO)6; an accelerating voltage of 23 keV; an ion beam current of 17 pA; and a residence time of 12 μs.

[0085] Similarly, the location where the fifth metal layer needs to be inducted was identified, i.e., the target area corresponding to the fifth metal layer. An ion beam was used to etch this target area, removing the oxide layer until the fifth metal layer was exposed. The size of the etched target area was consistent with the linewidth of the subsequently deposited second conductive line. This etching process was carried out under the following conditions: preheating to 23°C, with the angle between the ion beam jet direction and the upper surface of the sample to be etched within 98°, using a gallium ion source, accelerating voltage of 25 keV, ion beam current of 80 pA, and residence time of 9 μs.

[0086] A second conductive line is deposited onto the surface of an integrated circuit chip on the etched fifth metal layer using focused ion beam induced chemical vapor deposition (FCVD). The FCVD process is as follows: preheating to 30°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 89° and the target temperature; using a gallium ion source; a precursor gas of 12 sccm of tungsten hexacarbonyl W(CO)6; an accelerating voltage of 23 keV; an ion beam current of 17 pA; and a residence time of 12 μs.

[0087] Metal sputtering contamination in areas excluding the first and second conductive lines was completely removed using xenon difluoride, an auxiliary gas within the focused ion beam apparatus. The cleaning process was as follows: preheating to 58°C with the angle between the ion beam jet direction and the upper surface of the sample within 65°, using a gallium ion source, accelerating voltage of 12 keV, ion beam current of 6 pA, residence time of 13 μs, and xenon difluoride concentration of 19 sccm.

[0088] Based on the inductance value of the target inductor, the parameters of the metal coil to be formed are preset through ion beam-induced chemical vapor deposition, including the cross-sectional area S of a single turn of the metal coil, the length I of the metal coil, the number of turns N of the metal coil, and the radius r of the metal coil; according to the inductance calculation formula L=(k*μ0*μ s *N 2 *S) / I calculates the inductance value of the metal coil under preset parameters and compares it with the inductance value of the target inductance, where L is the inductance value; k is a coefficient; μ0 is the free permeability; μ s N represents the relative permeability of the magnetic core inside the coil. 2S is the square of the number of coil turns; S is the cross-sectional area of ​​a single coil turn; I is the length of the coil. Based on the inductance value of the target inductance, the preset parameters of the desired metal coil are adjusted to obtain the final parameters of the desired metal coil. The coefficient k corresponds to the ratio of the radius r of the metal coil to the length I of the metal coil. The coefficient k is obtained by referring to the k-value table based on the preset radius r and length I of the metal coil. The ion beam induced chemical vapor deposition is performed as follows: preheated to 32°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 94° and the target temperature; using a gallium ion source; the precursor gas is 18 sccm of tungsten hexacarbonyl W(CO)6; the accelerating voltage is 23 keV; the ion beam current is 19 pA; and the residence time is 7 μs.

[0089] In this embodiment, the inductance value is 20μH; the metal coil is an air-core coil, and the relative permeability μ of the magnetic core inside the coil is... s μ0 is 1; μ0 is 4π*10 -7 The preset length I of the metal coil is 200 μm, and the cross-sectional area S of a single turn of the metal coil is 4 μm. 2 The number of turns N is 3, and the radius r of the metal coil is 20μm; at this time, 2r / I is 2*20 / 200 = 0.2, and k is found to be 0.92 from the k-value table. According to the inductance calculation formula L = (k*μ0*μ) / (k*μ0 ... s *N 2 The inductance of the metal coil under the above parameters is calculated as *S) / I, which gives a value of 20 μH. Since the cross-sectional area S of a single turn of the metal coil is 4 μm... 2 Therefore, the width of the metal coil can be 4μm and the thickness can be 1μm.

[0090] A metal coil with the aforementioned parameters is deposited in a ring structure between the first and second conductors using a focused ion beam apparatus. Sputter contamination outside the deposited metal coil is removed using xenon difluoride, resulting in an inductance value of 20 μH.

[0091] Focused ion beam (FIB) etching parameters:

[0092] Ion source: using liquid gallium ions (Ga) + )source.

[0093] Acceleration voltage: Set to ensure sufficient energy to remove the passivation layer and dielectric material in the target area, while minimizing lateral etching (undercut).

[0094] Beam current: Selected based on etching accuracy and speed requirements. A smaller beam current is used to ensure high-precision positioning when locating the target area (i.e., the subsequent conductor deposition site). During the actual etching stage, a medium beam current range can be selected based on the oxide layer thickness and target size (here, the same as the conductor linewidth).

[0095] Focused ion beam (FIB) induced chemical vapor deposition (FIB-CVD) parameters (deposition wires and coils): Precursor gas: tungsten-based precursor gas is selected, usually hexacarbonyl tungsten [W(CO)6].

[0096] Gas injection: W(CO)6 is delivered to the deposition sites on the chip surface using a precise and controllable gas injection system (GIS). Localized gas injection is performed for wire and coil deposition areas, and the flow rate needs to be optimized to achieve the required deposition rate and purity.

[0097] Depositional conditions:

[0098] Beam current: Precisely control the deposition beam current to match the desired linewidth. Too low a beam current results in slow deposition, while too high a beam current may cause sputtering to exceed deposition.

[0099] Ion beam scanning mode and patterning: The scanning path and residence time of the ion beam are controlled by software, and tungsten metal is deposited according to the preset shape (straight-through structure of the wire, ring structure of the metal coil) and size (line width, coil spacing, number of turns).

[0100] Metal sputtering contamination removal mechanisms and processes:

[0101] Sources of contaminants: During FIB etching and CVD deposition, especially when using high beam currents or when subjected to ion beam irradiation in unwanted areas, metals (mainly gallium ions Ga from the ion source) are inevitably generated. + Physical sputtering contaminants (such as tungsten) deposit on non-target areas of the chip surface. Removal method: Focused ion beam assisted gas etching (IB-GAE).

[0102] Purging gas: Xenon difluoride (XeF2) is specifically selected as the auxiliary reaction gas. XeF2 has excellent isotropic etching properties and is highly reactive to sputtered metallic contaminants such as tungsten and aluminum alloys.

[0103] Removal Mechanism: XeF2 gas is selectively introduced into areas with sputter contamination. Low-energy FIB scanning of the contaminated area is then performed. The ion beam itself provides energy and breaks the chemical bonds of the contaminants; more importantly, it catalyzes the decomposition of adsorbed XeF2 molecules on the surface, generating highly reactive fluorine atoms (F) and fluorine radicals. These reactive fluorine species react violently with sputtered tungsten contaminants (W): W(s) + 6F(g) → WF6(g), producing volatile tungsten hexafluoride (WF6). Residual gallium ions and other contaminants may also be removed by reacting with fluorine to form volatile compounds (such as GaF3).

[0104] Removal effect: The generated volatile fluorides (WF6, GaF3, etc.) are quickly removed by the vacuum system.

[0105] Selective Removal: The key to this process lies in its high selectivity. Under optimized conditions (primarily by controlling the FIB energy / beam current and XeF2 exposure dose / time), the XeF2 / IB-GAE etch rate for contaminants is significantly higher than its etch rate for underlying silicon, silicon dioxide, and other chip body materials. By precisely controlling the localized injection of the auxiliary gas and the point scanning of the FIB, sputtered contaminants around metal coils, near wires, and other critical areas can be effectively removed without damaging the fabricated metal wires, coils, or the underlying original chip structure and metal layers.

[0106] Cleaning steps applied:

[0107] As described in Example 1, immediately after depositing the first and second conductors connecting the target metal layer, IB-GAE technology (XeF2 gas) is used to remove sputter contaminants generated in the vicinity of the area during the deposition of these conductors. Similarly, after the FIB deposition of the metal coil with the target inductance value is completed, IB-GAE technology is again used to remove (on-coil / off-coil) metal sputter contaminants generated during the coil deposition process that are located outside the coil area.

[0108] Additional details regarding material selection: Tungsten (W) was selected for the deposited metal wires (first wire, second wire) and metal coil in this embodiment, primarily because:

[0109] The FIB-CVD deposition process using tungsten hexacarbonyl [W(CO)6] as a precursor is stable and mature, and can provide good process controllability and repeatability.

[0110] Tungsten has a low resistivity (approximately 5.6 μΩ·cm), making it suitable for introducing inductance in verification circuits.

[0111] Tungsten has a high melting point, good chemical stability (especially in subsequent testing environments), and excellent resistance to electromigration, ensuring the reliability of the fabricated inductor structure during the verification process.

[0112] The aforementioned IB-GAE removal process is highly effective against tungsten sputtering contaminants.

[0113] The present invention also provides an inductance-enhancing structure for an integrated circuit chip fabricated using the above-described method for fabricating inductors on an integrated circuit chip.

[0114] like Figure 2As shown, the inductance-enhancing structure of this integrated circuit chip includes a chip body 10 and an inductor 20. The chip body 10 includes a first metal layer 11, a second metal layer 12, a first conductive line 13, and a second conductive line 14. The chip body 10 has a chip surface 10a. The inductor 20 is located on the chip surface 10a and includes a metal coil 21.

[0115] The chip surface 10a is the surface to be processed, and an inductor 20 can be fabricated on this surface. A first channel 15 and a second channel 16 are provided within the chip body 10. The first channel 15 extends from the chip surface 10a to the surface of the first metal layer 11. The second channel 16 extends from the chip surface 10a to the surface of the second metal layer 12.

[0116] The first conductor 13 is located within the first channel 15, with one end electrically connected to the first metal layer 11 and the other end electrically connected to one end of the metal coil 21. The second conductor 14 is located within the second channel 16, with one end electrically connected to the second metal layer 12 and the other end electrically connected to the other end of the metal coil 21.

[0117] The first channel 15 and the second channel 16 can be formed by etching. The first wire 13 enables the first metal layer 11 and the metal coil 21 to be electrically connected, and the second wire 14 enables the second metal layer 12 and the metal coil 21 to be electrically connected, thereby achieving the purpose of increasing the inductance 20 between the first metal layer 11 and the second metal layer 12.

[0118] The above structure enables the addition of inductor 20 to the circuit of an integrated circuit chip without the need to grow probe pads inside the chip and then connect the inductor 20 externally by inserting pins through a probe station. This solves the problem that the existing method of adding inductor 20 to the circuit of an integrated circuit chip is cumbersome and results in low chip verification efficiency.

[0119] In one embodiment, the length I, width W, thickness D, radius r, and number of turns N of the metal coil 21 can be obtained by preset adjustment using the inductance calculation formula and the corresponding k-value table. The inductance calculation formula is L=(k*μ0*μ s *N 2 *S) / I, where L is the inductance; k is the coefficient; and μ0 is the free permeability, with a value of 4π*10⁻⁶. -7 μ s N represents the relative permeability of the magnetic core inside the coil. 2 S is the square of the number of coil turns; S is the cross-sectional area of ​​a single coil turn; I is the length of the coil. The required inductance value of the additional inductance 20 varies depending on the test conditions, and no specific limit is given here.

[0120] The sample test results of Example 1 show that the inductor accuracy deviation is less than ±2%, and the frequency response range reaches 100MHz, which is significantly better than the ±10% deviation of the traditional probe point external inductor (limited by parasitic effects and external impedance). In terms of efficiency, the time from positioning to deposition completion is only 2 hours, which is more than 60% more efficient than the traditional method (which requires multiple steps such as growth probe pad, probe station calibration, and external inductor adjustment, usually taking 8-12 hours); and no additional equipment (such as probe station) is required, reducing the cost by about 50%, and the chip damage rate is reduced from the traditional 10% to less than 1%.

[0121] Example 2

[0122] The difference between this embodiment and Embodiment 1 lies only in the following: The location where additional inductance needs to be added to the fourth metal layer is identified, corresponding to the target area of ​​the fourth metal layer. An ion beam is used to etch this target area, removing the oxide layer until the fourth metal layer is exposed. The size of the etched target area is consistent with the linewidth of the subsequently deposited first conductive line. This etching process is performed with preheating to 50°C and the angle between the ion beam jet direction and the upper surface of the sample to be etched being within 105°. A gallium ion source is used, with an accelerating voltage of 20 keV, an ion beam current of 50 pA, and a residence time of 15 μs.

[0123] The first conductive line is deposited onto the surface of an integrated circuit chip on the etched fourth metal layer using focused ion beam induced chemical vapor deposition (FCVD). The FCVD process is as follows: preheating to 50°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched being between 95° and 50°; using a gallium ion source; a precursor gas of 20 sccm of tungsten hexacarbonyl W(CO)6; an accelerating voltage of 30 keV; an ion beam current of 50 pA; and a residence time of 10 μs.

[0124] Similarly, the location where the fifth metal layer needs to be inducted is identified, i.e., the target area corresponding to the fifth metal layer. An ion beam is used to etch this target area, removing the oxide layer until the fifth metal layer is exposed. The size of the etched target area is consistent with the linewidth of the subsequently deposited second conductive line. This etching process is performed with preheating to 20°C and the angle between the ion beam jet direction and the upper surface of the sample to be etched being within 105°, using a gallium ion source, an accelerating voltage of 20 keV, an ion beam current of 300 pA, and a residence time of 15 μs.

[0125] A second conductive line is deposited onto the surface of an integrated circuit chip on the etched fifth metal layer using focused ion beam induced chemical vapor deposition (FCVD). The FCVD process is as follows: preheating to 20°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched being between 95° and 20°; using a gallium ion source; employing a precursor gas of 5 sccm of hexacarbonyl tungsten (W(CO)6); setting an accelerating voltage of 30 keV; an ion beam current of 10 pA; and a residence time of 20 μs.

[0126] Metal sputtering contamination in areas excluding the first and second conductors was completely removed using xenon difluoride, an auxiliary gas within the focused ion beam apparatus. The cleaning process was as follows: preheating to 70°C with the angle between the ion beam jet direction and the upper surface of the sample between 85° and the target surface; gallium ion source; accelerating voltage 5 keV; ion beam current 10 pA; residence time 20 μs; xenon difluoride 40 sccm.

[0127] Based on the inductance value of the target inductor, the parameters of the metal coil to be formed are preset through ion beam-induced chemical vapor deposition, including the cross-sectional area S of a single turn of the metal coil, the length I of the metal coil, the number of turns N of the metal coil, and the radius r of the metal coil; according to the inductance calculation formula L=(k*μ0*μ s *N 2 *S) / I calculates the inductance value of the metal coil under preset parameters and compares it with the inductance value of the target inductance, where L is the inductance value; k is a coefficient; μ0 is the free permeability; μ s N represents the relative permeability of the magnetic core inside the coil. 2 S is the square of the number of coil turns; S is the cross-sectional area of ​​a single coil turn; I is the length of the coil. Based on the inductance value of the target inductance, the preset parameters of the desired metal coil are adjusted to obtain the final parameters of the desired metal coil. The coefficient k corresponds to the ratio of the radius r of the metal coil to the length I of the metal coil. The coefficient k is obtained by referring to the k-value table based on the preset radius r and length I of the metal coil. The ion beam induced chemical vapor deposition is performed as follows: preheated to 50°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 95° and the target temperature; using a gallium ion source; the precursor gas is 5 sccm of tungsten hexacarbonyl W(CO)6; the accelerating voltage is 30 keV; the ion beam current is 30 pA; and the residence time is 5 μs.

[0128] The sample test results of Example 2 show that the inductor accuracy deviation is less than ±3%, and the frequency response range reaches 100MHz, which is significantly better than the ±15% deviation of the traditional probe point external inductor (limited by parasitic effects and external impedance). In terms of efficiency, the time from positioning to deposition completion is only 3 hours, which is more than 50% more efficient than the traditional method (which requires multiple steps such as growth probe pad, probe station calibration, and external inductor adjustment, usually taking 8-12 hours); and no additional equipment (such as probe station) is required, reducing the cost by about 40%, and the chip damage rate is reduced from the traditional 10% to less than 2%.

[0129] Example 3

[0130] The only difference between this embodiment and Embodiment 1 is that the location where additional inductance needs to be added to the fourth metal layer is identified, i.e., the target area corresponding to the fourth metal layer. An ion beam is used to etch this target area, removing the oxide layer until the fourth metal layer is exposed. The size of the etched target area is consistent with the linewidth of the subsequently deposited first conductive line. This etching process is performed with preheating to 20°C and the angle between the ion beam jet direction and the upper surface of the sample to be etched being within 95°. A gallium ion source is used, with an accelerating voltage of 30 keV, an ion beam current of 300 pA, and a residence time of 5 μs.

[0131] The first conductive line is deposited onto the surface of an integrated circuit chip on the etched fourth metal layer using focused ion beam induced chemical vapor deposition (FCVD). The FCVD process is as follows: preheating to 20°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 88° and the target temperature; using a gallium ion source; a precursor gas of 5 sccm of tungsten hexacarbonyl W(CO)6; an accelerating voltage of 20 keV; an ion beam current of 10 pA; and a residence time of 20 μs.

[0132] Similarly, the location where the fifth metal layer needs to be inducted is identified, i.e., the target area corresponding to the fifth metal layer. An ion beam is used to etch this target area, removing the oxide layer until the fifth metal layer is exposed. The size of the etched target area is consistent with the linewidth of the subsequently deposited second conductive line. This etching process is performed with preheating to 20°C and the angle between the ion beam jet direction and the upper surface of the sample to be etched being within 95°, using a gallium ion source, an accelerating voltage of 30 keV, an ion beam current of 50 pA, and a residence time of 5 μs.

[0133] A second conductive line is deposited onto the surface of an integrated circuit chip on the etched fifth metal layer using focused ion beam induced chemical vapor deposition (FCVD). The FCVD process is as follows: preheating to 50°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 88° and the target temperature; using a gallium ion source; a precursor gas of 20 sccm of tungsten hexacarbonyl W(CO)6; an accelerating voltage of 20 keV; an ion beam current of 50 pA; and a residence time of 10 μs.

[0134] Metal sputtering contamination in areas excluding the first and second conductors was completely removed using xenon difluoride, an auxiliary gas within the focused ion beam apparatus. The cleaning process was as follows: preheating to 50°C with the angle between the ion beam jet direction and the upper surface of the sample within 60°, using a gallium ion source, accelerating voltage of 15 keV, ion beam current of 1 pA, residence time of 10 μs, and xenon difluoride at 15 sccm.

[0135] Based on the inductance value of the target inductor, the parameters of the metal coil to be formed are preset through ion beam-induced chemical vapor deposition, including the cross-sectional area S of a single turn of the metal coil, the length I of the metal coil, the number of turns N of the metal coil, and the radius r of the metal coil; according to the inductance calculation formula L=(k*μ0*μ s *N 2 *S) / I calculates the inductance value of the metal coil under preset parameters and compares it with the inductance value of the target inductance, where L is the inductance value; k is a coefficient; μ0 is the free permeability; μ s N represents the relative permeability of the magnetic core inside the coil. 2 S is the square of the number of coil turns; S is the cross-sectional area of ​​a single coil turn; I is the length of the coil. Based on the inductance value of the target inductance, the preset parameters of the desired metal coil are adjusted to obtain the final parameters of the desired metal coil. The coefficient k corresponds to the ratio of the radius r of the metal coil to the length I of the metal coil. The coefficient k is obtained by referring to the k-value table based on the preset radius r and length I of the metal coil. The ion beam induced chemical vapor deposition is performed as follows: preheated to 20°C with the angle between the ion beam jet direction and the upper surface of the sample to be etched between 90° and the target temperature; using a gallium ion source; the precursor gas is 20 sccm of tungsten hexacarbonyl W(CO)6; the accelerating voltage is 20 keV; the ion beam current is 15 pA; and the residence time is 10 μs.

[0136] The sample test results in Example 3 show that the inductance accuracy deviation is less than ±2.5%, and the frequency response range reaches 100MHz, which is significantly better than the ±13% deviation of the traditional probe point external inductor (limited by parasitic effects and external impedance). In terms of efficiency, the time from positioning to deposition completion is only 2.5 hours, which is more than 55% more efficient than the traditional method (which requires multiple steps such as growth probe pad, probe station calibration, and external inductor adjustment, usually taking 8-12 hours); and no additional equipment (such as probestation) is required, reducing the cost by about 45%, and the chip damage rate is reduced from the traditional 10% to less than 2%.

[0137] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0138] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for fabricating an inductor on an integrated circuit chip, used to add inductance between target metal layers of an integrated circuit chip, characterized in that, The method includes: In an integrated circuit chip, the target metal layer for which inductance needs to be increased is located, and the target metal layer includes a first metal layer and a second metal layer; The integrated circuit chip is first etched to expose the first metal layer; The integrated circuit chip is subjected to a second etching to expose the second metal layer; A metal coil with the same inductance value as the target inductor is formed on the surface of the integrated circuit chip by chemical vapor deposition induced by a first ion beam, and the metal coil is electrically connected to the first metal layer and the second metal layer; The first etching and / or the second etching are: preheated to 20°C-50°C and the angle between the jet direction of the ion beam and the upper surface of the sample to be etched is between 95°-105°, using a gallium ion source, accelerating voltage of 20-30keV, ion beam current of 50-300pA, and residence time of 5-15μs. The first ion beam induced chemical vapor deposition is performed as follows: the temperature is preheated to 20°C-50°C and the angle between the jet direction of the ion beam and the upper surface of the sample to be etched is between 90°-95°. The source is gallium ion, the precursor gas is 5-20 sccm of hexacarbonyl tungsten W(CO)6, the accelerating voltage is 20-30 keV, the ion beam current is 15-30 pA, and the residence time is 5-10 μs.

2. The method for fabricating an inductor on an integrated circuit chip according to claim 1, characterized in that, In the integrated circuit chip, the target metal layer for which inductance needs to be increased is located, and the target area on the target metal layer is also located. Performing a first etching on the integrated circuit chip to expose the first metal layer includes: A first etching is performed on the target area corresponding to the first metal layer on the integrated circuit chip to expose the first metal layer; Performing a second etching on the integrated circuit chip to expose the second metal layer includes: A second etching is performed on the target area corresponding to the second metal layer on the integrated circuit chip to expose the second metal layer.

3. The method for fabricating an inductor on an integrated circuit chip according to claim 2, characterized in that, In the target area corresponding to the first metal layer, a metal material is deposited by chemical vapor deposition induced by a second ion beam to form a first wire that electrically connects the first metal layer to the surface of the integrated circuit chip. In the target area corresponding to the second metal layer, a third ion beam is used to induce chemical vapor deposition of metal material to form a second wire that electrically connects the second metal layer to the surface of the integrated circuit chip. The metal coil is electrically connected to the first metal layer and the second metal layer through the first wire and the second wire; The second or third ion beam induced chemical vapor deposition is performed as follows: the temperature is preheated to 20°C-50°C and the angle between the jet direction of the ion beam and the upper surface of the sample to be etched is between 88°-95°. The source is gallium ion, the precursor gas is 5-20 sccm of hexacarbonyl tungsten W(CO)6, the accelerating voltage is 20-30 keV, the ion beam current is 10-50 pA, and the residence time is 10-20 μs.

4. The method for fabricating an inductor on an integrated circuit chip according to claim 3, characterized in that, The size of the target area of ​​the first metal layer is the same as the linewidth of the first conductor; and / or, The line width of the first conductor is the same as the line width of the metal coil; and / or, The size of the target area of ​​the second metal layer is the same as the linewidth of the second conductor; and / or, The line width of the second conductor is the same as the line width of the metal coil.

5. The method for fabricating an inductor on an integrated circuit chip according to claim 1, characterized in that, Before the step of forming a metal coil with the same inductance value as the target inductor on the surface of the integrated circuit chip, the method further includes: The parameters of the metal coil to be formed are preset, including at least the cross-sectional area S of a single turn of the metal coil, the length I of the metal coil, the number of turns N of the metal coil, and the radius r of the metal coil; According to the inductance calculation formula L=(k*μ0*μ s *N 2 *S) / I calculates the inductance value of the metal coil under preset parameters and compares it with the inductance value of the target inductance, where L is the inductance value; k is a coefficient; μ0 is the free permeability; μ s N represents the relative permeability of the magnetic core inside the coil. 2 S is the square of the number of turns in the coil; S is the cross-sectional area of ​​a single turn of the coil; I is the length of the coil. Adjust the preset parameters of the metal coil to be formed based on the inductance value of the target inductor.

6. The method for fabricating an inductor on an integrated circuit chip according to claim 5, characterized in that, The coefficient k corresponds to the ratio of the radius r of the metal coil to the length I of the metal coil; Based on the preset radius r and length I of the metal coil, the coefficient k is obtained by referring to the k value table; The table of k values ​​is as follows: 。 7. The method for fabricating an inductor on an integrated circuit chip according to claim 4, characterized in that, The metal coil is a planar helical winding.

8. The method for fabricating an inductor on an integrated circuit chip according to claim 7, characterized in that, The metal wire spacing of the metal coil ranges from 0.06 μm to 1 μm.

9. The method for fabricating an inductor on an integrated circuit chip according to claim 8, characterized in that, The spacing between the metal wires of the metal coil is alternating, wherein: the first spacing is 0.06μm-0.25μm; the second spacing is 0.6μm-0.95μm, and the spacing of the outermost gap satisfies the limitation of the second spacing.

10. The method for fabricating an inductor on an integrated circuit chip according to claim 1, characterized in that, After the step of forming the metal coil, the following steps are also included: Assist gas is used to remove sputtered metal contaminants outside the metal coil.

11. An inductance-enhancing structure for an integrated circuit chip, characterized in that, The inductor is manufactured by the method of fabricating an inductor on an integrated circuit chip according to any one of claims 1-10, wherein the inductor-enhancing structure comprises a chip body and an inductor; The chip body includes a first metal layer, a second metal layer, a first conductive line, and a second conductive line, and the chip body has a chip surface; The inductor is located on the surface of the chip, and the inductor includes a metal coil; The first wire extends from the surface of the chip to the first metal layer and is electrically connected to one end of both the first metal layer and the metal coil. The second wire extends from the surface of the chip to the second metal layer and is electrically connected to the second metal layer and the other end of the metal coil, respectively.

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