A design method of ultra-thin 3D inductor passive device

Abstract

This invention discloses a design method for an ultra-thin 3D inductor passive device, comprising the following steps: S1, selecting a suitable substrate; S2, setting a bottom metal on the bottom of the substrate, metallizing a hole on the bottom metal, and extending the metallized hole through the substrate and above the upper surface of the substrate; S3, setting a trace metal on the metallized hole, and fixing the trace metal to the upper surface of the substrate; S4, setting bumps on the trace metal, and setting a top metal on the top of the bumps, forming a passive device with 3D inductance. This invention reduces the aspect ratio of the 3D inductor while ensuring inductance performance, lowers the processing difficulty, and reduces the thickness of the manufactured product and the overall thickness of the packaging module.

Description

Technical Field

[0001] This invention relates to the field of passive device technology, and in particular to a design method for an ultra-thin 3D inductor passive device. Background Technology

[0002] 3D spiral inductors offer a higher Q value compared to planar inductors, and passive devices using 3D inductor structures can achieve better electrical performance. However, a key challenge in the fabrication of 3D inductors is achieving a large aspect ratio. Furthermore, excessive hole depth can result in a thicker product, hindering integration and modularization. Summary of the Invention

[0003] Therefore, it is necessary to provide a design method for ultra-thin 3D passive inductors to address the aforementioned technical problems.

[0004] A design method for an ultra-thin 3D passive inductor includes the following steps:

[0005] S1. Select a suitable substrate;

[0006] S2. A bottom metal is provided at the bottom of the substrate, a metallization hole is provided on the bottom metal, and the top of the metallization hole extends through the substrate and out above the upper surface of the substrate.

[0007] S3. Provide wiring metal on the cylindrical winding and fix the wiring metal to the upper surface of the substrate;

[0008] S4. A bump is provided on the trace metal, and a top metal is provided on the top of the bump to form a passive device with 3D inductance.

[0009] In one embodiment, the bottom metal is a plurality of strip-shaped first metal sheets arranged in parallel, and the column winding is disposed at both ends of the first metal sheets.

[0010] In one embodiment, step S3 includes:

[0011] S31. An independent trace metal is provided on the top of each of the metallized holes;

[0012] S32. Fix each of the said trace metals to the upper surface of the substrate.

[0013] In one embodiment, step S4 includes: the top metal includes a plurality of second metal sheets, each of the second metal sheets being sequentially and alternately connected to the upper surfaces of two adjacent protrusions.

[0014] In one embodiment, the distance between the bottom metal and the trace metal is less than 270 μm.

[0015] The above-mentioned design method for ultra-thin 3D inductor passive devices increases the inductance by setting trace metal on the upper surface of the substrate and adjusting the trace metal. Furthermore, by adding bumps on the top of the trace metal, the thickness of the substrate can be reduced by utilizing the height of the bumps. Thus, this invention reduces the aspect ratio of the 3D inductor while ensuring inductance performance, reduces the processing difficulty, and reduces the thickness of the manufactured product and the overall thickness of the packaging module. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a 3D passive inductor in the prior art;

[0018] Figure 2 This is a cross-sectional view of a 3D passive inductor in the prior art;

[0019] Figure 3 This is a schematic diagram of the structure of the ultra-thin 3D passive inductor of the present invention;

[0020] Figure 4 This is a cross-sectional view of the ultra-thin 3D passive inductor of the present invention;

[0021] Figure 5 This is a comparison chart of the Q values ​​of the ultra-thin 3D passive inductor of the present invention and the 3D passive inductor in the prior art;

[0022] Figure 6 This is a comparison diagram of the self-resonant frequencies of the ultra-thin 3D passive inductor of the present invention and the 3D passive inductor in the prior art;

[0023] Figure 7 This is a comparison chart of the Q values ​​of the ultra-thin 3D passive inductor and the 2D inductor of the present invention;

[0024] Figure 8 This is a comparison diagram of the self-resonant frequencies of the ultra-thin 3D passive inductor and the 2D inductor of the present invention. Detailed Implementation

[0025] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0026] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0028] The main concept of this invention lies in the following: In IPD (In-Metal Diode) processes, the thickness of the Nitride dielectric in MIM (Metal Injection Molding) capacitors is typically around 0.1µm. The processing accuracy of this dielectric thickness directly affects the capacitance (dielectric thickness is inversely proportional to capacitance). A 10nm thickness deviation affects the capacitance by 10%. Therefore, in actual production, the capacitance density generally exhibits a normal distribution. As the frequency selection requirements of filters become increasingly stringent, higher demands are placed on the processing accuracy of capacitors. Passive devices fabricated using this method can be fine-tuned by adjusting the height of the bump and the traces on the substrate.

[0029] Taking an LC resonator as an example, if the capacitance density is low during IPD processing, the resonant frequency of the LC resonator will be higher. Therefore, the inductance can be increased by increasing the height of the bump (the height of the bump for Φ80um is generally 50-90um), thereby increasing the inner diameter of the 3D inductor, or by adjusting the metal traces on the substrate to increase the inductance. In this way, the desired resonant frequency can be obtained.

[0030] See Figure 3-4 As shown, an embodiment of the present invention provides a design method for an ultra-thin 3D passive inductor, comprising the following steps:

[0031] S1. Select a suitable substrate 1; substrate 1 can be high-resistivity silicon, glass, gallium arsenide, etc.

[0032] S2. A bottom metal 2 is provided at the bottom of the substrate 1, a metallized hole 3 is provided on the bottom metal 2, and the top of the metallized hole 3 passes through the substrate 1 and extends above the upper surface of the substrate 1.

[0033] S3. A trace metal 4 is provided on the metallized hole 3, and the trace metal 4 is fixed on the upper surface of the substrate 1.

[0034] S4. A bump 5 is provided on the trace metal 4, and a top metal 6 is provided on the top of the bump 5 to form a passive device with 3D inductance.

[0035] The above-mentioned ultra-thin 3D inductor passive device design method involves setting metal 4 on the upper surface of substrate 1, adding bumps 5 on the top of metal 4, and using the height of bumps 5 to reduce the thickness of substrate 1. Then, a 3D inductor is formed by setting trace metal 6 on the surface of the packaging substrate, and the inductance can be finely adjusted by adjusting the trace metal 6. Thus, the present invention reduces the diameter-to-depth ratio of the metallized hole 3 while ensuring inductor performance, reduces the processing difficulty, and reduces the product thickness and the overall thickness of the packaging module.

[0036] In one embodiment of the present invention, the bottom metal 2 consists of a plurality of strip-shaped first metal sheets arranged in parallel, and the column winding 3 is disposed at both ends of the first metal sheets. In this embodiment, the first metal sheet is flat, and the plurality of strip-shaped first metal sheets are evenly spaced.

[0037] In one embodiment of the present invention, step S3 includes:

[0038] S31. An independent trace metal 4 is provided on the top of each of the metallized holes 3;

[0039] S32. Fix each of the said trace metals 4 to the upper surface of the substrate 1. In one embodiment of the present invention, step S4 includes: the top metal 6 includes a plurality of second metal sheets, each of the second metal sheets being sequentially and alternately connected to the upper surfaces of two adjacent bumps 5. In this way, the connection and conduction of the bottom metal 2, the metallized hole 3 and the top metal 6 can be realized, ensuring the normal operation of the 3D inductor.

[0040] In this embodiment, by changing the shape or thickness of the top metal 6, the inductance of the 3D inductor can be finely adjusted, thereby correcting the deviation of the resonant frequency caused by the processing precision of the MIM Cap.

[0041] In one embodiment of the present invention, the distance between the bottom metal 2 and the trace metal 4 is less than 270 μm. In this embodiment, the top metal 6 is located on the surface of the packaging substrate and needs to be sealed with the packaging substrate through bumps 5 to form a 3D inductor. This reduces the original thickness of the 3D inductor from 350 μm to 270 μm without changing its performance. In this embodiment, by utilizing the height of the bumps 5, the surface trace metal 4 of the substrate 1, and the top metal 6 on the bumps 5, the size of the chip is effectively reduced and the difficulty of the 3D inductor processing is reduced while ensuring electrical performance, thus contributing to the overall thickness reduction of the module.

[0042] See Figure 7-8 As shown, in terms of electrical performance comparison, the Q value and SRF (self-resonant frequency) of the 3D inductor of the present invention are significantly better than those of the 2D inductor.

[0043] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0044] The embodiments described above merely illustrate several implementations of the present invention and should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for designing an ultra-thin 3D inductive passive device, characterized in that, Includes the following steps: S1. Select a suitable substrate; S2. A bottom metal is provided at the bottom of the substrate, a metallization hole is provided on the bottom metal, and the top of the metallization hole extends through the substrate and out above the upper surface of the substrate. S3. Provide wiring metal on the metallized hole and fix the wiring metal to the upper surface of the substrate; S4. A bump is provided on the trace metal, and a top metal is provided on the top of the bump to form a passive device with 3D inductance; Step S3 includes: S31. An independent trace metal is provided on the top of each of the metallized holes; S32. Fix each of the said trace metals to the upper surface of the substrate; Step S4 includes: the top metal includes a plurality of second metal sheets, each of the second metal sheets being sequentially and alternately connected to the upper surfaces of two adjacent protrusions.

2. The ultra-thin 3D inductor passive device design method of claim 1, wherein, The bottom metal consists of multiple strip-shaped first metal sheets arranged side by side, and the metallization holes are located at both ends of the first metal sheets.

3. The ultra-thin 3D inductor passive device design method of claim 1, wherein, The distance between the bottom metal and the wiring metal is less than 270 μm.

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