High-precision wide-range current detection circuit

Abstract

The invention discloses a high-precision wide-range current detection circuit which comprises an auxiliary operational amplifier A1, a power tube MP, a sampling tube MS, a PMOS tube PM1, a resistor RS, an operational amplifier OP, a charge pump, a driving module and a high-voltage domain floating ground module. An auxiliary operational amplifier A1 is adopted to forcibly balance source electrode potentials of a sampling tube MS and a power tube MP, source electrode voltage of the power tube MP is sampled and fed back to an operational amplifier OP, an output signal of the operational amplifier OP is transmitted to a driving module, power supply of the driving module is provided by a charge pump and a high-voltage domain floating ground module, and the driving module dynamically adjusts grid electrode voltage of the power tube MP. According to the invention, the mismatch of the operational amplifier input end is reduced, and the current detection proportion precision is kept within the maximum-to-minimum range of the load current.

Description

Technical Field

[0001] The present invention relates to a detection circuit, in particular to a high-precision wide-range current detection circuit, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] High-side switches have become indispensable circuit components in modern electronic systems. Widely used in automotive electronics as critical load switches, these devices also integrate protection features for applications such as hot-swap control and surge suppression. In load-switch applications, precise output current detection and accurate power regulation are crucial to ensure real-time monitoring of load status and accurate transmission of diagnostic information to the main control unit.

[0003] Existing technologies mainly use two types of technical solutions to realize the current detection function of high-side switches: The first technical solution uses a resistive detection architecture (such as Figure 6 This solution acquires a current signal by connecting a sense resistor, Rsense, in series with the load circuit. Leveraging the op amp's virtual short characteristic, the sense voltage is transmitted to the ROUT resistor, generating a sampled current proportional to the load current in the PMOS transistor. Its value is (Rsense × ILoad) / R1. This current signal is ultimately converted to a measurable voltage signal, Vout, via the output resistor, Rout.

[0004] Although this detection architecture has the advantage of simple design, it has obvious limitations in engineering practice: on the one hand, when the system needs to handle high current loads, considerable power loss will be generated in the detection resistor; on the other hand, this solution places strict requirements on the resistance accuracy and temperature stability of the detection resistor.

[0005] The second technical solution is based on SenseFET technology (such as Figure 7 This solution cleverly utilizes the ratio of the number of chips in the main power unit and the sampling unit in the power tube. The closed-loop control formed by the operational amplifier ensures that the source potential of the two is consistent, thereby obtaining a sampling current that is strictly proportional to the main circuit current. When the MOS operates in the linear region, it is equivalent to a linear resistor. Its resistance Ron is proportional to the mobility μ and the gate oxide layer capacitance. , aspect ratio and overdrive voltage Vgs-Vth are as follows:

[0006] Then the theoretical formula can be derived:

[0007] According to the above theoretical analysis, in order to improve the current proportional accuracy K, it is necessary to minimize However, this solution has an inherent flaw: when the load current is very low, It approaches zero, making it difficult for the system to maintain accurate current detection ratio accuracy in the highest to lowest load current range (from high current to low current). Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a high-precision wide-range current detection circuit, which reduces the mismatch of the operational amplifier input terminal and maintains the current detection ratio accuracy within the range from the highest to the lowest load current.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is: A high-precision, wide-range current detection circuit includes an auxiliary operational amplifier A1, a power tube MP, a sampling tube MS, a PMOS tube PM1, a resistor RS, an operational amplifier OP, a charge pump Charge Pump, a driver module DRIVER, and a high-voltage domain floating ground module HVSS_Gen. The drain of the power tube MP, the drain of the sampling tube MS, and the charge pump Charge The input terminal of Pump is connected to the power supply voltage VCC. The gate of the power transistor MP is connected to the gate of the sampling transistor MS and the output terminal of the driver module DRIVER. The source of the power transistor MP is connected to the non-inverting input terminal of the auxiliary operational amplifier A1, the load LOAD, and the inverting input terminal of the operational amplifier OP to generate an output voltage OUT. The source of the sampling transistor MS is connected to the inverting input terminal of the auxiliary operational amplifier A1 and the source of the PMOS transistor PM1. The output terminal of the auxiliary operational amplifier A1 is connected to the gate of the PMOS transistor PM1. The drain of the PMOS transistor PM1 is connected to one end of the resistor RS to generate a voltage signal VSENS. The other end of the resistor RS is grounded. The non-inverting input terminal of the operational amplifier OP is connected to the reference voltage VREF. The output terminal of the operational amplifier OP is connected to the input terminal of the driver module DRIVER. The output terminal of the charge pump Charge Pump is connected to the high-voltage terminal of the driver module DRIVER to generate a voltage signal VCP. The output terminal of the high-voltage domain floating ground module HVSS_Gen is connected to the low-voltage terminal of the driver module DRIVER to generate a voltage signal HVSS.

[0010] Furthermore, the auxiliary operational amplifier A1 includes a main transconductance amplifier Gm1, a transimpedance amplifier R, an auxiliary transconductance amplifier Gm2, switches S1 to S7, and a capacitor C1. One end of the switch S1 serves as the inverting input end of the auxiliary operational amplifier A1. One end of the switch S2 is connected to one end of the switch S3 and one end of the switch S4 and serves as the non-inverting input end of the auxiliary operational amplifier A1. The other end of the switch S1 is connected to the other end of the switch S3 and the inverting input end of the main transconductance amplifier Gm1. The other end of the switch S2 is connected to the other end of the switch S4 and the non-inverting input end of the main transconductance amplifier Gm1. The output end of the transconductance amplifier Gm1 is connected to the input end of the transimpedance amplifier R and the output end of the auxiliary transconductance amplifier Gm2. The output end of the transimpedance amplifier R is connected to one end of the switch S5, one end of the switch S6, and one end of the capacitor C1 to generate an output signal Vout1. The other end of the switch S5 serves as the output end of the auxiliary operational amplifier A1. The other end of the capacitor C1 is grounded. The other end of the switch S6 is connected to the inverting input end of the auxiliary transconductance amplifier Gm2. One end of the switch S7 is connected to the non-inverting input end of the auxiliary transconductance amplifier Gm2. The other end of the switch S7 is connected to the bias voltage VCM.

[0011] Furthermore, the switches S1 , S2 , and S5 are controlled by a control signal φ1 , and the switches S3 , S4 , S6 , and S7 are controlled by a control signal φ2 . The control signal φ1 and the control signal φ2 are a pair of inverted signals.

[0012] Furthermore, the driving module DRIVER includes an NMOS tube M1, an NMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, an NMOS tube M11, a current source IB1, a current source IB2, a current source IB3, an inverter INV and switches S8 to S11, and the drain of the NMOS tube M1 is connected to the gate of the NMOS tube M1 and the gate of the NMOS tube M2 and serves as the driving module D The input end of RIVER, the source of the NMOS tube M1 is connected to the source of the NMOS tube M2 and one end of the current source IB1, the drain of the NMOS tube M2 is connected to the drain of the PMOS tube M3, the gate of the PMOS tube M3, the gate of the PMOS tube M4 and the gate of the PMOS tube M5, the drain of the PMOS tube M4 and the input end of the inverter INV and one end of the current source IB2 are connected to the node A, the drain of the PMOS tube M5 is connected to one end of the switch S8, the other end of the switch S8 is connected to one end of the switch S9, one end of the switch S10, the NMOS tube M1 and the gate of the NMOS tube M2. The drain of the S transistor M10, the gate of the NMOS transistor M10, and the gate of the NMOS transistor M11 are connected. The other end of the switch S9 is connected to the drain of the NMOS transistor M6. The output end of the inverter INV is connected to the gate of the NMOS transistor M6. The other end of the switch S10 is connected to the drain of the PMOS transistor M8. The gate of the PMOS transistor M8 is connected to the gate of the PMOS transistor M7. The drain of the PMOS transistor M7 is connected to one end of the current source IB3 and the gate of the PMOS transistor M9. The other end of the current source IB3 is grounded. The drain of the PMOS transistor M9 is connected to the switch S11. The other end of the switch S11 is connected to the drain of the NMOS transistor M11 and serves as the output end of the driving module DRIVER. The sources of the PMOS transistors M3, M4, M5, M7, M8 and M9 are connected to the voltage signal VCP. The other end of the current source IB1, the other end of the current source IB2, the sources of the NMOS transistors M6, M10 and M11 are connected to the voltage signal HVSS.

[0013] Furthermore, the switches S8 , S9 , and S11 are controlled by a control signal φ3 , and the switch S10 is controlled by a control signal φ4 . The control signal φ3 and the control signal φ4 are a pair of anti-phase signals.

[0014] Furthermore, the high-voltage domain floating ground module HVSS_Gen includes a coarse-adjustment ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment tube NM1, and a current adaptive adjustment circuit. The coarse-adjustment ground generation circuit generates a voltage VSS based on the power supply voltage VCC, and the reference voltage circuit generates a reference voltage VREF based on the power supply voltage VCC and the voltage VSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF, the inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistor network, the output terminal of the error amplifier EA is connected to the gate of the adjustment tube NM1 and the input terminal of the current adaptive adjustment circuit, the drain of the adjustment tube NM1 is connected to the power supply voltage VCC, the source of the adjustment tube NM1 is connected to the output terminal of the current adaptive adjustment circuit and generates a voltage signal HVSS, and the feedback resistor network divides the power supply voltage VCC and the voltage signal HVSS and outputs them.

[0015] Furthermore, the coarse adjustment ground generation circuit includes a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM6, a high-voltage NMOS transistor NM7, a high-voltage NMOS transistor NM8, a current source I1, and a current source I2. The source of the PMOS transistor PM2 and the drain of the NMOS transistor NM6 are connected to the power supply voltage VCC, the gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2 and the source of the PMOS transistor PM3, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, The gate of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7, the source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage VSS, the gate of the high-voltage NMOS transistor NM7 and the gate of the high-voltage NMOS transistor NM8 are connected to an enable signal EN, the source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1, the source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2, and the other end of the current source I1 and the other end of the current source I2 are grounded.

[0016] Furthermore, the current adaptive regulation circuit includes an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5 and a current source I0. One end of the current source I0 is connected to the power supply voltage VCC, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 is connected as the input end of the current adaptive regulation circuit to the output end of the low-voltage error amplifier EA and the gate of the adjustment transistor NM1. The source of the NMOS transistor NM2 is connected to the output end of the low-voltage error amplifier EA and the gate of the adjustment transistor NM1. The gate of the high-voltage PMOS transistor PM1 is connected to the drain of the high-voltage NMOS transistor NM5 and serves as the output end of the current adaptive regulation circuit to generate a voltage signal HVSS. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage VSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.

[0017] Furthermore, the feedback resistor network includes a resistor R1 and a resistor R2, one end of the resistor R1 is connected to the power supply voltage VCC, the other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output end of the feedback resistor network, and the other end of the resistor R2 is connected to the voltage signal HVSS.

[0018] Compared with the prior art, the present invention has the following advantages and effects: 1. The present invention uses Auto-Zero dynamic zeroing technology to significantly reduce the mismatch of the op amp input terminal; 2. The present invention introduces an additional loop, which intervenes only when the load current is very low to adjust the power tube overdrive voltage ,Will Fixed at a certain voltage, the system can maintain precise current detection ratio accuracy in the highest to lowest load current range (from high current to low current). BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a high-precision and wide-range current detection circuit of the present invention.

[0020] Figure 2 1 is a circuit diagram of the auxiliary operational amplifier A1 of the present invention.

[0021] Figure 3 4 is a circuit diagram of the driving module DRIVER of the present invention.

[0022] Figure 4 It is a circuit diagram of the high-voltage domain floating ground module HVSS_Gen of the present invention.

[0023] Figure 5 FIG. 1 is a circuit diagram of a coarse adjustment ground generating circuit according to the present invention.

[0024] Figure 6 is a schematic diagram of a resistive detection architecture in the prior art.

[0025] Figure 7 It is a schematic diagram of the prior art based on SenseFET technology. DETAILED DESCRIPTION

[0026] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0027] like Figure 1 As shown, the present invention is a high-precision wide-range current detection circuit, comprising an auxiliary operational amplifier A1, a power tube MP, a sampling tube MS, a PMOS tube PM1, a resistor RS, an operational amplifier OP, a charge pump Charge Pump, a driver module DRIVER and a high-voltage domain floating ground module HVSS_Gen, the drain of the power tube MP, the drain of the sampling tube MS and the charge pump Charge The input terminal of Pump is connected to the power supply voltage VCC. The gate of the power transistor MP is connected to the gate of the sampling transistor MS and the output terminal of the driver module DRIVER. The source of the power transistor MP is connected to the non-inverting input terminal of the auxiliary operational amplifier A1, the load LOAD, and the inverting input terminal of the operational amplifier OP to generate an output voltage OUT. The source of the sampling transistor MS is connected to the inverting input terminal of the auxiliary operational amplifier A1 and the source of the PMOS transistor PM1. The output terminal of the auxiliary operational amplifier A1 is connected to the gate of the PMOS transistor PM1. The drain of the PMOS transistor PM1 is connected to one end of the resistor RS to generate a voltage signal VSENS. The other end of the resistor RS is grounded. The non-inverting input terminal of the operational amplifier OP is connected to the reference voltage VREF. The output terminal of the operational amplifier OP is connected to the input terminal of the driver module DRIVER. The output terminal of the charge pump Charge Pump is connected to the high-voltage terminal of the driver module DRIVER to generate a voltage signal VCP. The output terminal of the high-voltage domain floating ground module HVSS_Gen is connected to the low-voltage terminal of the driver module DRIVER to generate a voltage signal HVSS.

[0028] The system samples the load current IL proportionally (with a sampling ratio of 1:K) and converts the current signal into a voltage signal, VSENS, using a sampling resistor, RS. To achieve high-precision current sampling over a wide dynamic range, the system uses an auxiliary op amp, A1, to force equalization between the source potentials of the sampling transistor MS and the power transistor MP. Auxiliary op amp A1 employs auto-zero technology to effectively suppress input offset voltage to below 1mV. In the feedback control loop, the source voltage of the power transistor MP is sampled and fed back to the op amp, OP. The output signal of the op amp OP is transmitted to the driver module, DRIVER. The driver module DRIVER operates in the high-voltage domain and is powered by a charge pump and a high-voltage floating ground module, HVSS_Gen. Ultimately, the driver module DRIVER dynamically adjusts the gate voltage of the power transistor MP to ensure that the output voltage OUT remains stable within the ideal operating range.

[0029] like Figure 2 As shown, the auxiliary operational amplifier A1 includes a main transconductance amplifier Gm1, a transimpedance amplifier R, an auxiliary transconductance amplifier Gm2, switches S1 to S7, and a capacitor C1. One end of the switch S1 serves as the inverting input end of the auxiliary operational amplifier A1. One end of the switch S2 is connected to one end of the switch S3 and one end of the switch S4 and serves as the non-inverting input end of the auxiliary operational amplifier A1. The other end of the switch S1 is connected to the other end of the switch S3 and the inverting input end of the main transconductance amplifier Gm1. The other end of the switch S2 is connected to the other end of the switch S4 and the non-inverting input end of the main transconductance amplifier Gm1. The output end of the amplifier Gm1 is connected to the input end of the transimpedance amplifier R and the output end of the auxiliary transconductance amplifier Gm2. The output end of the transimpedance amplifier R is connected to one end of the switch S5, one end of the switch S6, and one end of the capacitor C1 to generate an output signal Vout1. The other end of the switch S5 serves as the output end of the auxiliary operational amplifier A1. The other end of the capacitor C1 is grounded. The other end of the switch S6 is connected to the inverting input end of the auxiliary transconductance amplifier Gm2. One end of the switch S7 is connected to the non-inverting input end of the auxiliary transconductance amplifier Gm2. The other end of the switch S7 is connected to the bias voltage VCM.

[0030] The switches S1, S2, and S5 are controlled by a control signal φ1, and the switches S3, S4, S6, and S7 are controlled by a control signal φ2. The control signal φ1 and the control signal φ2 are a pair of anti-phase signals.

[0031] In the first stage, the control signal φ1 controls switches S1, S2, and S5 to close, and the control signal φ2 controls switches S3, S4, S6, and S7 to open. The auxiliary operational amplifier A1 is in the amplification stage, and the output signal Vout1 voltage at the output end is: Vout1=gm1*R*Vos1, where gm1 is the amplification factor of the main transconductance amplifier Gm1, R is the amplification factor of the transimpedance amplifier R, and Vos1 is the offset voltage introduced by the non-inverting input end of the main transconductance amplifier Gm1. The voltage of the input signal Vout1 and the DC voltage are both present on the capacitor C1, and the state of the external PMOS tube PM1 is maintained during the subsequent control signal φ1 disconnection stage. In the second stage, the control signal φ2 controls switches S3, S4, S6, and S7 to close, and the control signal φ1 controls switches S1, S2, and S5 to open. The auxiliary operational amplifier A1 enters the zeroing stage. The input of the auxiliary operational amplifier A1 is short-circuited, the output is open, and the auxiliary transconductance amplifier Gm2 intervenes. The capacitor C1 inputs the mismatch charge information of the main transconductance amplifier Gm1 in the first stage into the negative feedback loop of the auxiliary transconductance amplifier Gm2 to offset the mismatch charge of the offset voltage Vos1. At the same time, considering the offset voltage Vos2 introduced by the auxiliary transconductance amplifier Gm2, it can be written as: ; The equivalent mismatch at the corresponding input end will be greatly reduced. The bias voltage VCM is the same as the average value after the DC bias point in the first stage stabilizes: .

[0032] like Figure 3As shown, the driving module DRIVER includes an NMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, a current source IB1, a current source IB2, a current source IB3, an inverter INV and switches S8 to S11. The drain of the NMOS transistor M1 is connected to the gate of the NMOS transistor M1 and the gate of the NMOS transistor M2 and serves as the driving module DRIVER. The source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and one end of the current source IB1. The drain of the NMOS transistor M2 is connected to the drain of the PMOS transistor M3, the gate of the PMOS transistor M3, the gate of the PMOS transistor M4 and the gate of the PMOS transistor M5. The drain of the PMOS transistor M4 is connected to the input end of the inverter INV and one end of the current source IB2 at the node A. The drain of the PMOS transistor M5 is connected to one end of the switch S8. The other end of the switch S8 is connected to one end of the switch S9, one end of the switch S10 and the gate of the NMOS transistor M10. The drain of the NMOS transistor M10 is connected to the gate of the NMOS transistor M11, the other end of the switch S9 is connected to the drain of the NMOS transistor M6, the output end of the inverter INV is connected to the gate of the NMOS transistor M6, the other end of the switch S10 is connected to the drain of the PMOS transistor M8, the gate of the PMOS transistor M8 is connected to the gate of the PMOS transistor M7, the drain of the PMOS transistor M7 is connected to one end of the current source IB3 and the gate of the PMOS transistor M9, the other end of the current source IB3 is grounded, and the drain of the PMOS transistor M9 is connected to one end of the switch S11. The other end of the switch S11 and the drain of the NMOS transistor M11 are connected to the GATE node and serve as the output end of the driver module DRIVER. The sources of the PMOS transistors M3, M4, M5, M7, M8, and M9 are connected to the voltage signal VCP. The other end of the current source IB1, the other end of the current source IB2, the sources of the NMOS transistors M6, M10, and M11 are connected to the voltage signal HVSS.

[0033] The switches S8, S9, and S11 are controlled by a control signal φ3, and the switch S10 is controlled by a control signal φ4. The control signal φ3 and the control signal φ4 are a pair of anti-phase signals.

[0034] When the output voltage OUT is in a low voltage state, the output of the operational amplifier OP is a low level.

[0035] When the output voltage OUT is lower than the power supply voltage VCC, the op amp OP outputs a low level, turning off the NOS transistor M1 and the NMOS transistor M2. At this point, the PMOS transistors M3, M4, and M5, lacking bias current, assume a high-impedance state. Node A is pulled low by the current source IB2, and the NMOS transistor M6 is turned on via the inverter INV.

[0036] In the first phase, control signal φ3 closes switches S8, S9, and S11, while control signal φ4 opens switch S10. PMOS transistor M9 mirrors the current from current source IB3, charging the GATE node and increasing the GATE node voltage. NMOS transistors M10 and M11 are turned off by the pull-down action of NMOS transistor M6, which does not affect the charging process.

[0037] In the second phase, control signal φ3 opens switches S8, S9, and S11, while control signal φ4 closes switch S10. PMOS transistors M8, NMOS transistors M10, and NMOS transistors M11 precisely replicate the current from current source IB3, forming a discharge path at the GATE node and causing the voltage at the GATE node to drop. At this point, the dynamic regulation of the GATE node voltage is determined by the charge and discharge currents of current source IB3.

[0038] When the output voltage OUT is in a high voltage state, the output of the operational amplifier OP is a high level.

[0039] When the output voltage OUT is too high, the op amp OP outputs a high level, activating NMOS transistors M1 and M2 (the current of NMOS transistor M2 is three times that of NMOS transistor M1). At this time, the PMOS transistor M4 mirrors a current of 0.75*IB1, which is greater than the current of current source IB2, causing node A to be pulled high. The inverter INV outputs a low level, turning off NMOS transistor M6.

[0040] In the first phase, control signal φ3 closes switches S8, S9, and S11, while control signal φ4 opens switch S10. Continuing the above process, PMOS transistor M5 mirrors the current of 0.75*IB1. Combined with the current mirrored by PMOS transistor M9, the charging current at the GATE node in the first phase is IB3 + 0.75*IB1 (enhancing charging capability).

[0041] In the second phase, control signal φ3 controls switches S8, S9, and S11 to be open, and control signal φ4 controls switch S10 to be closed. The discharge current of the GATE node remains IB3 (maintaining the reference discharge).

[0042] Since the charging current is significantly greater than the discharging current, the voltage of the GATE node continues to rise, thereby adjusting the power tube gate, reducing the output voltage OUT, and realizing closed-loop control.

[0043] like Figure 4 As shown, the high-voltage domain floating ground module HVSS_Gen includes a coarse adjustment ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment tube NM1 and a current adaptive adjustment circuit. The coarse adjustment ground generation circuit generates a voltage VSS based on the power supply voltage VCC, and the reference voltage circuit generates a reference voltage VREF based on the power supply voltage VCC and the voltage VSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF, the inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistor network, the output terminal of the error amplifier EA is connected to the gate of the adjustment tube NM1 and the input terminal of the current adaptive adjustment circuit, the drain of the adjustment tube NM1 is connected to the power supply voltage VCC, the source of the adjustment tube NM1 is connected to the output terminal of the current adaptive adjustment circuit and generates a voltage signal HVSS, and the feedback resistor network divides the power supply voltage VCC and the voltage signal HVSS and outputs them.

[0044] like Figure 5 As shown, the coarse adjustment ground generating circuit includes a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM6, a high-voltage NMOS transistor NM7, a high-voltage NMOS transistor NM8, a current source I1, and a current source I2. The source of the PMOS transistor PM2 and the drain of the NMOS transistor NM6 are connected to the power supply voltage VCC, the gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2 and the source of the PMOS transistor PM3, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, and the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM3. The gate of the OS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7, the source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage VSS, the gate of the high-voltage NMOS transistor NM7 and the gate of the high-voltage NMOS transistor NM8 are connected to an enable signal EN, the source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1, the source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2, and the other ends of the current source I1 and I2 are grounded.

[0045] The current adaptive regulation circuit includes an NMOS tube NM2, a high-voltage PMOS tube PM1, an NMOS tube NM3, an NMOS tube NM4, a high-voltage NMOS tube NM5 and a current source I0. One end of the current source I0 is connected to the power supply voltage VCC, and the other end of the current source I0 is connected to the drain of the NMOS tube NM2 and the source of the high-voltage PMOS tube PM1. The gate of the NMOS tube NM2 is connected to the output of the low-voltage error amplifier EA and the gate of the adjustment tube NM1 as the input end of the current adaptive regulation circuit. The source of the NMOS tube NM2 is connected to the high-voltage The drain of the NMOS transistor NM5 is connected and serves as the output end of the current adaptive regulation circuit to generate a voltage signal HVSS. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage VSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.

[0046] The feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VCC. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output end of the feedback resistor network. The other end of resistor R2 is connected to the voltage signal HVSS.

[0047] The coarse ground generation circuit provides a ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, the NMOS transistors NM7 and NMOS transistors NM8 are turned on, the gate-source voltage of the PMOS transistor PM2 is |VGS1|, the gate-source voltage of the PMOS transistor PM3 is |VGS2|, and the gate-source voltage of the NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS=VDD-|VGS1|-|VGS2|-VGS3.

[0048] The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. The reference voltage VREF is connected to the non-inverting input of the low-voltage error amplifier EA. The precise voltage signal HVSS is obtained through the feedback resistor network composed of resistors R1 and R2 and the adjustment tube NM1. The voltage signal HVSS is expressed as: .

[0049] When the power supply voltage VCC is powered on, the enable signal EN goes high, first generating a coarse ground voltage HVSS. This voltage HVSS provides the ground voltage for the reference voltage circuit. This in turn causes the feedback resistor network, low-voltage error amplifier EA, pass transistor NM1, and current adaptive regulation circuit to begin operating. The resulting output voltage signal HVSS is a precise floating reference ground voltage with a fixed voltage differential from the power supply voltage VDD.

[0050] The working range of the reference voltage circuit is from the power supply voltage VDD to the voltage VSS, and the working range of the low-voltage error amplifier EA is from the power supply voltage VDD to the voltage signal HVSS. The voltage difference between the working ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, and no high-voltage tube is required, which greatly saves area.

[0051] The current I0 generated by the current source I0 is divided into two paths and flows to the NMOS transistor NM2 and the high-voltage PMOS transistor PM1 respectively. Assuming that the current flowing through the NMOS transistor NM2 is I1 and the current flowing through the high-voltage PMOS transistor PM1 is I2, then I0=I1+I2. Since the width-to-length ratio of the adjustment transistor NM1 and the NMOS transistor NM2 is m:1, the current flowing through the adjustment transistor NM1 is m*I1. The current flowing through the NMOS transistor NM3 is equal to the current I2 flowing through the high-voltage PMOS transistor PM1. At the same time, since the width-to-length ratio of the NMOS transistor NM4 and the NMOS transistor NM3 is n:1, the current flowing through the NMOS transistor NM4 is n*I2.

[0052] The load operates between the power supply voltage VCC and the voltage signal HVSS. The load current is IL. The current flowing through the NMOS transistor NM4 is equal to the sum of the current I1 flowing through the NMOS transistor NM2, the current m*I1 flowing through the adjustment transistor NM1, and the load current IL. Therefore, the current flowing through the NMOS transistor NM4 is expressed as: .

[0053] If the load current increases, the current flowing through the NMOS tube NM4 increases, that is, I2 increases. Since I0=I1+I2, the current I1 flowing through the NMOS tube NM2 decreases, realizing that the power consumption changes with the load current.

[0054] When the load is not working, that is, the load current IL=0, the current on the NMOS tube NM4 is only: .

[0055] The corresponding current of the floating ground generating circuit in the prior art is , thus reducing the current , when the load is not working, reduce the circuit power consumption.

[0056] The present invention uses Auto-Zero dynamic zeroing technology to significantly reduce the mismatch of the op amp input; the present invention introduces an additional loop that intervenes only when the load current is very low to adjust the power tube overdrive voltage ,Will Fixed at a certain voltage, the system can maintain precise current detection ratio accuracy in the highest to lowest load current range (from high current to low current).

[0057] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A high-precision, wide-range current detection circuit, characterized by: It includes an auxiliary operational amplifier A1, a power tube MP, a sampling tube MS, a PMOS tube PM1, a resistor RS, an operational amplifier OP, a charge pump Charge Pump, a driver module DRIVER, and a high-voltage domain floating ground module HVSS_Gen. The drain of the power tube MP, the drain of the sampling tube MS, and the input of the charge pump Charge Pump are connected to the power supply voltage VCC. The gate of the power tube MP is connected to the gate of the sampling tube MS and the output of the driver module DRIVER. The source of the power tube MP is connected to the positive-inverting input of the auxiliary operational amplifier A1, the load LOAD, and the negative-inverting input of the operational amplifier OP to generate an output voltage OUT. The source of the sampling tube MS is connected to the negative-inverting input of the auxiliary operational amplifier A1 and the source of the PMOS tube PM1. The output of the auxiliary operational amplifier A1 is connected to the gate of the PMOS tube PM1. The drain of the PMOS tube PM1 is connected to one end of the resistor RS to generate a voltage signal VSENS. The other end of the resistor RS is grounded. The positive-inverting input of the operational amplifier OP is connected to the reference voltage VREF. The output of the operational amplifier OP is connected to the input of the driver module DRIVER. The charge pump Charge The output end of Pump is connected to the high voltage end of the driver module DRIVER and generates a voltage signal VCP. The output end of the high voltage domain floating ground module HVSS_Gen is connected to the low voltage end of the driver module DRIVER and generates a voltage signal HVSS.

2. The high-precision, wide-range current detection circuit according to claim 1, characterized in that: The auxiliary operational amplifier A1 includes a main transconductance amplifier Gm1, a transimpedance amplifier R, an auxiliary transconductance amplifier Gm2, switches S1 to S7, and a capacitor C1. One end of the switch S1 serves as the inverting input end of the auxiliary operational amplifier A1. One end of the switch S2 is connected to one end of the switch S3 and one end of the switch S4 and serves as the non-inverting input end of the auxiliary operational amplifier A1. The other end of the switch S1 is connected to the other end of the switch S3 and the inverting input end of the main transconductance amplifier Gm1. The other end of the switch S2 is connected to the other end of the switch S4 and the non-inverting input end of the main transconductance amplifier Gm1. The output end of the transimpedance amplifier Gm1 is connected to the input end of the transimpedance amplifier R and the output end of the auxiliary transconductance amplifier Gm2. The output end of the transimpedance amplifier R is connected to one end of the switch S5, one end of the switch S6, and one end of the capacitor C1 to generate an output signal Vout1. The other end of the switch S5 serves as the output end of the auxiliary operational amplifier A1. The other end of the capacitor C1 is grounded. The other end of the switch S6 is connected to the inverting input end of the auxiliary transconductance amplifier Gm2. One end of the switch S7 is connected to the non-inverting input end of the auxiliary transconductance amplifier Gm2. The other end of the switch S7 is connected to the bias voltage VCM.

3. The high-precision wide-range current detection circuit according to claim 2, characterized in that: The switches S1 , S2 , and S5 are controlled by a control signal φ1 , and the switches S3 , S4 , S6 , and S7 are controlled by a control signal φ2 . The control signal φ1 and the control signal φ2 are a pair of anti-phase signals.

4. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The driving module DRIVER includes an NMOS transistor M1, an NMOS transistor M2, a PMOS transistor M3, a PMOS transistor M4, a PMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8, a PMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, a current source IB1, a current source IB2, a current source IB3, an inverter INV and switches S8 to S11. The drain of the NMOS transistor M1 is connected to the gate of the NMOS transistor M1 and the gate of the NMOS transistor M2 and serves as the driving module DRIVE. The input end of R, the source of the NMOS transistor M1 is connected to the source of the NMOS transistor M2 and one end of the current source IB1, the drain of the NMOS transistor M2 is connected to the drain of the PMOS transistor M3, the gate of the PMOS transistor M3, the gate of the PMOS transistor M4 and the gate of the PMOS transistor M5, the drain of the PMOS transistor M4 is connected to the input end of the inverter INV and one end of the current source IB2 at the node A, the drain of the PMOS transistor M5 is connected to one end of the switch S8, the other end of the switch S8 is connected to one end of the switch S9, one end of the switch S10, the NMOS transistor M The drain of the NMOS transistor M10, the gate of the NMOS transistor M10 and the gate of the NMOS transistor M11 are connected. The other end of the switch S9 is connected to the drain of the NMOS transistor M6. The output end of the inverter INV is connected to the gate of the NMOS transistor M6. The other end of the switch S10 is connected to the drain of the PMOS transistor M8. The gate of the PMOS transistor M8 is connected to the gate of the PMOS transistor M7. The drain of the PMOS transistor M7 and one end of the current source IB3 are connected to the gate of the PMOS transistor M9. The other end of the current source IB3 is grounded. The drain of the PMOS transistor M9 is connected to the gate of the switch S11. One end of the switch S11 is connected to the drain of the NMOS transistor M11 and serves as the output end of the driving module DRIVER. The sources of the PMOS transistors M3, M4, M5, M7, M8, and M9 are connected to the voltage signal VCP. The other end of the current source IB1, the other end of the current source IB2, the sources of the NMOS transistors M6, M10, and M11 are connected to the voltage signal HVSS.

5. The high-precision wide-range current detection circuit according to claim 4, characterized in that: The switches S8 , S9 , and S11 are controlled by a control signal φ3 , and the switch S10 is controlled by a control signal φ4 . The control signal φ3 and the control signal φ4 are a pair of anti-phase signals.

6. The high-precision wide-range current detection circuit according to claim 1, characterized in that: The high-voltage domain floating ground module HVSS_Gen includes a coarse adjustment ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment tube NM1 and a current adaptive adjustment circuit. The coarse adjustment ground generation circuit generates a voltage VSS based on the power supply voltage VCC, and the reference voltage circuit generates a reference voltage VREF based on the power supply voltage VCC and the voltage VSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF, the inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistor network, the output terminal of the error amplifier EA is connected to the gate of the adjustment tube NM1 and the input terminal of the current adaptive adjustment circuit, the drain of the adjustment tube NM1 is connected to the power supply voltage VCC, the source of the adjustment tube NM1 is connected to the output terminal of the current adaptive adjustment circuit and generates a voltage signal HVSS, and the feedback resistor network divides the power supply voltage VCC and the voltage signal HVSS and outputs them.

7. The high-precision wide-range current detection circuit according to claim 6, characterized in that: The coarse adjustment ground generation circuit includes a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM6, a high-voltage NMOS transistor NM7, a high-voltage NMOS transistor NM8, a current source I1, and a current source I2. The source of the PMOS transistor PM2 and the drain of the NMOS transistor NM6 are connected to a power supply voltage VCC. The gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2 and the source of the PMOS transistor PM3. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, the gate of the NMOS transistor NM6, and the drain of the high-voltage NMOS transistor NM7. The source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage VSS. The gate of the high-voltage NMOS transistor NM7 and the gate of the high-voltage NMOS transistor NM8 are connected to an enable signal EN. The source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1. The source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2. The other end of the current source I1 and the other end of the current source I2 are grounded.

8. The high-precision, wide-range current detection circuit according to claim 6, characterized in that: The current adaptive regulation circuit comprises an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5 and a current source I0. One end of the current source I0 is connected to the power supply voltage VCC, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 is connected to the output of the low-voltage error amplifier EA and the gate of the adjustment transistor NM1 as the input end of the current adaptive regulation circuit. The source of the NMOS transistor NM2 is connected to the high-voltage error amplifier EA and the gate of the adjustment transistor NM1. The drain of the high-voltage NMOS transistor NM5 is connected to the output end of the current adaptive regulation circuit to generate a voltage signal HVSS. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage VSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.

9. The high-precision wide-range current detection circuit according to claim 6, characterized in that: The feedback resistor network includes resistor R1 and resistor R2. One end of resistor R1 is connected to the power supply voltage VCC, the other end of resistor R1 is connected to one end of resistor R2 and serves as the output end of the feedback resistor network, and the other end of resistor R2 is connected to the voltage signal HVSS.

Images