Chip deblocking method
By covering the bare die with hot-melt wax and grinding it layer by layer, the problem of bare die damage during chip disassembly is solved, and the reliability of chip analysis is improved.
Patent Information
- Application Number
- CN202510888338.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-09-30
AI Technical Summary
During chip failure analysis, disassembling the chip's outer package can easily damage the internal bare die, resulting in reduced analysis reliability.
The bare die is covered with hot-melt wax and then embedded with chips. The chips are ground layer by layer and optically inspected. The correspondence between solder balls and bumps is recorded. The bare die is removed by melting the hot-melt wax and then cleaned.
While ensuring analysis accuracy, damage to the bare die is avoided and the reliability of chip analysis is improved.
Smart Images
Figure CN120722162A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to the field of testing technology, and in particular to a chip unsealing method. Background Art
[0002] With the development of semiconductor technology, chips, as core components of electronic devices, are gradually moving towards miniaturization and high density. When a chip fails, chip failure analysis can determine the cause of the failure and confirm the failure mechanism, providing a basis for optimizing design and improving process.
[0003] When performing chip failure analysis, it is necessary to remove the chip's outer package and inspect the bare die inside. However, due to the complex structure inside the chip, it is easy to cause damage to the bare die inside the chip when the chip's outer package is disassembled, making it difficult to perform failure analysis and reducing the reliability of chip failure analysis. Summary of the Invention
[0004] To overcome the problems existing in the related art, this specification provides a chip unsealing method.
[0005] According to a first aspect of an embodiment of this specification, a chip unsealing method is provided, comprising:
[0006] Removing the heat sink of the chip to be analyzed to expose the bare die of the chip to be analyzed, wherein the chip to be analyzed is a flip chip;
[0007] Place solid hot melt wax on the back of the die, heat the chip to be analyzed, melt the solid hot melt wax and flow to cover the die, and cool it down to solidify the liquid hot melt wax;
[0008] preparing an inlay solvent, placing the chip to be analyzed with the hot melt wax solidified therein into the inlay solvent and solidifying the wax to form an inlay layer outside the chip to be analyzed;
[0009] The chip to be analyzed is ground layer by layer from the front side of the die and optically inspected to record the correspondence between the solder balls of the chip to be analyzed and the bumps on the front side of the die until the solder balls and substrate of the chip to be analyzed are ground away;
[0010] Heating the chip to be analyzed to melt the hot melt wax on the outer layer of the chip to be analyzed, and taking out the bare chip of the chip to be analyzed;
[0011] The removed die is cleaned.
[0012] Optionally, removing the heat sink of the chip to be analyzed to expose the bare die of the chip to be analyzed includes:
[0013] Confirm the location of the die of the chip to be analyzed;
[0014] baking the chip to be analyzed, and cutting the support layer of the chip to be analyzed from the edge of the chip to be analyzed toward the bare die;
[0015] The chip to be analyzed is placed in an organic solvent, the heat sink is lifted, and the process is repeated until the heat sink is removed.
[0016] Optionally, baking the chip to be analyzed is specifically:
[0017] The chip to be analyzed is placed in an incubator and baked in a first temperature range for a first preset time, wherein the first temperature range is 90° C. to 110° C., and the first preset time is 5 minutes to 15 minutes.
[0018] Optionally, the melting point of the hot melt wax is 90° C. to 110° C., and the temperature for heating the chip to be analyzed is 140° C. to 160° C.
[0019] Optionally, the embedding solvent is a mixed solvent of epoxy resin and curing agent.
[0020] Optionally, the step of grinding the chip to be analyzed layer by layer from the front side of the die and performing optical inspection includes:
[0021] Using a grinding tool with a first particle size to grind the chip to be analyzed from the front side of the die and perform optical inspection;
[0022] When the copper layer on the substrate of the chip to be analyzed is visible, a grinding tool with a second particle size is selected to grind the chip to be analyzed from the front side of the die and perform optical inspection, wherein the second particle size is larger than the first particle size.
[0023] Optionally, the first particle size is 320 mesh to 800 mesh, and the second particle size is 1200 mesh to 1500 mesh;
[0024] During the grinding process, the rotation speed of the grinding equipment is 200 to 300 rpm.
[0025] Optionally, during the process of heating the chip to be analyzed, the heating temperature is 160°C to 180°C.
[0026] Optionally, the step of cleaning the removed die includes:
[0027] placing the removed die into fuming nitric acid and heating it in a fume hood for a second preset time, and removing the die after the fuming nitric acid cools down;
[0028] The die is placed in an organic solution for ultrasonic cleaning.
[0029] Optionally, the organic solvent is acetone or alcohol.
[0030] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:
[0031] In the embodiments of this specification, for a flip chip to be analyzed, after removing the outer layer structure, the bare chip is covered with hot-melt wax and then embedded with the chip to be analyzed. Through layer-by-layer grinding and optical inspection, the correspondence between the solder balls and the bumps of the chip to be analyzed is confirmed. While ensuring the accuracy of the chip analysis, damage to the bare chip during the chip disassembly and analysis process is avoided, thereby improving the reliability of the chip analysis process.
[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.
[0034] Figure 1 This is a flow chart of a chip unsealing method involved in this application;
[0035] Figure 2 It is a structural diagram of a chip to be analyzed corresponding to a chip unsealing method involved in this application. DETAILED DESCRIPTION
[0036] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.
[0037] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
[0038] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information without departing from the scope of this specification. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."
[0039] This application provides a chip unpacking method, such as Figure 1 Shown, including:
[0040] S100: removing the heat sink of the chip to be analyzed to expose the bare die of the chip to be analyzed.
[0041] The chip to be analyzed 100 is a flip chip. The structure of the chip to be analyzed 100 is as follows: Figure 2 Including:
[0042] A substrate 1, on which a wiring layer and a copper cladding layer are formed;
[0043] Bare die 2, the bottom of the bare die 2 is connected to the wiring layer or the copper layer through the bump 20;
[0044] A support layer 3 is provided on the peripheral side of the die 2;
[0045] The heat sink 4 is attached to the back surface 2A of the die 2 via a thermal paste 40 and abuts against the support layer 3;
[0046] The solder ball 5 is arranged on the side of the substrate 1 away from the bare chip 2 and is connected to the wiring layer or the copper cladding layer. In addition, the bump 20 at the bottom of the bare chip 2 is connected to the solder ball 5 through the wiring layer or the copper cladding layer. There is a corresponding relationship between the bump 20 and the solder ball 5, which is part of the chip analysis.
[0047] Specifically, the step S100 of removing the heat sink of the chip to be analyzed to expose the bare die of the chip to be analyzed includes:
[0048] S100A, confirm the position of the die of the chip to be analyzed.
[0049] Before removing the heat sink of the chip to be analyzed, the position of the die 2 in the chip to be analyzed can be confirmed by external appearance observation or X-ray perspective observation, thereby avoiding scratching the die 2 during the process of unpacking the chip to be analyzed.
[0050] S100B, baking the chip to be analyzed, and cutting the support layer of the chip to be analyzed from the edge of the chip to be analyzed toward the bare die.
[0051] Optionally, the step S100B of baking the chip to be analyzed is specifically as follows:
[0052] The chip to be analyzed is placed in an incubator and baked within a first temperature range for a first preset time.
[0053] Wherein, the first temperature range is 90° C. to 110° C., and the first preset time is 5 minutes to 15 minutes.
[0054] During the baking process, the thermal paste 40 between the heat sink 4 and the die 2 softens, reducing the bonding force between the heat sink 4 and the die 2, and the support layer 3 is also easier to cut. However, the cutting position needs to be controlled so as not to contact the die 2 to avoid damage to the die 2.
[0055] Preferably, the temperature of the incubator is set to 100° C., and the first preset time is set to 10 minutes.
[0056] S100C, placing the chip to be analyzed into an organic solvent, lifting the heat sink, and repeating until the heat sink is removed.
[0057] After the support layer 3 is cut, the chip 100 to be analyzed is immersed in the organic solvent, so that the organic solvent flows into the chip 100 to be analyzed along the gap formed by the cut position 41, thereby reducing the viscosity of the thermal paste 40, so that the heat sink 4 can be lifted more easily without damaging the bare chip 2.
[0058] After soaking, take out the chip 100 to be analyzed, and apply slight force to tilt the heat sink 4 upward. If it cannot be tilted, repeat soaking and baking until the support layer 3 can be tilted away, and then remove the heat sink 4.
[0059] Optionally, the organic solvent is acetone or alcohol. The selection of the organic solvent can be based on actual needs, that is, it can be set to reduce the viscosity of the thermal paste 40.
[0060] In the above process, the scratching and the organic solvent soaking can be repeated to gradually remove the heat sink 4, thereby reducing the risk of damage to the die caused by removing the heat sink.
[0061] S101, placing solid hot melt wax on the back of the bare chip, heating the chip to be analyzed so that the solid hot melt wax melts and flows to cover the bare chip, and cooling the hot melt wax so that the liquid hot melt wax solidifies.
[0062] Subsequently, a piece of solid hot melt wax can be cut off and placed on the back side 2A of the die 2, which is the side close to the heat sink 4. Since the heat sink 4 is removed, the back side 2A of the die 2 is exposed.
[0063] Thereafter, the chip 100 to be analyzed provided with solid hot melt wax is placed on a heating table. The hot melt wax is melted by heating and becomes liquid hot melt wax, so that it can cover the back side 2A of the bare chip 2 and protect the bare chip 2 .
[0064] Optionally, the melting point of the hot melt wax is 90° C. to 110° C., and the temperature for heating the chip to be analyzed is 140° C. to 160° C. Preferably, the melting point of the hot melt wax can be 100° C., and the temperature for heating the chip to be analyzed can be set to 150° C. During heating, the solder balls 5 of the chip to be analyzed 100 can be placed toward the heating stage.
[0065] S102 , preparing an inlay solvent, placing the chip to be analyzed with the hot melt wax solidified therein into the inlay solvent and solidifying it to form an inlay layer outside the chip to be analyzed.
[0066] Optionally, the embedding solvent is a mixed solvent of epoxy resin and curing agent.
[0067] Before embedding, epoxy resin and curing agent can be mixed to form a mixed solvent. The chip to be analyzed is placed in a mold, and then the mixed solvent is poured into the mold. The mixed solvent is allowed to solidify to encapsulate the chip to be analyzed with a solidified layer.
[0068] S103 , grinding the chip to be analyzed layer by layer from the front side of the bare die and performing optical inspection to record the correspondence between the solder balls of the chip to be analyzed and the bumps on the front side of the bare die, until the solder balls and substrate of the chip to be analyzed are ground away.
[0069] The front side of the die 2 is the side of the die 2 facing the substrate 1. The optical inspection can be performed by taking a picture with a camera or by taking a picture with an X-ray, whichever is selected according to actual needs.
[0070] Optionally, the step S103 of grinding the chip to be analyzed layer by layer from the front side of the die and performing optical inspection includes:
[0071] S103A, selecting a grinding tool with a first particle size to grind the chip to be analyzed from the front side of the die and performing optical inspection.
[0072] S103B: When the copper layer on the substrate of the chip to be analyzed is visible, use a grinding tool with a second particle size to grind the chip to be analyzed from the front side of the die and perform optical inspection.
[0073] The copper layer may include a copper clad layer or a signal line. The front side 2B of the bare chip 2 may be recorded by taking photos, so as to gradually record the corresponding relationship between the solder balls 5 and the bumps 20 for subsequent chip failure analysis.
[0074] During grinding, it is achieved through sandpaper or grinding wheel, etc., wherein different grinding efficiencies can be achieved through grinding devices with different particle sizes, for example, the second particle size is greater than the first particle size.
[0075] Optionally, the first particle size is 320 mesh to 800 mesh, and the second particle size is 1200 mesh to 1500 mesh. Preferably, the first particle size can be 500 mesh, and the second particle size can be 1400 mesh, which is not limited according to actual settings.
[0076] During the grinding process, the rotation speed of the grinding equipment is 200 rpm to 300 rpm. When grinding is achieved in the form of a grinding wheel or wrapped sandpaper, preferably, the rotation speed can be set to 250 rpm.
[0077] S104 , heating the chip to be analyzed to melt the hot melt wax on the outer layer of the chip to be analyzed, and taking out the bare chip of the chip to be analyzed.
[0078] After the ground chip to be analyzed is taken out, it can be heated. Optionally, during the heating process of the chip to be analyzed, the heating temperature is 160° C. to 180° C. Preferably, the heating temperature can be set to 170° C.
[0079] When the hot-melt wax is softened, the hot-melt wax portion can be clamped with metal tweezers to remove the chip to be analyzed coated with the hot-melt wax.
[0080] The chip to be analyzed is taken out and placed on a heating table, heated at a temperature of about 100° C. to remove the hot melt wax, and then the bare chip 2 is wiped clean with a cotton swab dipped in alcohol.
[0081] S105: Clean the removed bare die.
[0082] Optionally, the step S105 of cleaning the removed die includes:
[0083] S105A, placing the removed bare chip into fuming nitric acid and heating it in a fume hood for a second preset time, and taking out the bare chip after the fuming nitric acid cools down.
[0084] S105B, placing the bare chip into an organic solution for ultrasonic cleaning.
[0085] Heating with high-temperature acid can remove residual material from die 2, making the disassembled die 2 easier to observe and analyze. The heating temperature can be set to 90°C, and the second preset time can be set to 2 minutes. The fuming nitric acid can be understood as nitric acid with a concentration greater than 95%. Due to its high volatility, the beaker containing the fuming nitric acid needs to be placed in a fume hood for ventilation to prevent the fuming nitric acid from affecting the room. After the second preset time, the die 2 can be removed from the fuming nitric acid.
[0086] After the bare die 2 is taken out, it is placed in an organic solvent and cleaned by ultrasonic waves, and the process of step S105A to step S105B is repeated until the corrosion products on the bare die 2 are completely removed.
[0087] Optionally, the organic solvent is acetone or alcohol.
[0088] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:
[0089] In the embodiments of this specification, for a flip chip to be analyzed, after removing the outer layer structure, the bare chip is covered with hot-melt wax and then embedded with the chip to be analyzed. Through layer-by-layer grinding and optical inspection, the correspondence between the solder balls and the bumps of the chip to be analyzed is confirmed. While ensuring the accuracy of the chip analysis, damage to the bare chip during the chip disassembly and analysis process is avoided, thereby improving the reliability of the chip analysis process.
[0090] The above-mentioned chip unsealing method can be implemented through an assembly line, and automatically operated by electronic equipment such as links and robotic arms, so as to realize the automatic implementation of the chip unsealing method. Specifically, it can be set according to actual needs without restriction.
[0091] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.
[0092] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
[0093] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.
Claims
1. A chip unsealing method, characterized in that: include: Removing the heat sink of the chip to be analyzed to expose the bare die of the chip to be analyzed, wherein the chip to be analyzed is a flip chip; Place solid hot melt wax on the back of the die, heat the chip to be analyzed, melt the solid hot melt wax and flow to cover the die, and cool it down to solidify the liquid hot melt wax; preparing an inlay solvent, placing the chip to be analyzed with the hot melt wax solidified therein into the inlay solvent and solidifying the wax to form an inlay layer outside the chip to be analyzed; The chip to be analyzed is ground layer by layer from the front side of the die and optically inspected to record the correspondence between the solder balls of the chip to be analyzed and the bumps on the front side of the die until the solder balls and substrate of the chip to be analyzed are ground away; Heating the chip to be analyzed to melt the hot melt wax on the outer layer of the chip to be analyzed, and taking out the bare chip of the chip to be analyzed; The removed die is cleaned.
2. The method according to claim 1, characterized in that The step of removing the heat sink of the chip to be analyzed to expose the bare die of the chip to be analyzed includes: Confirm the location of the die of the chip to be analyzed; baking the chip to be analyzed, and cutting the support layer of the chip to be analyzed from the edge of the chip to be analyzed toward the bare die; The chip to be analyzed is placed in an organic solvent, the heat sink is lifted, and the process is repeated until the heat sink is removed.
3. The method according to claim 2, characterized in that The baking of the chip to be analyzed is specifically as follows: The chip to be analyzed is placed in an incubator and baked in a first temperature range for a first preset time, wherein the first temperature range is 90° C. to 110° C., and the first preset time is 5 minutes to 15 minutes.
4. The method according to claim 1, wherein The melting point of the hot melt wax is 90° C. to 110° C., and the temperature for heating the chip to be analyzed is 140° C. to 160° C.
5. The method according to claim 1, wherein The embedding solvent is a mixed solvent of epoxy resin and curing agent.
6. The method according to claim 1, characterized in that The method of grinding the chip to be analyzed layer by layer from the front side of the die and performing optical inspection includes: Using a grinding tool with a first particle size to grind the chip to be analyzed from the front side of the die and perform optical inspection; When the copper layer on the substrate of the chip to be analyzed is visible, a grinding tool with a second particle size is selected to grind the chip to be analyzed from the front side of the die and perform optical inspection, wherein the second particle size is larger than the first particle size.
7. The method according to claim 6, characterized in that The first particle size is 320 mesh to 800 mesh, and the second particle size is 1200 mesh to 1500 mesh; During the grinding process, the rotation speed of the grinding equipment is 200 to 300 rpm.
8. The method according to claim 1, characterized in that During the process of heating the chip to be analyzed, the heating temperature is 160°C to 180°C.
9. The method according to claim 1, characterized in that The step of cleaning the removed bare die includes: placing the removed die into fuming nitric acid and heating it in a fume hood for a second preset time, and removing the die after the fuming nitric acid cools down; The die is placed in an organic solution for ultrasonic cleaning.
10. The method according to claim 2 or 9, characterized in that The organic solvent is acetone or alcohol.