Digital clock jitter measurement circuit and measurement method

Abstract

The application provides a digital clock jitter measurement circuit and a measurement method. The measurement circuit comprises a delay module, which receives a clock signal to be measured and generates a first clock signal and a second clock signal, and the phase difference between the first clock signal and the second clock signal is one clock cycle; a measurement module, which comprises a sampling unit, an oscillator control unit, a measurement unit and a counter unit. The measurement unit comprises a slow-frequency oscillator, an intermediate-frequency oscillator and a high-frequency oscillator, and a first edge detector and a second edge detector, the first edge detector being connected with the slow-frequency oscillator and the intermediate-frequency oscillator, and the second edge detector being connected with the intermediate-frequency oscillator and the high-frequency oscillator. The clock jitter measurement circuit and the measurement method provided by the application can automatically select a matched oscillator according to the phase relationship between the first clock signal and the second clock signal, thereby realizing automatic measurement of clock jitter.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital circuit design, in particular to a digital clock jitter measurement circuit and a measurement method. BACKGROUND

[0002] With the explosion of demand for data throughput in artificial intelligence and big data centers, system chips (SoC) evolve towards "high frequency, high integration, and multiple heterogeneous modules". As an important part of the system, the jitter of the clock signal will directly lead to sampling misalignment / protocol interaction failure, so clock jitter measurement has become a core link to ensure system performance.

[0003] Off-chip measurement requires expensive special equipment such as high-speed input / output (I / O) circuits, high-frequency probes, and probe stations, and the operation is complex and costly. The on-chip system integrates the jitter measurement function inside the chip, without the need for additional external expensive equipment, reducing the measurement cost. At the same time, the off-chip system is difficult to comprehensively and accurately measure and control the jitter in the complex on-chip environment; while the on-chip system can better adapt to its complex internal structure, realize comprehensive monitoring of the jitter of each module and the entire system, and meet the stringent requirements of complex systems for jitter measurement.

[0004] In on-chip test technology, the method of digitizing the jitter of the measured signal based on the adjustable delay line structure using the delay difference between delay units is widely used. However, this kind of technology increases the chip area while improving the measurement resolution.

[0005] Therefore, it is necessary to provide a circuit and method for realizing digital clock jitter measurement with lower area cost. SUMMARY

[0006] In view of this, the present application provides a digital clock jitter measurement circuit and a measurement method to solve the above technical problems in the prior art.

[0007] According to one aspect of the present application, a digital clock jitter measurement circuit is provided, the measurement circuit comprising:

[0008] a delay module, which receives a clock signal to be measured and generates a first clock signal and a second clock signal, the phase difference between the first clock signal and the second clock signal being one clock period;

[0009] a measurement module, which comprises a sampling unit, an oscillator control unit, a measurement unit, and a counter unit,

[0010] The measurement unit comprises a slow frequency oscillator, an intermediate frequency oscillator and a fast frequency oscillator, and a first edge detector and a second edge detector, the first edge detector is connected with the slow frequency oscillator and the intermediate frequency oscillator, the second edge detector is connected with the intermediate frequency oscillator and the fast frequency oscillator,

[0011] The counter unit comprises a first counter and a second counter, the first counter is used for counting the oscillation times of the slow frequency oscillator or the intermediate frequency oscillator, and the second counter is used for counting the oscillation times of the intermediate frequency oscillator or the fast frequency oscillator;

[0012] The sampling unit samples the first clock signal and the second clock signal respectively and outputs the sampled signals to the oscillator control unit,

[0013] When the second clock signal lags behind the first clock signal, the oscillator control unit controls the slow frequency oscillator and the intermediate frequency oscillator to start, and the counter unit outputs the value of the first counter;

[0014] When the second clock signal leads the first clock signal, the oscillator control unit controls the fast frequency oscillator and the intermediate frequency oscillator to start, and the counter unit outputs the value of the second counter.

[0015] According to the preferred embodiment of the present application, the sampling unit comprises a first D flip-flop and a second D flip-flop, the first D flip-flop is used for sampling the rising edge of the first clock signal, and the second D flip-flop is used for sampling the rising edge of the second clock signal.

[0016] According to the preferred embodiment of the present application, the first edge detector is configured to detect the phase of the oscillation clock signal in the slow frequency oscillator and the intermediate frequency oscillator,

[0017] When the oscillation clock signal of the slow frequency oscillator lags behind the oscillation clock signal of the intermediate frequency oscillator, the first edge detector outputs a feedback signal PD1, so that the oscillator control unit closes the slow frequency oscillator and the intermediate frequency oscillator;

[0018] When the oscillation clock signal of the intermediate frequency oscillator lags behind the oscillation clock signal of the fast frequency oscillator, the second edge detector outputs a feedback signal PD2, so that the oscillator control unit closes the intermediate frequency oscillator and the fast frequency oscillator.

[0019] According to a preferred embodiment of the present application, the oscillator control unit comprises an OR gate, a third D flip-flop, a first AND gate and a second AND gate, the inputs of the OR gate being the feedback signal PD1 of the first phase detector output and the feedback signal PD2 of the second phase detector output, the inputs of the first AND gate being the Q terminal of the first D flip-flop and the non-Q terminal of the third flip-flop, the inputs of the second AND gate being the Q terminal of the second D flip-flop and the non-Q terminal of the third flip-flop, the output terminal of the OR gate being connected to the input terminal of the third D flip-flop, the output terminal of the first AND gate being connected to the slow frequency oscillator and the fast frequency oscillator, and the output terminal of the second AND gate being connected to the intermediate frequency oscillator.

[0020] According to a preferred embodiment of the present application, the counter unit further comprises a phase detector and a selector, the input terminals of the phase detector being connected to the output terminals of the first D flip-flop and the second D flip-flop, the output terminal of the phase detector being connected to the control terminal of the selector, when the phase detector detects that the phase of the first clock signal is ahead of the second clock, the selector selects the output of the first counter under the control of the phase detector; when the phase detector detects that the phase of the first clock signal is behind the second clock, the selector selects the output of the second counter under the control of the phase detector.

[0021] According to a preferred embodiment of the present application, the measurement unit comprises a slow intermediate frequency measurement unit and an intermediate fast frequency measurement unit, the slow intermediate frequency measurement unit comprising a slow frequency oscillator, an intermediate frequency oscillator and a first edge detector, and the intermediate fast frequency measurement unit comprising an intermediate frequency oscillator, a fast frequency oscillator and a second edge detector.

[0022] According to a preferred embodiment of the present application, the slow frequency oscillator, the intermediate frequency oscillator and the fast frequency oscillator comprise an adjustable load for adjusting the resolution of the measurement unit.

[0023] According to a preferred embodiment of the present application, the first edge detector and the second edge detector are used to detect the rising edge or the falling edge of the clock signal.

[0024] According to a preferred embodiment of the present application, the measurement circuit further comprises a synchronous reset unit for synchronously resetting the first D flip-flop, the second D flip-flop and the third D flip-flop DFF3, and clearing the data of the first counter and the second counter.

[0025] According to another aspect of the present application, a clock jitter measurement method is provided, the method being controlled by an automatic control module to execute the measurement circuit described above, and the method comprising the following steps:

[0026] Step S1, adjusting the delay module to generate a first clock signal and a second clock signal;

[0027] Step S2, resetting the measurement module;

[0028] Step S3, measuring the jitter of the clock signal to be measured within a given time;

[0029] Step S4, recording the measurement result and updating the measurement times;

[0030] Step S5, if the measurement times reach a preset value, ending the measurement, or if the measurement times do not reach the preset value, returning to step S2.

[0031] From the above technical solution, it can be seen that the measurement circuit provided by the present application can automatically select a matched oscillator to realize fast and accurate measurement of the digital clock jitter with a lower area cost. In addition, in the measurement circuit provided by the present application, the oscillator can have an adjustable load. Through the digitally controlled load capacitor, the measurement accuracy can be adjusted, and the measurement resolution is improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solutions of the present application, but do not constitute a limitation on the technical solutions of the present application.

[0033] Figure 1 A structural schematic diagram of a clock jitter measurement circuit of an exemplary embodiment of the present application is shown;

[0034] Figure 2 A structural schematic diagram of a measurement module of an exemplary embodiment of the present application is shown;

[0035] Figure 3 A signal waveform diagram in a measurement unit of an exemplary embodiment of the present application is shown;

[0036] Figure 4 A structural schematic diagram of an oscillator of an exemplary embodiment of the present application is shown;

[0037] Figure 5 A structural schematic diagram of an edge detector of an exemplary embodiment of the present application is shown;

[0038] Figure 6 A structural schematic diagram of a synchronous reset unit of an exemplary embodiment of the present application is shown;

[0039] Figure 7 A flow chart of a clock jitter measurement method of an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] Various exemplary embodiments of the present application will be described herein below with reference to the drawings. The description of the exemplary embodiments is merely illustrative in nature and is in no way intended to limit the application, its application, or uses. The application can be implemented in numerous ways, including but not limited to those set forth in the following description below. Such embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0041] Unless specifically stated otherwise, as long as a numerical limitation of an element is not intentionally limited, the element can be one or more. The term "plurality" means two or more, the term "based on" should be interpreted as "based at least in part on", the terms "and / or" and "at least one of" encompass any and all possible combinations of the listed items. In addition, "first", "second", and similar terms are used only for descriptive purposes and do not necessarily imply relative importance or an implicit indication of the number of indicated technical features.

[0042] Reference is made to Figure 1 which shows a structural schematic diagram of a clock jitter measurement circuit according to an exemplary embodiment of the present application. As shown in Figure 1 , the clock jitter measurement circuit includes a delay module and a measurement module. The clock signal to be measured CK IN passes through the delay module to generate two clock signals, a first clock signal CK1 and a second clock signal CK2, wherein the phase difference between the two clock signals CK1 and CK2 is one clock period. The measurement module processes the clock signals CK1 and CK2 output by the delay module and quantizes the phase difference between the clock signals CK1 and CK2, outputting a jitter signal J OUT. The clock jitter measurement circuit also includes an automatic control module for controlling the measurement module to achieve automated measurement.

[0043] Reference is made to Figure 2 which shows a structural schematic diagram of a measurement module according to an exemplary embodiment of the present application. As shown in Figure 2 , the measurement module includes a sampling unit, an oscillator control unit, a measurement unit, and a counter unit.

[0044] The sampling unit includes a first D flip-flop DFF1 and a second D flip-flop DFF2. The first D flip-flop DFF1 is used to sample the rising edge of the input first clock signal CK1, and the second D flip-flop DFF2 is used to sample the rising edge of the input second clock signal CK2.

[0045] The measuring unit comprises a slow intermediate frequency measuring unit and an intermediate fast frequency measuring unit. The slow intermediate frequency measuring unit comprises a slow frequency oscillator, an intermediate frequency oscillator and a first edge detector. The intermediate fast frequency measuring unit comprises an intermediate frequency oscillator, a fast frequency oscillator and a second edge detector. The oscillation frequency F1 of the slow frequency oscillator, the oscillation frequency F2 of the intermediate frequency oscillator and the oscillation frequency F3 of the fast frequency oscillator are successively increased, and preferably the oscillators are provided with adjustable loads.

[0046] When the input first clock signal CK1 is ahead of the input second clock signal CK2, the slow intermediate frequency measuring unit is operated, in which the slow frequency oscillator and the intermediate frequency oscillator start oscillation, and initially the phase of the oscillation clock signal RO_S of the slow frequency oscillator is ahead of the phase of the oscillation clock signal RO_M of the intermediate frequency oscillator. When the edge detector detects that the phase of the oscillation clock signal RO_S of the slow frequency oscillator is behind the phase of the oscillation clock signal RO_M of the intermediate frequency oscillator, the first edge detector of the slow intermediate frequency measuring unit outputs a phase detection feedback signal PD1 to control the slow frequency oscillator and the intermediate frequency oscillator to stop oscillation. When the input second clock signal CK2 is ahead of the input first clock signal CK1, the intermediate fast frequency measuring unit is operated. In which the intermediate frequency oscillator and the fast frequency oscillator start oscillation, and initially the phase of the oscillation clock signal RO_M of the intermediate frequency oscillator is ahead of the phase of the oscillation clock signal RO_F of the fast frequency oscillator. When the edge detector detects that the phase of the oscillation clock signal RO_M of the intermediate frequency oscillator is behind the phase of the oscillation clock signal RO_F of the fast frequency oscillator, the edge detector of the intermediate fast frequency measuring unit outputs a phase detection feedback signal PD2 to control the intermediate frequency oscillator and the fast frequency oscillator to stop oscillation. By controlling the adjustable load of the oscillators, the resolution of the measuring unit can be adjusted.

[0047] The oscillator control unit comprises an or gate OR with the first phase detection feedback signal PD1 of the slow intermediate frequency measuring unit and the second phase detection feedback signal PD2 of the intermediate fast frequency measuring unit as input signals, a third D flip-flop DFF3, a first and gate AND1 with the non-Q terminal of the third D flip-flop DFF3 and the Q terminal of the first D flip-flop DFF1 as input signals, and a second and gate AND2 with the non-Q terminal of the third D flip-flop DFF3 and the Q terminal of the second D flip-flop DFF2 as input signals. The oscillator control unit is used to control the start and stop of the slow intermediate frequency measuring unit and the intermediate fast frequency measuring unit.

[0048] The counter unit includes two counters (a first counter and a second counter), a selector MUX, and a phase detector. The counter unit is configured to count the oscillation times CNT1 of the oscillation clock RO1 generated by the slow intermediate frequency measurement unit and the oscillation times CNT2 of the oscillation clock RO2 of the intermediate fast frequency measurement unit, and select the oscillation times CNT1 of the slow intermediate frequency measurement unit or the oscillation times CNT2 of the intermediate fast frequency measurement unit through the selector MUX. The output of the phase detector is connected with the selection signal SEL of the selector MUX. When the first clock signal CK1 is ahead of the second clock signal CK2, the phase detector arbitrates the phase relationship and provides the selection signal SEL for the selector MUX to select the oscillation times CNT1 generated by the slow intermediate frequency measurement unit; when the first clock signal CK1 is behind the second clock signal CK2, the phase detector arbitrates the phase relationship and provides the selection signal SEL for the selector MUX to select the oscillation times CNT2 generated by the intermediate fast frequency measurement unit. The output jitter value J_OUT is:

[0049]

[0050] wherein F1 is the frequency of the slow frequency oscillator, F2 is the frequency of the intermediate frequency oscillator, and F3 is the frequency of the fast frequency oscillator.

[0051] The measurement circuit according to the embodiment of the present application can further include a synchronous reset unit configured to perform a synchronous reset operation on the input reset signal RST. The synchronous reset operation includes resetting the first D flip-flop DFF1, the second D flip-flop DFF2 of the sampling module, and the third D flip-flop DFF3 of the oscillator control unit, and clearing the counter data of the counter unit CNT1 and CNT2.

[0052] Reference Figure 3 which shows the signal waveform diagram in the measurement unit of the exemplary embodiment of the present application. As shown in FIG. 1, the measurement unit includes a slow intermediate frequency measurement unit, an intermediate fast frequency measurement unit, a counter unit, a sampling module, and an oscillator control unit. Figure 3As shown, when the first clock signal CK1 101 is ahead of the second clock signal CK2 102, the first D flip-flop samples the rising edge of the input clock signal CK1 to obtain a rising edge pulse 103, and the second D flip-flop samples the rising edge of the input clock signal CK2 to obtain a rising edge pulse 104. Then the oscillation control unit starts the slow IF measurement unit, and the slow frequency oscillator and the intermediate frequency oscillator start oscillating. Initially, the phase 105 of the oscillation clock signal RO_S of the slow frequency oscillator is ahead of the phase 106 of the oscillation clock signal RO_M of the intermediate frequency oscillator. When the edge detector detects that the phase 107 of the oscillation clock signal RO_S of the slow frequency oscillator is behind the phase 108 of the oscillation clock signal RO_M of the intermediate frequency oscillator, the edge detector of the slow IF measurement unit pulls up the phase detection feedback signal PD1 level 109, and then feeds back to the slow IF measurement unit to control the slow frequency oscillator and the intermediate frequency oscillator to stop oscillating. When the first clock signal CK1 201 is behind the second clock signal CK2 202, the first D flip-flop samples the rising edge of the input clock signal CK1 to obtain a rising edge pulse 203, and the second D flip-flop samples the rising edge of the input clock signal CK2 to obtain a rising edge pulse 204. Then the oscillation control unit starts the medium IF measurement unit, and the intermediate frequency oscillator and the fast frequency oscillator start oscillating. Initially, the phase 205 of the oscillation clock signal RO_M of the intermediate frequency oscillator is ahead of the phase 206 of the oscillation clock signal RO_F of the fast frequency oscillator. When the edge detector detects that the phase 207 of the oscillation clock signal RO_M of the intermediate frequency oscillator is behind the phase 208 of the oscillation clock signal RO_F of the fast frequency oscillator, the edge detector of the medium IF measurement unit pulls up the phase detection feedback signal PD2 level 209, and then feeds back to the medium IF measurement unit to control the intermediate frequency oscillator and the fast frequency oscillator to stop oscillating.

[0053] Reference Figure 4 FIG. 1 shows a structure diagram of an oscillator according to an example embodiment of the present application. Figure 2 The slow frequency oscillator, the intermediate frequency oscillator or the fast frequency oscillator shown in FIG. 1 can all adopt the oscillator structure. The oscillator circuit structure is not limited in the embodiments of the present application. Refer to Figure 4 The oscillator receives the output signal 10 of the oscillator control unit and generates an oscillation output signal 11. In the oscillator, the total number of combination logic elements including NAND gates is odd. Figure 4 The inverters in FIG. 1 can be replaced by other combination logic elements, such as NAND gates or XOR gates, etc. The slow frequency oscillator, the intermediate frequency oscillator or the fast frequency oscillator can use the same circuit, adjust the frequency of the circuit by adjusting the adjustable load, or use different circuit structures, but need to satisfy that the frequency of the slow frequency oscillator is lower than the frequency of the intermediate frequency oscillator, and the frequency of the intermediate frequency oscillator is lower than the frequency of the fast frequency oscillator.

[0054] Reference Figure 5 which shows a structural diagram of an edge detector of the exemplary embodiment of the present application. Figure 2 The first edge oscillator and the second edge oscillator shown in the above Figure 5 As shown, the edge detector can detect the phase of the edges (rising or falling) of the two oscillator output clocks 20 and 21 to generate a phase detection feedback signal PD1 or PD2 (numbered 22 in the figure). The output end 23 of the AND gate is connected to the input end of the first D flip-flop DFF1, and the output end of the second D flip-flop DFF2 is connected to the input end of the third D flip-flop DFF3. Figure 2 The counters are connected to the output ends of the D flip-flops, and output the oscillation times of the oscillators.

[0055] Reference Figure 6 which shows a structural diagram of a synchronous reset unit of the exemplary embodiment of the present application. The synchronous reset unit performs a reset operation on the falling edges of the first clock CK1 and the second clock CK2 after operation, thereby avoiding the uncertainty of asynchronous reset to cause abnormal state of the measurement module.

[0056] Reference Figure 7 which shows a flow chart of a clock jitter measurement method of the exemplary embodiment of the present application. The measurement method is controlled by an automatic control module to execute the measurement circuit described above. The automatic control module can be logically designed by using a hardware description language and realized as a hardware circuit. The measurement method includes the following steps:

[0057] Step S1, adjusting a delay module to generate a first clock signal and a second clock signal;

[0058] Step S2, resetting the measurement module;

[0059] Step S3, measuring the jitter of the to-be-measured clock signal within a given time;

[0060] Step S4, recording the measurement result and updating the measurement times;

[0061] Step S5, if the measurement times reach a preset value, ending the measurement, and if the measurement times do not reach the preset value, returning to Step S2 to continue the measurement.

[0062] In Step S1, the delay module receives the to-be-measured clock signal, delays the to-be-measured clock signal to generate the first clock signal and the second clock signal, and the phase difference between the first clock signal and the second clock signal is one clock period;

[0063] In Step S2, the measurement circuit is initialized. The first D flip-flop, the second D flip-flop and the third D flip-flop DFF3 are reset by the synchronous reset unit, and the data of the first counter and the second counter are emptied.

[0064] In step S3, the first clock signal CK1 and the second clock signal CK2 are sampled in a given time, the jitter signal J_OUT is measured and output. The given time is generally set as a fixed value in the test process. Since the jitter value generally has an empirical range, the larger the jitter, the longer the time generated by PD1 / PD2. In actual operation, the measurement time can be estimated and set according to the maximum jitter.

[0065] In step S4, the measurement result is stored and the measurement times are recorded by the counter.

[0066] In step S5, it is judged whether the measurement times reach a predetermined measurement times, for example, 1000 times. If the predetermined measurement times are not reached, the measurement module is reset and the measurement continues to step S2. If the predetermined measurement times are reached, the measurement is ended.

[0067] After the measurement is ended, the jitter parameters can be calculated according to the stored jitter signal data by the following method. The method comprises: collecting jitter raw data; constructing a probability density function (PDF) based on the jitter raw data; obtaining a probability distribution corresponding to different jitter values according to a curve of the probability density function (PDF); calculating or deducing a peak-to-peak jitter and a root mean square (RMS) jitter based on the probability density function (PDF).

[0068] The foregoing and the following description and the description of the drawings in the specification of the present application are not restrictive, and it is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the scope of the present application claimed is defined by the claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are covered within the scope of the present application.

Claims

1. A digital clock jitter measurement circuit, characterized by, The measurement circuit comprises: a delay module, which receives a clock signal to be measured and generates a first clock signal and a second clock signal, and a phase difference between the first clock signal and the second clock signal is one clock cycle; a measurement module, which comprises a sampling unit, an oscillator control unit, a measurement unit and a counter unit, wherein the measurement unit comprises a slow-frequency oscillator, an intermediate-frequency oscillator and a fast-frequency oscillator, and a first edge detector and a second edge detector, the first edge detector is connected with the slow-frequency oscillator and the intermediate-frequency oscillator, and the second edge detector is connected with the intermediate-frequency oscillator and the fast-frequency oscillator, the counter unit comprises a first counter and a second counter, the first counter is used to count the oscillation times of the slow-frequency oscillator or the intermediate-frequency oscillator, and the second counter is used to count the oscillation times of the intermediate-frequency oscillator or the fast-frequency oscillator; the sampling unit samples the first clock signal and the second clock signal respectively and outputs the sampled signals to the oscillator control unit, when the second clock signal lags behind the first clock signal, the oscillator control unit controls the slow-frequency oscillator and the intermediate-frequency oscillator to start, and the counter unit outputs the value of the first counter; when the second clock signal leads the first clock signal, the oscillator control unit controls the fast-frequency oscillator and the intermediate-frequency oscillator to start, and the counter unit outputs the value of the second counter.

2. The measurement circuit of claim 1, wherein, The sampling unit comprises a first D flip-flop and a second D flip-flop, the first D flip-flop is used to sample the rising edge of the first clock signal, and the second D flip-flop is used to sample the rising edge of the second clock signal.

3. The measurement circuit of claim 2, wherein, The first edge detector is configured to detect the phase relationship of the oscillation clock signals in the slow-frequency oscillator and the intermediate-frequency oscillator, when the oscillation clock signal of the slow-frequency oscillator lags behind the oscillation clock signal of the intermediate-frequency oscillator, the first edge detector outputs a feedback signal PD1, so that the oscillator control unit closes the slow-frequency oscillator and the intermediate-frequency oscillator; when the oscillation clock signal of the intermediate-frequency oscillator lags behind the oscillation clock signal of the fast-frequency oscillator, the second edge detector outputs a feedback signal PD2, so that the oscillator control unit closes the intermediate-frequency oscillator and the fast-frequency oscillator.

4. The measurement circuit of claim 3, wherein, The oscillator control unit comprises an OR gate, a third D flip-flop, a first AND gate and a second AND gate, the inputs of the OR gate are the feedback signals PD1 and PD2 output by the first phase detector and the second phase detector, the inputs of the first AND gate are the Q terminal of the first D flip-flop and the non-Q terminal of the third flip-flop, the inputs of the second AND gate are the Q terminal of the second D flip-flop and the non-Q terminal of the third flip-flop, the output terminal of the OR gate is connected to the input terminal of the third D flip-flop, the output terminal of the first AND gate is connected to the slow-frequency oscillator and the fast-frequency oscillator, and the output terminal of the second AND gate is connected to the intermediate-frequency oscillator.

5. The measurement circuit of claim 2, wherein, The counter unit comprises a phase detector and a selector, the output terminals of the first D flip-flop and the second D flip-flop are connected to the input terminal of the phase detector, the output terminal of the phase detector is connected to the control terminal of the selector, and when the phase detector detects that the phase of the first clock signal leads the second clock, the selector selects the output of the first counter under the control of the phase detector. When the phase detector detects that the phase of the first clock signal lags behind the second clock, the selector selects the output of the second counter under the control of the phase detector.

6. The measurement circuit of claim 1, wherein, The measurement unit comprises a slow intermediate frequency measurement unit and an intermediate fast frequency measurement unit, the slow intermediate frequency measurement unit comprising the slow frequency oscillator, the intermediate frequency oscillator and the first edge detector, and the intermediate fast frequency measurement unit comprising the intermediate frequency oscillator, the fast frequency oscillator and the second edge detector.

7. The measurement circuit of claim 1, wherein, The slow frequency oscillator, the intermediate frequency oscillator and the fast frequency oscillator comprise an adjustable load for adjusting the resolution of the measurement unit.

8. The measurement circuit of claim 3, wherein, The first edge detector and the second edge detector are used for detecting the rising edge or the falling edge of the clock signal.

9. The measurement circuit of claim 4, wherein, The measurement circuit further comprises a synchronous reset unit for synchronously resetting the first D flip-flop, the second D flip-flop and the third D flip-flop DFF3 and emptying the data of the first counter and the second counter.

10. A method of clock jitter measurement, characterized by, The method is controlled by an automatic control module and is performed by the measurement circuit according to any one of claims 1 to 9, and the method comprises the following steps: Step S1, adjusting the delay module to generate a first clock signal and a second clock signal; Step S2, resetting the measurement module; Step S3, measuring the jitter of the to-be-measured clock signal within a given time; Step S4, recording the measurement result and updating the measurement times; Step S5, if the measurement times reach a preset value, ending the measurement, and if the measurement times do not reach the preset value, returning to step S2.

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