Probe card, test method of memory chip, detection circuit and system

Abstract

The application discloses a test method, a detection circuit and a system for a storage chip of a probe card, relates to the technical field of semiconductor testing, and discloses a detection circuit, which comprises a control module and an Ethernet module. The control module comprises a joint test action group interface, the joint test action group interface is connected with the Ethernet module, a test control end of the control module is used for electrical connection with a storage chip, the Ethernet module communicates with a host computer, is used for receiving a first test programming program in an Ethernet protocol format sent by the host computer, and converts the first test programming program into a second test programming program in a joint test protocol format; the control module is used for receiving the second test programming program through the joint test action group interface, and performing read-write function testing on the storage chip based on the second test programming program, so that functional detection of the storage chip on the probe card can be realized, and performance decline of the probe card caused by storage chip failure can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, in particular to a test method for a storage chip of a probe card, a detection circuit and a system. BACKGROUND

[0002] In the field of probe cards, a storage chip is usually configured for each functional block to mainly store version numbers and related information. Therefore, it is necessary to test each storage chip on the probe card before the probe card is shipped.

[0003] Currently, the test of the storage chip on the probe card is mainly in the form of visual inspection and flying probe detection. However, the visual inspection mainly relies on human visual judgment, and the flying probe detection can only detect electrical connections and is difficult to find potential faults. SUMMARY

[0004] The present application provides a test method for a storage chip of a probe card, a detection circuit and a system, which can perform functional detection on the storage chip on the probe card to avoid performance degradation of the probe card due to storage chip failure.

[0005] To achieve the above-mentioned purpose, the present application provides a detection circuit for testing a storage chip on a probe card to be tested, which comprises a control module and an Ethernet module. The control module comprises a Joint Test Action Group (JTAG) interface connected with the Ethernet module. A test control end of the control module is electrically connected with the storage chip:

[0006] The Ethernet module communicates with an upper computer, receives a first test programming program in the format of an Ethernet protocol sent by the upper computer, and converts the first test programming program into a second test programming program in the format of a Joint Test Protocol (JTP).

[0007] The control module receives the second test programming program through the JTAG interface and performs read-write function test on the storage chip based on the second test programming program.

[0008] In an embodiment, the detection circuit further comprises an isolation module, and the test control end of the control module is electrically connected with the storage chip through the isolation module.

[0009] In an embodiment, the integrated circuit bus comprises a serial data line and a serial clock line. The control module connects data interfaces of each storage chip through a shared serial data line, and connects clock interfaces of each storage chip through a shared serial clock line.

[0010] In an embodiment, the isolation module employs a bus-specific signal isolation chip.

[0011] In an embodiment, the detection circuit further comprises a power module, configured to provide power supply for the control module, the isolation module and the Ethernet module.

[0012] In an embodiment, the control module is specifically configured to:

[0013] parse the second test programming to perform the following steps:

[0014] send a write instruction of test data to each of the memory chips, so as to write the test data into each of the memory chips, wherein the test data written into the memory chip is defined as write data;

[0015] read the write data stored in each of the memory chips;

[0016] obtain a read-write function test result according to a comparison result of the write data of each of the memory chips and the test data;

[0017] send the read-write function test result to the host computer through the Ethernet module.

[0018] In addition, to achieve the above object, the present application further provides a test method for memory chips of a probe card, comprising:

[0019] electrically connecting the memory chips on the probe card to be tested to a detection circuit;

[0020] receiving a first test programming in an Ethernet protocol format sent by a host computer through an Ethernet module of the detection circuit, and converting the first test programming into a second test programming in a joint test protocol format;

[0021] receiving the second test programming through a control module of the detection circuit;

[0022] performing read-write function test on each of the memory chips based on the second test programming through the control module;

[0023] wherein the detection circuit is as described above.

[0024] In addition, to achieve the above object, the present application further provides a functional detection system for memory chips of a probe card, comprising:

[0025] a host computer;

[0026] a detection circuit, in communication connection with the host computer, wherein the detection circuit is as described above.

[0027] The detection circuit is also electrically connected with each memory chip of the probe card to be detected.

[0028] The one or more technical solutions provided in the application have at least the following technical effects:

[0029] The detection circuit provided in the application includes a control module and an Ethernet module, the control module includes a joint test action group interface, the joint test action group interface is connected with the Ethernet module, a test control end of the control module is used for electrical connection with the memory chip, the Ethernet module communicates with an upper computer, is used for receiving a first test programming program in an Ethernet protocol format sent by the upper computer, and converts the first test programming program into a second test programming program conforming to a joint test protocol format, the control module is used for receiving the second test programming program through the joint test action group interface, and performs read-write function test on the memory chip based on the second test programming program, the test programming program of the upper computer can be quickly and stably transmitted to the detection circuit, so that the functional detection of the memory chip on the probe card can be realized through the test programming program, so as to avoid the performance decline of the probe card caused by the memory chip failure. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings incorporated in and forming a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0032] Figure 1 The structural diagram provided for an embodiment of the detection circuit of the present application;

[0033] Figure 2 The structural diagram provided for another embodiment of the detection circuit of the present application;

[0034] Figure 3 The flowchart of an embodiment of the test method of the memory chip of the probe card of the present application;

[0035] Figure 4 The structural block diagram of an embodiment of the test system of the memory chip of the probe card of the present application. DETAILED DESCRIPTION

[0036] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0037] Currently, the storage chips on the probe card are tested mainly by visual inspection and flying probe detection. However, the visual inspection mainly depends on manual visual judgment, and the flying probe detection can only detect electrical connection and is difficult to find potential faults.

[0038] To solve the above problems, the embodiments of the present application provide a detection circuit for testing the storage chips on the probe card to be tested. The detection circuit of the embodiments of the present application will be described in detail below in conjunction with the drawings of the specification.

[0039] Please refer to Figure 1 , the detection circuit includes a control module 20 and an Ethernet module 10, the control module 20 includes a Joint Test Action Group interface 201, the Joint Test Action Group interface 201 is electrically connected with the Ethernet module 10, and the test control end of the control module 20 is used for electrical connection with the storage chip: the Ethernet module 10 communicates with the host computer, is used for receiving the first test burning program in the Ethernet protocol format sent by the host computer, and converts the first test burning program into the second test burning program conforming to the Joint Test Protocol format; the control module 20 is used for receiving the second test burning program through the Joint Test Action Group interface 201, and performing read-write function test on each storage chip based on the second test burning program.

[0040] Specifically, the host computer can use a development tool (such as Keil) to compile to generate an executable file (such as.hex format or.bin format) of the control module 20, and obtain the first test burning program in the Ethernet format. The first test burning program contains the logic of the functional test of each storage chip, such as read-write instruction, verification algorithm, etc. Then, the host computer encapsulates the first test burning program into a TCP / IP packet and sends it to the Ethernet module 10 through the Ethernet. After the Ethernet module 10 receives the TCP / IP packet, it parses the first test burning program contained in the packet, and converts it into the second test burning program conforming to the Joint Test Protocol format.

[0041] Exemplarily, the control module 20 adopts a microcontroller of STM32F103C8T6. The control module 20 is built-in Joint Test Action Group (JTAG) interface 201, which is an internationally recognized hardware debugging and testing standard (IEEE 1149.1), originally designed for Boundary Scan Test of integrated circuits (IC), and now widely used for chip debugging, programming and system testing.

[0042] In some embodiments, the Ethernet module 10 is built-in with a conversion chip for realizing conversion between the JTAG protocol and the Ethernet protocol, so as to convert the first test programming sent by the host computer in the Ethernet format into a second test programming in the joint test protocol format. In this process, the Ethernet module 10 only changes the packaging format of data transmission, without modifying the data content of the test programming itself, thereby ensuring the accuracy and integrity of the data. Exemplarily, the conversion chip can be an STM32F407MAC-based conversion chip.

[0043] Specifically, after receiving the second test programming sent by the Ethernet module 10 through the Joint Test Action Group interface 201, the control module 20 parses the second test programming to perform read-write function tests on each storage chip, thereby completing the functional detection of the storage chips on the probe card.

[0044] Please refer to Figure 2 In some embodiments, the detection circuit further comprises an isolation module 30, and the test control end of the control module 20 is electrically connected to the storage chips through the isolation module 30. During the test process and the plug-in and plug-out operation of the storage chips, ripple surges and static electricity are often inevitably generated on the probe card. By setting the isolation module 30, the damage of the detection circuit caused by the ripple surges and static electricity can be reduced, thereby effectively ensuring the stability and reliability of the detection circuit.

[0045] Further, the storage chips include a plurality of storage chips, and the isolation module 30 is electrically connected to each storage chip through an integrated circuit bus (i.e., I2C) and is electrically connected to the test control end of the control module 20 through the integrated circuit bus. Specifically, the integrated circuit bus includes a serial data line SDL and a serial clock line SCL, and the control module 20 is connected to the data interfaces of the storage chips through one shared serial data line SDL, and the control module is connected to the clock interfaces of the storage chips through one shared serial clock line SCL.

[0046] By adopting the bus form to connect the numerous storage chips, only one control module with a set of I2C communication functions needs to be selected as the control core to meet all functional requirements. This design significantly reduces the material cost of the control module. In addition, connecting all the storage chips on the probe card to the isolation module in the form of a bus and then uniformly accessing the control module can enhance the driving capability of the integrated circuit bus I2C in long-distance transmission. On the other hand, in the cross-PCBA communication scene, the isolation module can effectively block the interference of abnormal conditions such as ripple surges and short circuits generated by the probe card on the detection circuit, thereby ensuring the stable operation of the detection circuit.

[0047] Exemplarily, the isolation module 30 adopts a bus special signal isolation chip. The bus special signal isolation chip is an isolation device for I2C bus communication, which can realize electrical isolation (such as voltage isolation, noise isolation) while maintaining signal integrity.

[0048] In some embodiments, referring to Figure 2 The detection circuit further comprises a power module 40 electrically connected with the control module 20. The power module 40 is configured to provide power supply for the control module 20, the isolation module 30 and the Ethernet module 10. By setting the power module 40, stable power support can be provided for the entire detection circuit, so as to ensure that the control module 20, the isolation module 30 and the Ethernet module 10 can work normally.

[0049] In some embodiments, the control module 20 is specifically configured to:

[0050] The second test programming is parsed to perform the following steps:

[0051] A write instruction of the test data is sent to each storage chip, so as to write the test data into each storage chip respectively, wherein the test data written into the storage chip is defined as write data;

[0052] The write data stored in each storage chip is read;

[0053] The read-write function test result is obtained according to the comparison result of the write data of each storage chip and the test data;

[0054] The read-write function test result is sent to the host computer through the Ethernet module.

[0055] Specifically, after receiving the second test programming through the Joint Test Action Group interface, the control module programs the second test programming into the storage area of the control module. Then, the control module parses the second test programming to extract the test instruction and the test data. According to the test instruction, the control module sends a write instruction of the test data to each storage chip through the integrated circuit bus, so as to write the test data into each storage chip respectively. After the writing is completed, the control module sends a read instruction of the test data to each storage chip through the integrated circuit bus, and receives the write data sent by each storage chip through the integrated circuit bus. Then, the control module compares the received write data with the original test data, and obtains the read-write function test result according to the comparison result. Specifically, if the write data of each storage chip is consistent with the original test data, it is determined that the read-write function of each storage chip on the probe card under test is normal, and if the write data of any storage chip is inconsistent with the original test data, it is determined that the read-write function of the storage chip is abnormal. Finally, the control module sends the read-write function test result of each storage chip to the host computer through the Ethernet module, and the user can view the test result on the host computer.

[0056] In some embodiments, the Ethernet module is built-in with a security chip, and a decryption key is stored in a storage area of the security chip. When the host computer sends an encrypted data packet in Ethernet format to the Ethernet module, the encrypted data packet is obtained by encrypting and packaging the first test programming, and the encryption key and the decryption key are paired. The Ethernet module first receives the encrypted data packet and performs preliminary verification on the encrypted data packet, such as checking whether the header information of the encrypted data packet is complete and whether the checksum is correct. If the verification fails, the encrypted data packet is discarded and an error feedback is sent to the host computer; if the verification passes, the encrypted data packet is passed to the security chip for processing. After receiving the encrypted data packet, the security chip decrypts the encrypted data packet using the decryption key stored in its internal storage area to obtain the first test programming in Ethernet protocol format, and then converts the first test programming into a second test programming in joint test protocol format.

[0057] Further, during the decryption process, the security chip performs real-time verification on the first test programming data obtained after decryption, such as using a cyclic redundancy check (CRC) algorithm to verify the first test programming data, to ensure the integrity and accuracy of the decrypted data. If an error occurs during decryption, such as key mismatch or data corruption, the security chip sends a decryption failure message to the host computer and discards the encrypted data packet.

[0058] In some embodiments, the detection circuit is integrated on a circuit board, the circuit board is packaged in a shell, the circuit board is fixed to the bottom plate of the shell, the shell further includes an upper cover plate fixed by anti-disassembly screws, a micro switch is arranged in the shell, the micro switch is installed on the inner side of the upper cover plate, the detection pin of the security chip is connected to the normally closed contact of the micro switch through a flexible circuit, and the detection pin of the security chip is also connected to the control module; the control module is further configured to: when it is detected that the micro switch is disconnected, execute a key erasing mechanism, and the key erasing mechanism includes controlling the security chip to execute an erasing operation on the decryption key.

[0059] The micro switch is a kind of switch with small contact interval and quick action mechanism, which performs switching action with specified stroke and specified force, and is covered by a shell, and has a driving rod outside. Because the contact interval of the switch is small, it is called micro switch, also called sensitive switch.

[0060] Specifically, the detection circuit is integrated on a circuit board, which is firmly installed on the bottom plate by screws or other fixing methods. The upper cover plate is matched in shape and size with the bottom plate. The upper cover plate is fixed on the bottom plate by anti-disassembly screws. The micro switch is installed on the inner side of the upper cover plate, and when the upper cover plate is normally installed, the micro switch is in a closed state; when the upper cover plate is illegally disassembled, the micro switch will immediately open. The normally closed contact of the micro switch is connected to the detection pin of the security chip through a flexible circuit. The flexible circuit has good flexibility and reliability, and can maintain stable electrical connection during the opening and closing of the upper cover plate. At the same time, the detection pin of the security chip is also connected to the control module. The control module monitors the level state of the detection pin of the security chip in real time through internal signal lines. After the control module is powered on, it will immediately start monitoring the level state of the detection pin of the security chip. The monitoring process adopts a timing polling method, and the level value of the detection pin is read once every certain time interval (such as 100 milliseconds). The control module compares the read level value with the preset normal level value. Under normal circumstances, when the upper cover plate is normally installed, the micro switch is in a closed state, and the level value of the detection pin is low; when the upper cover plate is illegally disassembled, the micro switch is open, and the level value of the detection pin is high. If the control module detects that the level value of the detection pin changes from low to high, i.e. the micro switch is open, the control module determines that an illegal disassembly event has occurred. The control module will immediately send an erase instruction to the security chip. After receiving the erase instruction, the security chip will start the internal erase program to erase the sensitive data such as decryption keys stored therein. At the same time, the control module will send a tamper-proof alarm information to the upper computer to inform the upper computer that the detection circuit has an illegal disassembly event. After receiving the alarm information, the upper computer can take corresponding measures, such as recording alarm logs, stopping subsequent test operations, etc.

[0061] Through the above implementation, the security and reliability of the detection circuit can be further improved, illegal disassembly and data leakage can be effectively prevented, and the correct transmission and execution of the test and programming program can be ensured.

[0062] In some embodiments, the control module is specifically configured to: when detecting that the micro switch is open, send a verification request to the upper computer, the verification request being used to verify the identity information of the user, and if the control module receives a verification failure prompt information sent by the upper computer, execute the key erasing mechanism.

[0063] Further, the control module is further configured to: if the control module receives a verification correct prompt information sent by the upper computer, suspend the key erasing mechanism.

[0064] Specifically, after receiving the verification request, the host computer prompts the user to input the identity number. After the user inputs the identity number, the host computer verifies the identity number. If the identity number is correct, the host computer sends a correct verification prompt information to the control module; if the identity number is incorrect, the host computer sends an incorrect verification prompt information to the control module.

[0065] By adding the identity verification link on the basis of the original detection of illegal disassembly based on microswitch, when illegal disassembly is detected, the key erasing operation is not directly executed, but identity verification is performed first. This design avoids the key erasing error caused by misoperation (such as accidental triggering of the microswitch during normal maintenance), and also ensures that only the legal personnel who have passed the identity verification can suspend the key erasing mechanism and operate the detection circuit, effectively preventing unauthorized illegal access and damage.

[0066] Further, the control module is further configured to: after receiving the maintenance operation completion information sent by the host computer, restore the key erasing mechanism.

[0067] Through the scheme, if the illegal disassembly event occurs again subsequently, the security chip will execute the key erasing operation, ensuring the security of the key.

[0068] Correspondingly, the embodiment of the application also provides a test method for a storage chip of a probe card, applied to the detection circuit provided in the above embodiment. The detection circuit includes a control module and an Ethernet module. The control module includes a joint test action group interface, which is connected with the Ethernet module. The test control end of the control module is configured to be electrically connected with the storage chip. The Ethernet module is also in communication connection with a host computer. Please refer to Figure 3 The test method for the storage chip of the probe card includes steps S10-S40:

[0069] S10, electrically connecting the storage chip on the to-be-tested probe card with the detection circuit;

[0070] S20, receiving the first test programming program in the Ethernet protocol format sent by the host computer through the Ethernet module, and converting the first test programming program into a second test programming program in the joint test protocol format;

[0071] S30, receiving the second test programming program through the joint test action group interface of the control module;

[0072] S40, performing read-write function test on each storage chip based on the second test programming program through the control module.

[0073] In some embodiments, before electrically connecting the storage chip on the probe card under test with the detection circuit, further comprising: performing voltage detection at each level of the detection circuit. Specifically, connecting the detection circuit with the power supply device. After the detection circuit is connected with the power supply, using a multimeter to detect the output voltage of the power module in the detection circuit. Then, comparing the detected output voltage value with the rated working voltage of each module (including the isolation module, the control module, etc.) in the detection circuit. If the output voltage value is within the allowable error range of the rated working voltage of each module (usually ± 5% of the rated voltage), it means that the output voltage of the power module is normal, and each module can obtain normal working voltage; if the output voltage value exceeds the allowable error range, it is necessary to check whether the power module is faulty, such as whether the capacitor in the power supply circuit is damaged, whether the voltage stabilizing chip is working normally, etc., and timely maintenance or replacement.

[0074] In some embodiments, before electrically connecting the storage chip on the probe card under test with the detection circuit, further comprising: testing whether the host computer and the detection circuit can normally communicate. Specifically, the host computer can send a heartbeat packet to the detection circuit, and detect whether the response data returned by the detection circuit is received within a preset time period. If yes, it means that the host computer and the detection circuit can normally communicate; if no, it means that the current host computer and the detection circuit cannot normally communicate, and it is necessary to check whether the communication line is connected normally, whether the communication parameter setting is correct, whether the Ethernet module of the detection circuit is faulty, etc., and perform corresponding troubleshooting and processing.

[0075] In some embodiments, the Ethernet module includes a security chip, and the test method of the storage chip of the probe card further comprises:

[0076] Receiving, by the Ethernet module, an encrypted data packet in Ethernet format sent by the host computer, wherein the encrypted data packet is obtained by encrypting and packaging the first test burning program by using an encryption key;

[0077] Transferring, by the Ethernet module, the encrypted data packet to the security chip for processing;

[0078] After receiving the encrypted data packet by the security chip of the Ethernet module, decrypting the encrypted data packet by using a decryption key set in the internal storage area thereof to obtain the first test burning program in Ethernet protocol format, wherein the encryption key and the decryption key are paired;

[0079] Converting, by the Ethernet module, the first test burning program into a second test burning program in Joint Test Protocol format.

[0080] By encrypting the test burning program sent by the host computer during data transmission to form an encrypted data packet, and then transmitting it through the Ethernet module, this encrypted transmission method can effectively prevent data from being stolen or tampered with during transmission. At the same time, since the encryption key is used in pairs with the decryption key set in the internal storage area of the security chip, only the security chip with the correct decryption key can decrypt the encrypted data packet. This key pairing mechanism further improves the security of data transmission, preventing illegal devices from obtaining and decrypting test data, effectively resisting external attacks and malicious intrusion.

[0081] In some embodiments, the detection circuit is integrated on a circuit board, the circuit board is packaged in a shell, the circuit board is fixed to the bottom plate of the shell, the shell further comprises an upper cover plate fixed by an anti-disassembly screw, a micro switch is arranged in the shell, the micro switch is installed on the inner side of the upper cover plate, the detection pin of the security chip is connected to the normally closed contact of the micro switch through a flexible circuit, and the detection pin of the security chip is also connected to the control module; the test method of the storage chip of the probe card further comprises: when it is detected that the micro switch is disconnected, the security chip is controlled to perform an erasing operation on the decryption key.

[0082] By automatically erasing the decryption key when illegal disassembly is detected, the security of the key is ensured, even if the detection circuit is illegally obtained, the attacker cannot obtain the valid decryption key, so as to cannot obtain or tamper with the test data, effectively protecting the security of the test process and the confidentiality of the data.

[0083] Correspondingly, please refer to Figure 4 The embodiments of the present application also provide a functional detection system for a storage chip of a probe card, comprising a host computer M2 and a detection circuit M1, wherein the detection circuit M1 is in communication connection with the host computer M2, and the detection circuit M1 adopts the detection circuit provided in the above embodiments; the detection circuit M1 is also electrically connected with each storage chip of the probe card to be tested.

[0084] The detection circuit uses the detection circuit provided in the above embodiments, and its structure and implementation principle are consistent with those of the above embodiments, and will not be repeated here.

[0085] The above only describes some embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structural transformation made by using the contents of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A detection circuit, characterized in that, The detection circuit is used to test multiple memory chips on the probe card under test. The detection circuit includes a control module and an Ethernet module. The control module includes a Joint Test Action Group (TTAP) interface, which is connected to the Ethernet module. The test control terminal of the control module is used to electrically connect to each of the memory chips. The Ethernet module communicates with the host computer. The Ethernet module has a built-in security chip, and the security chip stores the decryption key in its storage area. The Ethernet module is used to receive encrypted data packets in Ethernet protocol format sent by the host computer. The encrypted data packets are data packets obtained by encrypting and encapsulating the first test programming program. The Ethernet module is also used to decrypt the encrypted data packet using the decryption key stored in the security chip to obtain the first test programming program, and to convert the first test programming program into a second test programming program that conforms to the joint test protocol format. The control module is used to receive the second test programming program through the joint test action group interface, and to perform read and write function tests on each of the memory chips based on the second test programming program. The detection circuit is integrated on a circuit board, which is encapsulated in a housing. A micro switch is provided inside the housing. The detection pin of the safety chip is connected to the normally closed contact of the micro switch through a flexible circuit. The detection pin of the safety chip is also connected to the control module. The control module is also used to: when the micro switch is detected to be open, send a verification request to the host computer, the verification request being used to verify the user's identity information; If the control module receives a verification failure message from the host computer, it executes a key erasure mechanism, which includes controlling the security chip to erase the decryption key; if the control module receives a verification success message from the host computer, it pauses the key erasure mechanism. The control module is also used to restore the key erasure mechanism after receiving maintenance operation completion information sent by the host computer.

2. The detection circuit as described in claim 1, characterized in that, The detection circuit also includes an isolation module, and the test control terminal of the control module is electrically connected to the memory chip through the isolation module.

3. The detection circuit as described in claim 2, characterized in that, The isolation module is electrically connected to each of the memory chips via an integrated circuit bus, and is also electrically connected to the test control terminal of the control module via the integrated circuit bus.

4. The detection circuit as described in claim 3, characterized in that, The integrated circuit bus includes a serial data line and a serial clock line. The control module is connected to the data interface of each memory chip through a shared serial data line, and the control module is connected to the clock interface of each memory chip through a shared serial clock line.

5. The detection circuit as described in claim 3, characterized in that, The isolation module uses a dedicated bus signal isolation chip.

6. The detection circuit as described in claim 3, characterized in that, The detection circuit also includes a power supply module, which provides power to the control module, the isolation module, and the Ethernet module.

7. The detection circuit as described in claim 1, characterized in that, The control module is specifically used for: The second test programming program is parsed to perform the following steps: Send a write instruction for test data to each of the memory chips to write the test data to each of the memory chips respectively, wherein the test data written to the memory chips is defined as write data; Read the write data stored in each of the aforementioned memory chips; The read / write function test results are obtained based on the comparison results between the written data and the test data of each memory chip. The test results of the read / write function are sent to the host computer via the Ethernet module.

8. The detection circuit as described in claim 1, characterized in that, The memory chip is an electrically erasable programmable read-only memory chip.

9. A method for testing the memory chip of a probe card, characterized in that, Applied to the detection circuit as described in any one of claims 1 to 8, the detection circuit includes a control module and an Ethernet module, the control module includes a Joint Test Action Group (JTA) interface connected to the Ethernet module, and the test control terminal of the control module is used for electrical connection to the memory chip, the method comprising: The multiple memory chips on the probe card to be tested are electrically connected to the detection circuit respectively; The Ethernet module receives encrypted data packets in Ethernet protocol format sent by the host computer. The encrypted data packets are data packets obtained by encrypting and encapsulating the first test programming program. The encrypted data packets are decrypted using the decryption key stored in the security chip to obtain the first test programming program. The first test programming program is then converted into a second test programming program that conforms to the joint test protocol format. The second test programming program is received through the joint test action group interface of the control module; The control module performs read / write function tests on each of the memory chips based on the second test programming program. The method further includes: When the micro switch is detected to be open, a verification request is sent to the host computer. The verification request is used to verify the user's identity information. If the control module receives a verification failure message from the host computer, it executes the key erasure mechanism. If the control module receives a verification confirmation message from the host computer, it will pause the key erasure mechanism. After receiving the maintenance operation completion message from the host computer, the key erasure mechanism is restored.

10. A testing system for a probe card's memory chip, characterized in that, include: Host computer; A detection circuit is communicatively connected to the host computer, and the detection circuit is the detection circuit as described in any one of claims 1 to 8; The detection circuit is also electrically connected to each memory chip of the probe card under test.

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