FPGA daisy chain communication structure and communication system

Abstract

The invention discloses a field programmable gate array (FPGA) daisy chain communication structure and a communication system, relates to the technical field of communication, and solves the problems that interfaces and protocols are not standardized and are difficult to develop and debug due to the fact that sub-function modules are connected by adopting a star topology structure in an existing FPGA. The key points of the technical scheme are as follows: a UART (Universal Asynchronous Receiver / Transmitter) interface is adopted as a physical interface between an upper computer and an FPGA (Field Programmable Gate Array) in a communication structure, and sub-function modules in the FPGA are connected in a daisy chain mode; according to the communication structure adopted by the invention, the upper computer can directly communicate with each sub-function module through a standardized interface and a protocol, each sub-function module can be independently developed and debugged, and the communication structure is suitable for FPGA design in the field of electronic product testing.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more particularly to an FPGA daisy chain communication structure and a communication system. Background Art

[0002] like Figure 1 As shown, Figure 1 The topology diagram of the communication between the functional modules within an existing FPGA and the host computer is shown below. The communication topology between the functional modules within an existing FPGA and the host computer generally follows a "host computer - central module - multiple sub-functional modules" structure. The host computer is connected to the single central module within the FPGA via a physical link such as a serial port or network port. The central module is responsible for receiving data from the host computer, sending responses from the sub-functional modules, parsing and encapsulating communication packets, and pairing the sub-functional modules with bus interfaces. The remaining sub-functional modules are connected to the central module via an internal bus to transmit commands and responses from the host computer.

[0003] The star topology of "central module-multiple sub-function modules" used in existing FPGAs has the following drawbacks: 1. Unstandardized interfaces and protocols: The communication protocol between the host computer and the FPGA was not calibrated, resulting in differences between different projects. As a result, the protocol parsing part of the central module could not be solidified and needed to be reprogrammed according to the specific protocol of the project. The bus between the central module and each sub-functional module was also not calibrated, and the requirements of different sub-modules varied, resulting in the central module interface also needing to be adapted according to the sub-module interface conditions. Due to differences in functional requirements between different projects, each sub-functional module had different interface requirements, resulting in the need to reconstruct the program code of the central module and sub-functional modules, resulting in a long development cycle and high labor consumption.

[0004] 2. The high coupling between the central module and sub-functional modules leads to development and debugging difficulties: The central module is the bridge between the host computer and the sub-functional modules. To debug the sub-functional modules, the correctness of the central module must be ensured. The central module and sub-functional modules are interdependent, and program debugging can only be carried out in a coordinated manner, which is difficult and time-consuming. The tight coupling between functional modules leads to poor program code repeatability and loss of the module's sustainable optimization capability. If the sub-functional modules and the central module are not in the same clock domain, cross-clock domain processing will occur. When the number of interfaces is large, it is very time-consuming and labor-intensive, and it is also difficult to troubleshoot problems.

[0005] In the field of electronic product testing, each sub-module needs to complete specific interface or service testing functions. Communication between the host computer and these sub-modules requires low speed and real-time performance. If the FPGA were to use a star topology to interconnect these sub-modules, multiple communication protocols would exist between the host computer, resulting in complex and difficult-to-coordinate bus interfaces. Designers would be forced to design and implement programs based on different projects and requirements, resulting in poor inheritability and uncertain code reliability. This also means that the same modules would need to be repeatedly designed and tested.

[0006] To this end, the present application provides an FPGA daisy chain communication structure and communication system to solve the above problems. Summary of the Invention

[0007] The purpose of this application is to provide an FPGA daisy chain communication structure and communication system to solve the problem that the existing FPGA uses a star topology structure to connect the sub-functional modules, resulting in non-standard interfaces and protocols and difficulties in development and debugging; the communication structure proposed in this application uses a UART interface as the physical interface between the host computer and the FPGA, and the sub-functional modules inside the FPGA are connected in a daisy chain manner; the communication structure adopted in this application enables direct communication between the host computer and the sub-functional modules through standardized interfaces and protocols, and each sub-functional module can be independently developed and debugged, which is suitable for FPGA design in the field of electronic product testing.

[0008] The present application first provides an FPGA daisy-chain communication structure, comprising: multiple FPGA internal function modules, which are serially connected in a daisy-chain topology and communicate externally through a UART interface, wherein the transmit port of the previous FPGA internal function module is connected to the receive port of the next FPGA internal function module; each FPGA internal function module comprises: a TMIP interface module and a sub-function module, wherein the TMIP interface module and the sub-function module communicate via a TMI interface, the TMIP interface module is configured to generate and parse data frames according to the TMIP protocol; the sub-function module is configured to execute functions configured in registers in response to instructions in the data frames; wherein the TMIP protocol stipulates that: each FPGA internal function module forwards data frames that do not match its own ID, and responds to data frames that match its own ID and updates the forwarded content.

[0009] In one possible implementation, the data frame includes: a frame header, a module ID, a command word, a data length, a register address, a data packet, and a frame tail; wherein the frame header is a data frame start flag, the module ID is the ID of the sub-function module on the daisy chain, the command word is an operation instruction represented by different values, and at least includes: a NOP operation, a read operation, a write operation, and a command response; the data length is the number of data packets in the read and write operations; the register address is the register starting address of the sub-function module in the read and write operations; the data packet is the data required for the read and write operations; all data words in the data packet are filled with 0 during the read operation; and all data words in the data packet are filled with write data by default during the write operation; and the frame tail is a data frame end flag.

[0010] In a possible implementation manner, the bit width occupied by the module ID determines the upper limit number of sub-functional modules mounted in the daisy chain topology.

[0011] In one possible implementation, the TMIP protocol also stipulates that when each FPGA internal functional module responds to a data frame that matches its own ID and updates the forwarding content, the data packet is updated to the response data generated by the sub-functional module in response to the operation instruction, and the command word representing the read operation and write operation is updated to the command word representing the command response.

[0012] In one possible embodiment, the TMIP interface module is specifically used to: receive input data and convert the input data into parallel data; receive a frame header and perform frame header detection until a correct frame header is detected; receive a module ID and detect whether the module ID matches the corresponding sub-function module ID; if the module ID matches the corresponding sub-function module ID, sequentially receive a command word, data length, register address, data packet, and frame trailer, wherein the data in the data packet is received one by one according to the data length; send the command word, register address, and data packet to the sub-function module and receive response data returned by the sub-function module; use the frame header, module ID, command word, data length, register address, and frame trailer as forwarded data, wherein when the command word indicates a read operation or a write operation, it is modified to a command response; update the data packet according to the response data, and convert the forwarded data and the response data into a serial data frame for output.

[0013] In one possible embodiment, the TMIP interface module includes: a data transceiver module, a protocol parsing module and a data buffer module; the data transceiver module is used to convert the received input data into parallel data and send it to the protocol parsing module, and convert the data sent by the data buffer module into serial data output; the protocol parsing module is used to parse the data frame in the input data, and when the module ID of the data frame matches the sub-function module ID, send the command word, register address and data packet to the sub-function module, and forward the other content of the data frame to the data buffer module; the data buffer module is used to receive the forwarded content of the protocol parsing module and the response data of the sub-function module when the module ID of the data frame matches the sub-function module ID, and forward them to the data transceiver module.

[0014] In a possible implementation manner, the protocol analysis module is further configured to generate a handshake signal, and send the handshake signal together with the command word, register address, and data packet to the sub-functional module.

[0015] In one possible implementation, the sub-function module includes: a register mapping module and a function implementation module; the register mapping module is used to map the register address to a specific register; the function implementation module is used to execute the register configuration parameters to implement the corresponding function of the sub-function module.

[0016] In one possible implementation, the sub-functional module receives through the TMI interface: a handshake signal i_valid, a command word i_cmd, a register address i_addr, and a data packet i_data. When the handshake signal i_valid is high, the other three signals are valid inputs. The sub-functional module outputs through the TMI interface: a handshake signal o_valid and response data o_data. When the handshake signal o_valid is high, the response data o_data is a valid output. The handshake signals i_valid and o_valid only maintain a high level within one clock cycle.

[0017] The present application also provides an FPGA daisy chain communication system, which includes the FPGA daisy chain communication structure as described above.

[0018] Compared with the existing technology, the present application has the following beneficial effects: a daisy chain communication structure is adopted to replace the original central module star topology structure, the host computer and each FPGA internal functional module can communicate directly through a standard interface and protocol, and each FPGA internal functional module can be connected to an external host computer through a UART interface for independent debugging and operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 It is a topological diagram of the communication between the existing FPGA internal functional modules and the host computer; Figure 2 A schematic diagram of the FPGA daisy chain communication structure provided in an embodiment of the present application; Figure 3 A schematic diagram of an FPGA daisy chain communication structure provided in an embodiment of the present application; Figure 4 A schematic diagram of a TMIP data frame provided in an embodiment of the present application; Figure 5 A flowchart of the TMIP interface module provided in the embodiment of the present application; Figure 6 Functional block diagram of the TMIP interface module and sub-function modules provided in the embodiment of the present application; Figure 7 This is a code diagram for the definition of the external clock test function module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] Hereinafter, the terms "include" or "may include" as used in various embodiments of the present application indicate the presence of the claimed function, operation, or element, and do not limit the addition of one or more functions, operations, or elements. In addition, as used in various embodiments of the present application, the terms "include", "have" and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing or the possibility of adding one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing.

[0021] In various embodiments of the present application, the expression "or" or "at least one of B or / and C" includes any or all combinations of the words listed simultaneously. For example, the expression "B or C" or "at least one of B or / and C" may include B, may include C, or may include both B and C.

[0022] The terms used in the various embodiments of the present application are only used for the purpose of describing specific embodiments and are not intended to limit the various embodiments of the present application. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise specified, all terms used herein (including technical terms and scientific terms) have the same meaning as those commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in the various embodiments of the present application.

[0023] In order to make the objectives, technical solutions and advantages of this application more clear, the present application is further described in detail below in conjunction with examples and drawings. The schematic implementation methods of this application and their descriptions are only used to explain this application and are not intended to limit this application.

[0024] See Figure 2 As shown, Figure 2 A schematic diagram of an FPGA daisy-chain communication structure provided in an embodiment of the present application. The structure includes: multiple FPGA internal function modules, which are serially connected in a daisy-chain topology and communicate externally via a UART interface, wherein the transmit port of a preceding FPGA internal function module is connected to the receive port of a succeeding FPGA internal function module; each FPGA internal function module includes: a TMIP interface module and a sub-function module, wherein the TMIP interface module and the sub-function module communicate via a TMI interface; the TMIP interface module is configured to generate and parse data frames according to the TMIP protocol; the sub-function module is configured to execute functions configured in registers in response to instructions in the data frames; wherein the TMIP protocol stipulates that each FPGA internal function module forwards data frames that do not match its own ID, and responds to data frames that match its own ID and updates the forwarded content.

[0025] Specifically, if Figure 2As shown, each FPGA internal functional module consists of a TMIP interface module and a sub-functional module. The sub-functional modules are interconnected with the TMIP interface module via TMI interfaces (TMI_S and TMI_M). The first TMIP interface module's rxd interface receives the external input signal i_rxd via the UART interface. The second TMIP interface module's rxd interface connects to the previous TMIP interface module's txd interface. The final TMIP interface module's txd interface transmits the external output signal o_txd via the UART interface, thus implementing a daisy-chain topology. The TMIP interface module is primarily responsible for parsing data packets from the external control end. If the parsed data frame instruction matches the associated sub-functional module ID, the TMIP interface module communicates with the sub-functional module via the TMI interface, prompting the sub-functional module to execute the corresponding function and transmit response data. If the parsed data frame instruction does not match the associated sub-functional module ID, the TMIP interface module directly forwards the data frame.

[0026] See Figure 3 As shown, Figure 3 This is a schematic diagram of an FPGA daisy-chain communication structure used in an embodiment of the present application. In the figure, a host computer is connected to FPGA1 via a UART interface. FPGA1's sub-function modules include: a DDR3 module, an SPI_S module, an RST module, an FGPIO module, a UART test module, a logic version module, an XADC module, a DAC module, and an ADC module. Each sub-function module is sequentially mounted to the communication chain via the TMIP interface module. FPGA1 is also connected to an external FPGA2 and DSP via a UART interface. Sub-function modules within FPGA2 and DSP can also be mounted to the daisy communication link via the TMIP interface module to expand the daisy chain, ultimately returning to FPGA1 to form a closed loop and communicate with the host computer, enabling daisy-chain communication between multiple sub-function modules within the FPGA and an external control terminal (host computer, other FPGAs, ARM, DSP, PS, etc.). It should be noted that the figure also exemplifies other modules commonly used in FPGA design, such as the GPIO_SCAN module, which will not be detailed here. In the figure, FPGA1_RXD represents the input of FPGA1, FPGA1_TXD represents the output of FPGA1, FPGA2_RXD represents the input of FPGA2, FPGA2_TXD represents the output of FPGA2, DSP_RXD represents the input of DSP, and DSP_TXD represents the output of DSP.

[0027] The improvement presented in this application is to design a daisy-chain topology within the FPGA, replacing the existing star topology. This allows daisy-chain communication between multiple sub-modules and an external control terminal (host computer, other FPGAs, ARM, DSP, PS, etc.) through the TMIP interface module, achieving interface and protocol standardization and avoiding central module coupling. The TMIP interface module enables direct external communication via a UART (Universal Asynchronous Receiver / Transmitter) interface. Sub-modules are described in registers, allowing for customized functionality for each sub-module. Development and debugging of each sub-module can be completed independently, reducing development and debugging complexity.

[0028] See Figure 4 As shown, Figure 4 A schematic diagram of a TMIP data frame provided in an embodiment of the present application. In one possible implementation, the data frame includes: a frame header, a module ID, a command word, a data length, a register address, a data packet, and a frame trailer. The frame header marks the start of the data frame; the module ID is the ID of the sub-function module on the daisy chain; the command word is an operation instruction represented by different values, including at least: a NOP operation, a read operation, a write operation, and a command response; the data length is the number of data packets in a read or write operation; the register address is the register starting address of the sub-function module in the read or write operation; the data packet is the data required for the read or write operation; all data words in the data packet are padded with 0s during a read operation, and all data words in the data packet are padded with write data by default during a write operation; and the frame trailer marks the end of the data frame.

[0029] Specifically, if Figure 4 The figure shows a schematic diagram of a data frame for a NOP operation (NOP), a read operation (READ), a write operation (WRITE), and a command response (RESPONSE). The data frame includes a frame header (0x5A55), a module ID (DADD[7:0]), a command word (CMD[7:0]), a data length (DLEN[15:0]), a register address (RADD[15:0]), a data packet (n × DATA[15:0]), and a frame trailer (0xA5AA). The module ID and command word each occupy 8 bits, while the frame header, data length, register address, and frame trailer each occupy 16 bits, and the data packet occupies n × 16 bits.

[0030] Table 1 shows the structure of a TMIP data frame. The frame header consists of two 16-bit bytes, with a fixed value of 0x5A55 representing the start of the data frame. The module ID consists of one 8-bit byte, which can represent the ID of each sub-functional module under test in the daisy chain. The command word consists of one 8-bit byte, with 0 representing a NOP operation, 1 representing a read operation, 2 representing a write operation, and 3 representing a command response. Other operation instructions can be expanded. The data length consists of two 16-bit bytes, representing the number of data packets in a read or write operation, with a maximum of 65,535 16-bit data packets. The register address consists of two 16-bit bytes, representing the register starting address of the device in a read or write operation. The data packet consists of bytes 2 to 131,070, representing the data required for read and write operations. All data in a read operation is padded with 0s, and all data in a write operation is padded with write data by default. The sub-functional module under test can also redefine this data. The frame trailer consists of two 16-bit bytes, with a fixed value of 0xA5AA, representing the end of the data frame.

[0031] Table 1 TMIP data frame composition

[0032] Furthermore, the bit width occupied by the module ID determines the upper limit number of sub-functional modules mounted in the daisy chain topology.

[0033] Specifically, when the module ID occupies 8 bits, the range that can be represented is 0x00-0xFF. 0x00 is generally not used. A daisy chain can connect up to 255 sub-function modules.

[0034] It should be noted that the more devices on the daisy chain, the greater the communication delay. Therefore, the FPGA daisy chain communication structure provided in this application is more suitable for scenarios where real-time communication requirements are not high, such as FPGA design in the field of electronic product testing.

[0035] Furthermore, the TMIP protocol also stipulates that when each FPGA internal functional module responds to a data frame that matches its own ID and updates the forwarding content, the data packet is updated to the response data generated by the sub-functional module in response to the operation instruction, and the command word representing the read operation and write operation is updated to the command word representing the command response.

[0036] Specifically, when updating the forwarding content, the data packet in the data frame is updated to the response data generated by the corresponding sub-function module, the command word representing the read operation and the write operation is updated to the command word representing the command response, and the rest of the data frame is directly forwarded after being stored.

[0037] See Figure 5 As shown, Figure 5A flowchart of the TMIP interface module provided in an embodiment of the present application. In one possible implementation, the TMIP interface module is specifically configured to: receive input data and convert the input data into parallel data; receive a frame header and perform frame header detection until a correct frame header is detected; receive a module ID and detect whether the module ID matches the corresponding sub-function module ID; if the module ID matches the corresponding sub-function module ID, sequentially receive a command word, data length, register address, data packet, and frame trailer, wherein the data in the data packet is received one by one according to the data length; send the command word, register address, and data packet to the sub-function module and receive response data returned by the sub-function module; use the frame header, module ID, command word, data length, register address, and frame trailer as forwarded data, wherein the command word is modified to a command response when it indicates a read operation or a write operation; update the data packet according to the response data, and convert the forwarded data and the response data into a serial data frame for output.

[0038] Specifically, if Figure 5 As shown, the TMIP interface module only responds to data frames with the same ID as its own sub-module. Data frames with non-self-identified sub-module IDs are forwarded directly without any processing. During the response data frame processing, only the data packet is updated based on the sub-module's response data. When the command word indicates a read or write operation, it is changed to a response command. The rest of the data is forwarded directly.

[0039] See Figure 6 As shown, Figure 6 This is a functional block diagram of the TMIP interface module and sub-function modules provided in an embodiment of the present application. Furthermore, the TMIP interface module includes: a data transceiver module, a protocol parsing module, and a data buffer module; the data transceiver module is configured to convert received input data into parallel data and send it to the protocol parsing module, and to convert data sent by the data buffer module into serial data for output; the protocol parsing module is configured to parse data frames in the input data and, if the module ID of the data frame matches the sub-function module ID, send the command word, register address, and data packet to the sub-function module and forward the rest of the data frame to the data buffer module; and the data buffer module is configured to receive the forwarded content from the protocol parsing module and the response data from the sub-function module and forward them to the data transceiver module if the module ID of the data frame matches the sub-function module ID.

[0040] Furthermore, the protocol analysis module is also used to generate a handshake signal, and send the handshake signal together with the command word, register address and data packet to the sub-functional module.

[0041] Specifically, if Figure 6As shown, each FPGA internal functional module consists of a TMIP interface module and a sub-functional module. Data is transmitted between the TMIP interface module and the sub-functional module via the TMI interface. The TMI interface is called TMI_M on the TMIP interface module side and TMI_S on the sub-functional module side. Signals transmitted via the TMI interface include command words i_cmd, register addresses i_addr, data packets i_data, handshake signals i_valid and o_data, and response data o_valid. The TMIP interface module consists of a data transceiver module (serial-to-parallel uart_rx, parallel-to-serial uart_tx), a protocol parser module tmip_parse, and a data buffer module data_fifo. The TMIP interface module can directly connect to the UART interface to receive input data i_rxd and transmit output data o_txd.

[0042] See Figure 6 As shown, Figure 6 This is a functional block diagram of the TMIP interface module and sub-function modules provided in an embodiment of the present application. In one possible implementation, the sub-function modules include: a register mapping module and a function implementation module; the register mapping module is used to map register addresses to specific registers; and the function implementation module is used to execute register configuration parameters to implement the corresponding functions of the sub-function modules.

[0043] Specifically, see Figure 7 As shown, Figure 7 The code diagram of the definition of the external clock test function module provided in the embodiment of the present application. Take an external clock test function module as an example to illustrate the definition of the sub-function module. Figure 7 As shown in the figure, in the external clock test function module, the define macro includes the externally visible register definitions and the supported command list of the external clock test function module. The figure provides four register definitions (EXT_CLK1_REGL, EXT_CLK2_REGL, EXT_CLK3_REGL, EXT_CLK4_REGL) and read and write command definitions (CMD_READ, CMD_WRITE).

[0044] Furthermore, the sub-functional module receives through the TMI interface: handshake signal i_valid, command word i_cmd, register address i_addr and data packet i_data. When the handshake signal i_valid is high, the other three signals are valid inputs. The sub-functional module outputs through the TMI interface: handshake signal o_valid and response data o_data. When the handshake signal o_valid is high, the response data o_data is a valid output. The handshake signals i_valid and o_valid only maintain a high level within one clock cycle.

[0045] Specifically, the TMI interface of the external clock test functional module needs to transmit four input signals and two output signals. These six signals are consistent in any sub-functional module. The four input signals are i_valid, i_cmd, i_addr, and i_data. When i_valid is high, the other three input signals are valid inputs; the two output signals include o_valid and o_data. When o_valid is high, o_data is a valid output. It should be noted that i_valid and o_valid only maintain one clock cycle when the same data is present. In order to ensure the determinism of the interface delay, data must be output as soon as possible after the input is valid.

[0046] Exemplarily, the register definition of the external clock test function module is shown in Table 2.

[0047] Table 2 Register definition example of external clock test function module

[0048] To facilitate a thorough understanding of the FPGA daisy chain communication structure provided by this application by those skilled in the art, this embodiment of the application also uses the data flow of a computer accessing four sub-function modules as an example to illustrate the FPGA daisy chain communication structure of this application. The output data of the computer enters from sub-function module 1, and the input data is output from sub-function module 4. The specific steps are as follows: Step 1: The computer sends a read operation data frame: 0x5A55 0x0301 0x0002 0x0000 0x00000x0000 0xA5AA; Step 2: After the data enters the sub-function module with ID = 0x01, no response is given and it is directly transparently transmitted. The output data of the sub-function module with ID = 0x01 is as follows: 0x5A55 0x0301 0x0002 0x0000 0x0000 0x0000 0xA5AA; Step 3: After the data enters the sub-function module with ID = 0x02, it does not respond and is directly transparently transmitted. The output data of the sub-function module with ID = 0x02 is as follows: 0x5A55 0x0301 0x0002 0x0000 0x0000 0x0000 0xA5AA; Step 4: After the data enters the sub-function module with ID = 0x03, it responds and reads out 2 words of data. The output data is as follows: 0x5A55 0x0303 0x0002 0x0000 0x55AA 0x1234 0xA5AA (both the command word and the data packet have changed); Step 5: After the data enters the sub-function module with ID = 0x04, no response is given and it is directly transparently transmitted. The output data of the sub-function module with ID = 0x04 is as follows: 0x5A55 0x0303 0x0002 0x0000 0x55AA 0x1234 0xA5AA; Step 6: The computer receives the read operation response frame: 0x5A55 0x0303 0x0002 0x0000 0x55AA0x1234 0xA5AA.

[0049] It is understandable that the present application provides an FPGA daisy chain communication structure: 1. Achieve modularization and interface standardization: The external communication interface of the sub-functional module is defined as a combination of multiple registers. The meaning of the registers is defined by the functional module itself, ensuring the independence and flexibility of the module. The TMI interface, as a parallel interface for accessing registers, becomes a common interface for sub-functional modules, achieving interface standardization and facilitating communication and integration between modules. This modular design not only simplifies the system architecture but also improves the system's scalability and maintainability. 2. Achieve independent debugging and convenient development: After the sub-function module is connected to the TMIP interface module, it only needs to connect the RXD / TXD of the TMIP interface module with the external RXD / TXD to independently complete the product module-level functional debugging. During the development process, the sub-function module does not need to consider the communication interface and protocol with the host computer, but only needs to focus on its own function development and register definition. The same sub-function module can be easily transplanted in different projects with only a simple port call, which greatly improves development efficiency and module reusability. 3. Optimized communication link design: After multiple modules are connected in a daisy-chain manner, each TMIP interface module can receive data from the host computer or response data from the previous module, simplifying the communication link and the number of signal lines. The communication data packet size is variable, which can meet the requirements of both fast transmission of small data packets and complete transmission of large data packets. The TMIP interface module adopts an asynchronous communication mode, and each sub-functional module can operate in a different clock domain without considering cross-clock domain issues. The UART interface is not only applicable to FPGA internal modules, but can also be extended to processor modules such as DSP, ARM, and PS, further enhancing the scalability and compatibility of the system.

[0050] The embodiment of the present application also provides an FPGA daisy chain communication system, the system includes: Figure 2 The FPGA daisy-chain communication structure shown.

[0051] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An FPGA daisy chain communication structure, characterized in that: include: Multiple FPGA internal function modules, the multiple FPGA internal function modules are serially connected in a daisy-chain topology and communicate with the outside through a UART interface, wherein a transmitting port of a previous FPGA internal function module is connected to a receiving port of a subsequent FPGA internal function module; Each FPGA internal functional module includes: a TMIP interface module and a sub-functional module, wherein the TMIP interface module and the sub-functional module communicate via a TMI interface, wherein the TMIP interface module is configured to generate and parse data frames according to the TMIP protocol; and wherein the sub-functional module is configured to execute functions configured in registers in response to instructions in the data frames. The TMIP protocol stipulates that each FPGA internal functional module forwards data frames that do not match its own ID, responds to data frames that match its own ID, and updates the forwarded content.

2. The FPGA daisy chain communication structure according to claim 1, characterized in that: The data frame includes: Frame header, module ID, command word, data length, register address, data packet, frame tail; Among them, the frame header is the start mark of the data frame, the module ID is the ID of the sub-function module on the daisy chain, the command word is the operation instruction represented by different values, including at least: NOP operation, read operation, write operation, command response, the data length is the number of data packets in the read and write operations, the register address is the register starting address of the sub-function module in the read and write operations, the data packet is the data required for the read and write operations, all data words in the data packet are filled with 0 during the read operation, and all data words in the data packet are filled with write data by default during the write operation, and the frame tail is the data frame end mark.

3. The FPGA daisy chain communication structure according to claim 2, characterized in that: The bit width occupied by the module ID determines the upper limit number of sub-function modules mounted in the daisy chain topology.

4. The FPGA daisy chain communication structure according to claim 2, wherein: The TMIP protocol also stipulates that when each FPGA internal functional module responds to a data frame that matches its own ID and updates the forwarding content, the data packet is updated to the response data generated by the sub-functional module in response to the operation instruction, and the command word representing the read operation and write operation is updated to the command word representing the command response.

5. The FPGA daisy chain communication structure according to claim 2, characterized in that: The TMIP interface module is specifically used for: Receive input data and convert the input data into parallel data; Receive the frame header and perform frame header detection until the correct frame header is detected; Receive module ID and check whether the module ID matches the corresponding sub-function module ID; When the module ID matches the corresponding sub-function module ID, the command word, the data length, the register address, the data packet and the frame tail are received in sequence, wherein the data in the data packet are received one by one according to the data length; Send the command word, register address and data packet to the sub-function module, and receive the response data returned by the sub-function module; The frame header, module ID, command word, data length, register address and frame tail are used as forwarded data, and when the command word indicates a read operation or a write operation, it is modified into a command response; The data packet is updated according to the response data, and the forwarded data and the response data are converted into a serial data frame for output.

6. The FPGA daisy chain communication structure according to claim 5, characterized in that: The TMIP interface module includes: a data transceiver module, a protocol analysis module and a data buffer module; The data transceiver module is used to convert the received input data into parallel data and send it to the protocol analysis module, and convert the data sent by the data buffer module into serial data for output; The protocol parsing module is used to parse the data frame in the input data, and when the module ID of the data frame matches the sub-function module ID, it sends the command word, register address and data packet to the sub-function module and forwards the rest of the data frame to the data buffer module; The data buffer module is used to receive the forwarding content of the protocol analysis module and the response data of the sub-function module and forward them to the data transceiver module when the module ID of the data frame matches the sub-function module ID.

7. The FPGA daisy chain communication structure according to claim 6, characterized in that: The protocol analysis module is further configured to generate a handshake signal, and send the handshake signal together with the command word, register address and data packet to the sub-function module.

8. The FPGA daisy chain communication structure according to claim 2, characterized in that: The sub-function modules include: Register mapping module and function implementation module; The register mapping module is used to map the register address to a specific register; The function implementation module is used to execute the parameters configured by the register to realize the corresponding functions of the sub-function module.

9. The FPGA daisy chain communication structure according to claim 8, characterized in that: The sub-function module receives through the TMI interface: a handshake signal i_valid, a command word i_cmd, a register address i_addr and a data packet i_data. When the handshake signal i_valid is high, the other three signals are valid inputs. The sub-function module outputs through the TMI interface: a handshake signal o_valid and response data o_data, when the handshake signal o_valid is high, the response data o_data is a valid output; The handshake signals i_valid and o_valid maintain a high level only in one clock cycle.

10. An FPGA daisy chain communication system, characterized in that: The communication system includes the FPGA daisy chain communication structure according to any one of claims 1 to 9.

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