Dynamic impedance adjusting device for semiconductor signal circuit and adjusting method thereof

Abstract

The embodiment of the invention provides a dynamic impedance adjusting device for a semiconductor signal circuit and an adjusting method thereof, and belongs to the technical field of semiconductor signal detection. The dynamic impedance adjusting device comprises a first adjusting unit which is provided with a first switch array and a first resistor array which are electrically connected to perform binary coarse adjustment through different resistance value combinations so as to determine a target resistance value to perform impedance preliminary matching; the second adjusting unit is provided with a second switch array and a second resistor array which are electrically connected, and the second switch array and the second resistor array are subjected to sub-ohm level stepping linear fine tuning to precisely correct a target resistance value obtained by the first adjusting unit to complete impedance matching; the control unit is electrically connected with the first adjusting unit and the second adjusting unit so as to control on-off of each switch in the first switch array and the second switch array. According to the dynamic impedance adjusting device, high-precision real-time dynamic adjustment is carried out on impedance matching through mixed adjustment of combined resistance coarse adjustment and small resistance value fine adjustment of multi-switch series connection resistors.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor signal detection, and in particular to a dynamic impedance adjustment device for a semiconductor signal circuit and an adjustment method thereof. Background Art

[0002] In high-speed digital communications (such as 5G / 6G, high-speed SerDes) and RF systems, the impedance matching accuracy of signal transmission lines directly determines signal integrity and system performance. Traditional impedance adjustment technology has the following bottlenecks: (1) Lagging adjustment method: Mechanical potentiometers require manual calibration and cannot adapt to real-time dynamic environmental changes; digital potentiometers (DigiPOTs) rely on MOS switches, and the on-resistance and parasitic capacitance cause accuracy drift, and the isolation is insufficient at high frequencies. (2) The contradiction between speed and power consumption: The switching speed of MOS-based resistor arrays is limited (microseconds), making it difficult to meet the needs of nanosecond signal compensation; large-size relay switches have high power consumption and are bulky, making them unable to be integrated into high-density PCBs. (3) It is difficult to balance accuracy and range, and existing impedance adjustment methods make it impossible to optimize the two together.

[0003] In view of this, the present invention proposes a novel dynamic impedance adjustment device and adjustment method for a semiconductor signal circuit to fully or partially solve the above problems. Summary of the Invention

[0004] To address at least one aspect of the aforementioned problems and shortcomings in the prior art, embodiments of the present invention provide a dynamic impedance adjustment device and method for semiconductor signal circuits. This device utilizes a control unit to control multiple MESE switches connected in series with resistors to achieve coarse adjustment of a wide range of resistance combinations and fine adjustment of small resistance values ​​in the sub-ohm range, enabling high-precision, real-time dynamic adjustment of the impedance matching of semiconductor signal circuits. The technical solution is as follows:

[0005] According to one aspect of the present invention, a dynamic impedance adjustment device for a semiconductor signal circuit is provided. The dynamic impedance adjustment device comprises:

[0006] A first adjustment unit is configured to perform binary coarse adjustment on a first switch array and a first resistor array electrically connected to each other through different resistance value combinations to determine a target resistance value for preliminary impedance matching;

[0007] A second adjustment unit is provided, which is configured to electrically connect a second switch array and a second resistor array and perform sub-ohm step linear fine-tuning to precisely correct the target resistance value obtained by the first adjustment unit to achieve impedance matching;

[0008] A control unit is electrically connected to the first regulating unit and the second regulating unit respectively to control the on-off of each switch in the first switch array and the on-off of each switch in the second switch array.

[0009] In some embodiments, specifically, the first switch array includes n first switches, and the first resistor array includes n coarse adjustment resistors, where n is a positive integer greater than or equal to 1. The n first switches are connected in parallel, and each of the n coarse adjustment resistors is connected in series with each corresponding first switch of the n first switches connected in parallel. Alternatively, the n first switches are connected in series, and each of the n coarse adjustment resistors is connected in parallel with each corresponding first switch of the n first switches connected in series.

[0010] In some embodiments, the dynamic impedance adjustment device further includes an intermediate transmission unit electrically connected to the first adjustment unit, and the intermediate transmission unit transmits the target resistance value obtained through binary coarse adjustment as feedback to the control unit.

[0011] In some embodiments, further, each coarse adjustment resistor has a fixed resistance value different from each other, and the control unit controls the on and off of the n first switches to provide different combined resistance values. The n first switches provide a total of 2 n A combined resistance value.

[0012] In some embodiments, specifically, the second switch array includes N second switches connected in parallel, and the second resistor array includes N fine-tuning resistors, wherein each of the N fine-tuning resistors is respectively connected in series with each of the N second switches, and N is a positive integer greater than or equal to 1.

[0013] In some embodiments, the dynamic impedance adjustment device further includes a final transmission unit electrically connected to the second adjustment unit, and the final transmission unit transmits the precisely corrected target resistance value obtained through linear fine-tuning as feedback to the control unit or the external detection circuit.

[0014] In some embodiments, each trimming resistor has the same fixed trimming resistance value, and the trimming resistance value ranges from 0.1 to 0.4 Ω. The control unit controls the on and off of the N second switches to precisely adjust the target resistance value in steps of at least 0.1 Ω.

[0015] In some embodiments, preferably, the n first switches in the first switch array and the N second switches in the second switch array are MEMS switches, and a switch control circuit is provided inside the MEMS switch, which performs switching on and off actions through an FPGA or a buffer chip.

[0016] In some embodiments, the control unit preferably includes a simulation module, a verification module, and a feedback module. The simulation module inputs a simulated combined resistance value into the verification module to test the impedance adjustment effect. The simulated combined resistance value that passes the test is then output to the first adjustment unit via the control unit for actual binary coarse adjustment. The feedback module is electrically connected to the verification module and the second adjustment unit to form a closed control loop for automatic impedance matching. The control unit is an FPGA (field programmable gate array) or an MCU (microprocessor unit).

[0017] In some embodiments, preferably, the control unit further comprises an acquisition module, which acquires initial signal parameters of the semiconductor circuit. The initial signal parameters are used as an accuracy evaluation benchmark for impedance adjustment and are used for circuit verification by the verification module.

[0018] According to another aspect of the present invention, a method for adjusting the dynamic impedance of a semiconductor signal circuit is provided. The method uses the dynamic impedance adjustment device described in the above aspects to dynamically adjust the impedance of the semiconductor signal circuit in real time. The method includes:

[0019] The control unit controls the on and off of the first switch array of the first adjustment unit to obtain different combined resistance values ​​and tests the signal quality corresponding to each combined resistance value, and selects at least one combined resistance value based on the test results;

[0020] Based on the at least one combined resistance value, the control unit controls the on and off of the second switch array of the second adjustment unit to perform sub-ohm step linear fine adjustment to precisely calibrate the at least one combined resistance value;

[0021] After each fine calibration, the signal quality is retested by the control unit;

[0022] The control unit outputs an impedance matching resistance value based on a test result of the retested signal quality.

[0023] In some embodiments, specifically, the signal quality includes any one of eye diagram height or width, reflection loss, transmission loss, time domain reflection analysis, and loopback signal error analysis, or any combination thereof.

[0024] The dynamic impedance adjustment device and adjustment method for a semiconductor signal circuit provided by the embodiments of the present invention have at least one or part of the following advantages:

[0025] (1) Through the FPGA or MCU control unit to control the multi-way MESE switch series resistor to perform a wide range of multiple resistance combination coarse adjustment and small resistance sub-ohm level fine adjustment of the hybrid adjustment architecture to perform high-precision real-time dynamic adjustment of the impedance matching of semiconductor signal circuits, especially dense high-speed signal circuits;

[0026] (2) By setting corresponding n MESE switches and n resistors of different resistance values ​​in the first adjustment unit to form each independent resistance circuit, a binary weighted array is realized to obtain a combination resistor with a wide adjustable resistance range, which can quickly locate the target resistor;

[0027] (3) By setting corresponding N MESE switches and N small-value resistors in the second adjustment unit, a more accurate correction or compensation can be performed after the target resistance is obtained, and a minimum step size of 0.1Ω can be provided for linear fine-tuning;

[0028] (4) By repeatedly fine-tuning the impedance through the verification module and feedback module in the control unit, the impedance value can be dynamically changed during signal transmission according to the actual conditions of the semiconductor chip, thereby suppressing reflections, maintaining signal integrity, and improving the reliability and robustness of the high-speed communication system;

[0029] (5) The simulation module in the control unit can simulate the combined resistance value for binary coarse adjustment in advance and provide the initial impedance adjustment range for the first adjustment unit after circuit verification, thereby further improving the impedance matching efficiency;

[0030] (6) By using MEMS mechanical switches, it does not rely on MOS or potentiometers and has the characteristics of high impedance isolation, ultra-low power consumption, and nanosecond switching speed;

[0031] (7) Compared with traditional VR or MOS matrix, MEMS structure is more suitable for miniaturization and high-density circuit wiring, and its power consumption is almost zero in static state. It is also suitable for online adjustment and mismatch correction of interfaces such as ATE, DDR / PCIe, production testing (ATE), system compensation, aging self-calibration and other scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of the preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 2 is a schematic structural diagram of a dynamic impedance adjustment device for a semiconductor signal circuit according to an embodiment of the present invention;

[0034] Figure 2 for Figure 1 A structural schematic diagram of a first adjustment unit of an embodiment of a dynamic impedance adjustment device is shown;

[0035] Figure 3 for Figure 1 A structural schematic diagram of a first adjustment unit of another embodiment of a dynamic impedance adjustment device is shown;

[0036] Figure 4 for Figure 1 A structural schematic diagram of a second adjustment unit of an embodiment of a dynamic impedance adjustment device shown;

[0037] Figure 5 The figure is a flow chart of a method for adjusting the dynamic impedance of a semiconductor signal circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The technical solution of the present invention will be further described in detail below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as limiting the present invention.

[0039] It should also be understood that although the terms "first," "second," "third," etc. may be used in the following embodiments of the present invention to describe that a component includes two or more components, these components should not be limited by these terms. These terms are merely used to distinguish each component from another and should not be construed as limiting the present invention.

[0040] In semiconductor communications, especially high-speed digital communications and radio frequency systems, the impedance matching accuracy of signal transmission lines directly determines signal integrity and system performance. Therefore, embodiments of the present invention provide a dynamic impedance adjustment device and method for semiconductor signal circuits. This hybrid adjustment architecture utilizes an FPGA- or MCU-based control unit to control multiple MESE switches in parallel with resistors, enabling coarse adjustment of a wide range of resistance combinations and fine adjustment of small resistance values ​​in the sub-ohm range. This architecture allows for high-precision, real-time dynamic adjustment of the impedance matching of semiconductor signal circuits.

[0041] According to one aspect of the present invention, a dynamic impedance adjustment device for a semiconductor signal circuit is provided.

[0042] See also Figure 1 , showing the specific structure and circuit connections of a dynamic impedance adjustment device according to an embodiment. The dynamic impedance adjustment device 100 primarily comprises five electrically connected modules: a control unit 10, a first adjustment unit 20 for binary coarse adjustment, a second adjustment unit 30 for linear fine adjustment, an intermediate transmission unit 40, and a final transmission unit 50.

[0043] The first adjustment unit 20 is internally electrically connected to the first switch array 21 and the first resistor array 22 to perform binary coarse adjustment through different resistance value combinations to determine the target resistance value for preliminary impedance matching.

[0044] The second adjustment unit 30 is internally electrically connected to the second switch array 31 and the second resistor array 32 to precisely calibrate the target resistance value obtained by the first adjustment unit 20 through sub-ohm step linear fine-tuning to achieve impedance matching.

[0045] The control unit 10 is electrically connected to the first regulating unit 20 and the second regulating unit 30 to control the on / off of each switch in the first switch array 21 and the on / off of each switch in the second switch array 31 .

[0046] Dynamic impedance adjustment device 100 combines binary weighted coarse adjustment with small resistance linear fine adjustment via first adjustment unit 20 and second adjustment unit 30 to form a controllable and adjustable resistor array. This device supports and implements multi-level impedance adjustment, achieving high-resolution resistance matching adjustment from wide-range coarse adjustment to small-step fine adjustment.

[0047] The workflow of the dynamic impedance adjustment device 100 controlling the on / off switching of the connected resistor through the control unit 10 therein can be divided into two stages, namely, coarse adjustment followed by fine adjustment. By combining multiple switches (especially MEMS switches) with the resistor for adjusting the impedance, a variety of different combined resistance values ​​for adjusting the impedance can be provided, thereby realizing dynamic adjustment of the equivalent resistance in the semiconductor circuit and adjusting the impedance of the signal path in the matching circuit.

[0048] The coarse adjustment + fine adjustment dual-stage impedance matching architecture provides a wider range of combined resistance values ​​during coarse adjustment and combines with the analog adjustment inside the control unit 10 to quickly find the appropriate impedance adjustment range. It supports sub-ohm adjustment steps during fine adjustment and has a response speed of up to nanoseconds. It is suitable for high-speed application scenarios such as DDR5, GDDR6, PCIe 5.0 / 6.0, making up for the limitations of accuracy and responsiveness of traditional static matching structures, and can also achieve dynamic optimization of the signal quality of semiconductor products when they are working.

[0049] See also Figure 2 , shows the internal structure, electrical connections and signal transmission connection relationship of the first regulating unit 20 of an embodiment. In which several switches in the first switch array 21 in the first regulating unit 20 are arranged in parallel.

[0050] In one example, specifically, the first switch array 21 includes n first switches connected in parallel, for example Figure 2 MEMS1-1, MEMS1-2, MEMS1-3...MEMS1-n are shown; the first resistor array 22 includes n coarse adjustment resistors, for example Figure 2R1-1, R1-2, R1-3, ..., R1-n are shown, wherein each of the n coarse adjustment resistors is connected in series with each of the n first switches, and n is a positive integer greater than or equal to 1.

[0051] See also Figure 3 , shows the internal structure, electrical connections and signal transmission connection relationship of the first regulating unit 20' of another embodiment, wherein several switches in the first switch array 21' in the first regulating unit 20' are arranged in series.

[0052] In one example, specifically, the first switch array 21 ′ includes n first switches connected in series, for example Figure 3 MEMS1-1, MEMS1-2, MEMS1-3...MEMS1-n are shown; the first resistor array 22' includes n coarse adjustment resistors, for example Figure 3 R1-1, R1-2, R1-3, ..., R1-n are shown, wherein each of the n coarse adjustment resistors is connected in parallel with each of the n first switches, and n is a positive integer greater than or equal to 1.

[0053] like Figure 2 or Figure 3 As shown, in one example, the dynamic impedance adjustment device 100 further includes an intermediate transmission unit 40 electrically connected to the first adjustment unit 20 (which may also be the first adjustment unit 20 ′), and the intermediate transmission unit 40 transmits the target resistance value obtained through binary coarse adjustment to the control unit 10 as feedback.

[0054] In one example, further, each coarse adjustment resistor has a fixed resistance value different from each other, and the control unit 10 controls the on and off of n first switches to provide different combined resistance values. The n first switches provide a total of 2 n A combined resistance value.

[0055] In one example, n first switches are connected in series with n coarse adjustment resistors one by one. After the power supply module (which can be independently provided outside the dynamic impedance adjustment device 100 or integrated with the dynamic impedance adjustment device 100, such as the control unit 10) supplies power, the switch can be turned on and off according to the control signal or control instruction of the control unit 10 to form a total of 2 n The combination of resistance values ​​follows binary weight logic to form a binary weighted resistor array, which is used to cover a wider impedance adjustment compensation range in the coarse adjustment stage.

[0056] For example, Figure 2Taking the parallel switch layout shown as an example, four first switches MEMS1-1, MEMS1-2, MEMS1-3 and MEMS1-4 are set in the first switch array 21, and four coarse adjustment resistors R1-1, R1-2, R1-3 and R1-4 are correspondingly set in the first resistor array 22, and the coarse adjustment resistors are assigned R1-1=R, R1-2=2R, R1-3=4R, R1-4=8R. The binary weighted array method refers to controlling a plurality of MEMS switches with different resistance values ​​in series by the control unit 10 to perform resistance combination. For example, when MEMS1-1 is turned on, R1-1 is connected to obtain a coarse adjustment resistor with a resistance value of R, and when MEMS1-2 is turned on, R1-2 is connected to obtain a coarse adjustment resistor with a resistance value of 2R. Then, the combined resistance value is R+2R=3R. By analogy, the maximum number of combined resistance values ​​that can be obtained by n MEMS switches is 2 n . Figure 3 The resistor combination of the series switch layout shown can be obtained similarly and will not be repeated here. The actual circuit design can choose to configure the switches in parallel or in series according to the impedance adjustment requirements of the semiconductor signal circuit and the actual parameters such as antenna effect.

[0057] See also Figure 4 , showing the internal specific structure, electrical connection and signal transmission connection relationship of the second adjustment unit 30.

[0058] In one example, specifically, the second switch array 31 includes N second switches connected in parallel, for example Figure 4 MEMS2-1, MEMS2-2, MEMS2-3...MEMS2-N are shown; the second resistor array 32 includes N fine-tuning resistors, for example Figure 4 R2-1, R2-2, R2-3, ..., R2-N are shown, wherein each of the N fine-tuning resistors is connected in series with each of the N second switches, and N is a positive integer greater than or equal to 1.

[0059] In one example, the dynamic impedance adjustment device 100 further includes a final transmission unit 50 electrically connected to the second adjustment unit 30, and the final transmission unit 50 transmits the precisely corrected target resistance value obtained by linear fine-tuning and feeds it back to the control unit 10 or the external detection circuit.

[0060] In one example, each trimming resistor has the same fixed trimming resistance value, and the trimming resistance value ranges from 0.1 to 0.4 Ω. The control unit 10 controls the on and off of the N second switches to precisely adjust the target resistance value with a minimum step size of 0.1 Ω.

[0061] For example, if each trimming resistor has a resistance of 0.1Ω, the minimum resistance step for linearly trimming the target resistance obtained by the first adjustment unit 20 is 0.1Ω. In other words, turning on a second switch (e.g., MEMS2-1) connects a trimming resistor (corresponding to R2-1), allowing the target resistance to be fine-tuned in 0.1Ω steps. Repeated fine-tuning can yield the final adjusted impedance value.

[0062] Typically, the impedance matching error of most PCB traces needs to be as small as possible, less than 1Ω. Conventional methods or device structures that finely adjust impedance using a step-by-step approach have a minimum step resolution of 0.5Ω. Therefore, the dynamic impedance adjustment device 100 can achieve a smaller impedance adjustment step size.

[0063] In one example, the n first switches in the first switch array 21 and the N second switches in the second switch array 31 are preferably MEMS switches. A switch control circuit is provided within the MEMS switches, which performs on-off switching via an FPGA or buffer chip. By distributing MEMS switches within the first adjustment unit 20 and the second adjustment unit 30, respectively, and connecting corresponding resistors for adjusting impedance in series, an adjustable and controllable resistor network structure based on the MEMS micro-switch matrix is ​​formed.

[0064] MEMS switches are micromechanical switches that don't rely on MOS or potentiometers. Therefore, they offer high-impedance isolation, ultra-low power consumption, and nanosecond switching speeds. Furthermore, MEMS switches can support dynamic switching for automatic online resistance compensation, feedback control, and temperature drift adaptation. They also support real-time programming for self-repairing impedance matching. For example, all MEMS switches can be controlled by an FPGA or MCU.

[0065] In one example, preferably, Figure 1 As shown, the control unit 10 includes a simulation module 11, a verification module 12, and a feedback module 13. The simulation module 11 inputs the simulated combined resistance value into the verification module 12 to test the impedance adjustment effect, and outputs the simulated combined resistance value that passes the test to the first adjustment unit 20 through the control unit 10 for actual binary coarse adjustment. The feedback module 13 is electrically connected to the verification module 12 and the second adjustment unit 30 to form a control closed loop to automatically match the impedance. Alternatively, the control unit 10 is controlled in real time by an FPGA or MCU, dynamically adjusting and selecting the appropriate combined resistance according to the operating status of the signal circuit, thereby achieving fine adjustment and compensation of the impedance of the signal circuit.

[0066] For example, after the simulation module 11 and the verification module 12 are integrated within the control unit 10, the impedance adjustment may not initially involve actual impedance matching adjustment. Instead, a simulation test of the resistance combination is first performed in the simulation module 11 and the verification module 12 using a simulation-loopback-test process, combining the combined resistance values ​​provided by the first adjustment unit 20. Once the optimal combined resistance value is obtained through the simulation test, impedance matching is initiated in the MEMS switch resistor array network structure actually loaded into the semiconductor signal circuit.

[0067] For example, a MEMS switch resistor array network structure identical to the first adjustment unit 20 can be established in the simulation module 11. Then, the verification module 12 loops back to test all 2 n The transmission signal quality is tested using the combined resistance to obtain at least one optimal combined resistance value and output it to the first adjustment unit 20 for the first stage of coarse adjustment.

[0068] In one example, the control unit 10 preferably further includes an acquisition module 14 that acquires initial signal parameters of the semiconductor circuit. The initial signal parameters serve as a benchmark for evaluating the accuracy of impedance adjustment and are then used for circuit verification by the verification module 12. In other words, the parameters acquired in the initial stage (e.g., S11, eye height, jitter, reflection point, etc.) are used to establish a reference model for impedance adjustment and serve as a benchmark for evaluating the effectiveness of subsequent adjustment.

[0069] The main functions of the initial signal parameters include, but are not limited to, comparing the subsequent signal quality changes using each set of combined resistance adjustments, determining whether the impedance compensation is effective, serving as the original state or fallback state during the loopback debugging process, and serving as a training sample for the adjustment model. Furthermore, the feedback module 13 receives the fine-tuned target resistance value through the final transmission unit 50 and is electrically connected to the second adjustment unit 30, and feeds it back to the control unit 10 to re-enter the verification module 12 for signal quality testing and analysis. In this way, during the fine-tuning stage, closed-loop feedback can be achieved to continuously fine-tune the resistance value of the target resistor to approach the optimal adjustment impedance, or dynamic fine-tune it continuously through closed-loop feedback according to the real-time working state changes of the signal circuit.

[0070] For example, when using an FPGA as the control unit 10, an ADC analyzer (such as EyeScan) can be internally connected to it, while also being connected to an external high-speed sampling device for debugging. The FPGA executes closed-loop scanning using an FSM control structure, dynamically adjusting the on / off states of the switch arrays in the first adjustment unit 20 and / or the second adjustment unit 30 based on the current signal score. For example, during the test phase to determine the coarse adjustment combined resistance value, a pseudo-random bit sequence (PRBS) or specific edge transition data is transmitted. After each combined resistance value is tested and evaluated, the evaluation scores are ranked and the optimal value is selected.

[0071] According to another aspect of the present invention, a method for adjusting the dynamic impedance of a semiconductor signal circuit is provided, wherein the method uses the dynamic impedance adjustment device 100 described in the above aspect to dynamically adjust the impedance of the semiconductor signal circuit in real time.

[0072] See also Figure 5 , shows the steps of the dynamic impedance adjustment method. Figure 1 The specific structure of the dynamic impedance adjustment device shown in FIG. 1 , the adjustment method includes:

[0073] Step S100: the control unit 10 controls the on and off of the first switch array 21 of the first adjustment unit 20 to obtain different combined resistance values ​​and tests the signal quality corresponding to each combined resistance value, and selects at least one combined resistance value based on the test results.

[0074] Step S200 : Based on the at least one combined resistance value obtained in step S100 , the control unit 10 controls the on and off of the second switch array 31 of the second adjustment unit 30 to perform sub-ohm step linear fine adjustment to precisely calibrate the at least one combined resistance value.

[0075] Step S300: retesting the signal quality via the control unit 10 after each precision calibration.

[0076] Step S400: The control unit 10 outputs an impedance matching resistance value based on the test result of the retest signal quality obtained in step S300.

[0077] Illustratively, the signal quality includes any one of eye diagram height or width, reflection loss, transmission loss, time domain reflection analysis, and loopback signal error analysis, or any combination thereof.

[0078] For example, during the testing process, evaluation criteria are dynamically adjusted. For example, a separate indicator set can be established for each type of interface signal on a semiconductor circuit, or a general indicator set can be established first and then supplemented with a specific indicator set. General indicators that can be used for test evaluation include eye height > 200mV, return loss < –10dB, and minimal ISI (inter-symbol interference). Specific indicators include DDR4's focus on alignment of setup / hold time and read DQS, PCIe's focus on BER after equalization and the effects of CTLE + DFE, and GDDR6's consideration of overshoot caused by excessive signal switching rates.

[0079] In one example, the dynamic impedance adjustment device 100 and the dynamic impedance adjustment method thereof described in the above aspects are described below through an exemplary control flow embodiment.

[0080] The control unit 10 uses an FPGA and can implement programmable dynamic control by a state machine (FSM) inside the FPGA.

[0081] During the initialization phase, all MEMS switches in the first adjustment unit 20 and the second adjustment unit 30 are turned off, and the system enters a default state. The acquisition module 14 in the control unit 10 acquires initial signal parameters (such as reflection intensity and line end waveform).

[0082] Entering the coarse adjustment phase of the first adjustment unit 20 (this example uses a parallel connection of several switches in the first switch array 21; a series connection is similar and will not be described again), the control unit 10 scans the MEMS switch-resistor array network structure formed by the series combination of the first switch array 21 and the first resistor array 22, testing the signal integrity of each resistance value used to adjust the impedance. Based on the test results, the target resistance value for coarse adjustment is selected with the best performance.

[0083] Entering the fine-tuning phase, the second adjustment unit 30 gradually opens the MEMS switches within the second switch array 31, based on the coarse adjustment, to achieve fine compensation adjustment in small resistance steps. After each step adjustment, the verification module 12 of the control unit 10 re-evaluates the signal quality until it reaches or continuously approaches the optimal performance.

[0084] During the dynamic balancing or adjustment phase, the dynamic impedance adjustment device 100 maintains its current optimal state. If the control unit 10 or other external detection device detects a change in the semiconductor circuit's operating environment (e.g., temperature or load) or an impedance adjustment timer is triggered, the dynamic impedance adjustment device 100 re-enters the impedance adjustment mode and performs coarse and fine adjustments to re-match the optimal impedance adjustment resistance value.

[0085] The dynamic impedance adjustment device and adjustment method for a semiconductor signal circuit provided by the embodiments of the present invention have at least one or part of the following advantages:

[0086] (1) The FPGA control unit controls the multi-channel MESE switch series resistor to perform a wide range of multiple resistance combination coarse adjustment and small resistance sub-ohm level fine adjustment. The hybrid adjustment architecture can achieve high-precision real-time dynamic adjustment of the impedance matching of semiconductor signal circuits, especially dense high-speed signal circuits;

[0087] (2) By setting corresponding n MESE switches and n resistors of different resistance values ​​in the first adjustment unit to form each independent resistance circuit, a binary weighted array is realized to obtain a combination resistor with a wide adjustable resistance range, which can quickly locate the target resistor;

[0088] (3) By setting corresponding N MESE switches and N small-value resistors in the second adjustment unit, a more accurate correction or compensation can be performed after the target resistance is obtained, and a minimum step size of 0.1Ω can be provided for linear fine-tuning;

[0089] (4) By repeatedly fine-tuning the impedance through the verification module and feedback module in the control unit, the impedance value can be dynamically changed during signal transmission according to the actual conditions of the semiconductor chip, thereby suppressing reflections, maintaining signal integrity, and improving the reliability and robustness of the high-speed communication system;

[0090] (5) The simulation module in the control unit can simulate the combined resistance value for binary coarse adjustment in advance and provide the initial impedance adjustment range for the first adjustment unit after circuit verification, thereby further improving the impedance matching efficiency;

[0091] (6) By using MEMS mechanical switches, it does not rely on MOS or potentiometers and has the characteristics of high impedance isolation, ultra-low power consumption, and nanosecond switching speed;

[0092] (7) Compared with traditional VR or MOS matrix, MEMS structure is more suitable for miniaturization and high-density circuit wiring, and its power consumption is almost zero in static state. It is also suitable for online adjustment and mismatch correction of interfaces such as ATE, DDR / PCIe, production testing (ATE), system compensation, aging self-calibration and other scenarios.

[0093] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A dynamic impedance adjustment device for a semiconductor signal circuit, characterized in that: The dynamic impedance adjustment device comprises: a first adjustment unit, wherein a first switch array and a first resistor array electrically connected to each other are provided in the first adjustment unit to perform binary coarse adjustment through different resistance value combinations to determine a target resistance value for preliminary impedance matching; a second adjustment unit, wherein a second switch array and a second resistor array electrically connected to each other are provided in the second adjustment unit, and impedance matching is achieved by precisely correcting the target resistance value obtained by the first adjustment unit through sub-ohm step linear fine-tuning; A control unit is electrically connected to the first regulating unit and the second regulating unit to control the on / off of each switch in the first switch array and the on / off of each switch in the second switch array.

2. The dynamic impedance adjustment device according to claim 1, wherein: The first switch array includes n first switches, and the first resistor array includes n coarse adjustment resistors, where n is a positive integer greater than or equal to 1; The n first switches are connected in parallel, and each of the n coarse adjustment resistors is connected in series with each of the n first switches connected in parallel, respectively; or The n first switches are connected in series, and each of the n coarse adjustment resistors is connected in parallel with each of the n first switches connected in series; The dynamic impedance adjustment device further includes an intermediate transmission unit electrically connected to the first adjustment unit, and the intermediate transmission unit transmits the target resistance value obtained through binary coarse adjustment as feedback to the control unit.

3. The dynamic impedance adjustment device according to claim 2, wherein: Each of the coarse adjustment resistors has a fixed resistance value different from each other, The control unit controls the on and off of the n first switches respectively to provide different combined resistance values. The n first switches provide a total of 2 n The combined resistance value.

4. The dynamic impedance adjustment device according to claim 2, wherein: The second switch array includes N second switches connected in parallel, The second resistor array includes N fine-tuning resistors, each of the N fine-tuning resistors is connected in series with each of the N second switches. Wherein N is a positive integer greater than or equal to 1; The dynamic impedance adjustment device further includes a final transmission unit electrically connected to the second adjustment unit, and the final transmission unit transmits the precisely calibrated target resistance value obtained through linear fine-tuning and feeds it back to the control unit or the external detection circuit.

5. The dynamic impedance adjustment device according to claim 4, characterized in that: Each of the fine-tuning resistors has the same and fixed fine-tuning resistance value, and the range of the fine-tuning resistance value is 0.1-0.4Ω; The control unit controls the on and off of the N second switches respectively to precisely adjust the target resistance value with a minimum step size of 0.1Ω.

6. The dynamic impedance adjustment device according to any one of claims 1 to 5, characterized in that: The n first switches in the first switch array and the N second switches in the second switch array are MEMS switches; A switch control circuit is provided inside the MEMS switch, and the switch control circuit performs switch on-off actions through an FPGA or a buffer chip.

7. The dynamic impedance adjustment device according to claim 6, characterized in that: The control unit includes a simulation module, a verification module and a feedback module. The simulation module inputs the simulated combined resistance value into the verification module to test the impedance adjustment effect and outputs the simulated combined resistance value that passes the test to the first adjustment unit through the control unit to perform actual binary coarse adjustment; The feedback module is electrically connected to the verification module and the second adjustment unit to form a control closed loop for automatic impedance matching; The control unit is FPGA or MCU.

8. The dynamic impedance adjustment device according to claim 7, characterized in that: The control unit also includes an acquisition module, The acquisition module acquires initial signal parameters of the semiconductor circuit, and the initial signal parameters are used as an accuracy evaluation benchmark for impedance adjustment to perform circuit verification through the verification module.

9. A method for adjusting the dynamic impedance of a semiconductor signal circuit, wherein the method uses the dynamic impedance adjustment device according to any one of claims 1 to 8 to dynamically adjust the impedance of the semiconductor signal circuit in real time, characterized in that: The adjustment method comprises: The control unit controls the on and off of the first switch array of the first adjustment unit to obtain different combined resistance values ​​and tests the signal quality corresponding to each combined resistance value, and selects at least one combined resistance value based on the test results; Based on the at least one combined resistance value, the control unit controls the on and off of the second switch array of the second adjustment unit to perform sub-ohm step linear fine adjustment to precisely calibrate the at least one combined resistance value; Retesting the signal quality by the control unit after each precision calibration; The control unit outputs an impedance matching resistance value based on a test result of the retested signal quality.

10. The adjustment method according to claim 9, characterized in that: The signal quality includes any one of eye diagram height or width, reflection loss, transmission loss, time domain reflection analysis and loopback signal error analysis, or any combination thereof.

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