Starting circuit capable of being automatically turned off for phase-locked loop oscillator

Abstract

The invention discloses a starting circuit capable of being automatically turned off for a phase-locked loop oscillator, and belongs to the field of integrated circuits. The starting circuit comprises a reference current source and a starting current source; the starting current source enables a voltage-controlled oscillator in the phase-locked loop to start oscillation from an initial state, and mirror image processing is carried out on the working current of the voltage-controlled oscillator; and after the voltage-controlled oscillator reaches the preset oscillation frequency, the reference current source is used for comparison, so that the starting circuit is automatically closed, and the normal working performance of the phase-locked loop is not influenced. The circuit structure provided by the invention can ensure that the voltage-controlled oscillator starts to oscillate from the initial state of the circuit through the starting current source, and after the phase-locked loop starts to work normally, the starting circuit is automatically closed by utilizing comparison of the reference current source without influencing the normal working performance of the phase-locked loop; the problem that the phase-locked loop enters deadlock and cannot be started due to the fact that the alternating-current coupling buffer is interfered by power supply noise in the starting process of the phase-locked loop is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a startup circuit capable of automatically shutting down a phase-locked loop oscillator. Background Art

[0002] A phase-locked loop (PLL) is a circuit structure that uses an external reference signal to control the frequency and phase of an oscillating signal within the loop. By responding to the feedback frequency and phase of the output signal, a dynamically locked output clock signal is generated.

[0003] A phase-locked loop (PLL) typically consists of several key modules: a divider (DIVIDER), a phase frequency detector (PFD), a charge pump, a loop filter (LF), and a voltage-controlled oscillator (VCO). The VCO generates a clock signal, which is typically passed to a subsequent AC-coupled buffer for output. However, during the PLL's startup process, the AC-coupled buffer may be affected by power supply noise and amplify it, generating a premature high-frequency signal that can disrupt the PLL's PFD and prevent the PLL from properly calibrating. This can affect the PLL's startup. Summary of the Invention

[0004] The object of the present invention is to provide a startup circuit for a phase-locked loop oscillator capable of automatically shutting down, so as to solve the problems of the background technology.

[0005] In order to solve the above technical problems, the present invention provides a startup circuit for a phase-locked loop oscillator that can automatically shut down. The phase-locked loop includes a divider, a frequency detector-charge pump, a loop filter, a voltage-controlled oscillator, and a low-dropout linear regulator. The startup circuit includes a reference current source and a startup current source; The startup current source enables the voltage-controlled oscillator in the phase-locked loop to start oscillating from an initial state and performs mirror processing on the operating current of the voltage-controlled oscillator; After the voltage-controlled oscillator reaches a preset oscillation frequency, the reference current source is used for comparison, so that the startup circuit is automatically turned off without affecting the normal working performance of the phase-locked loop.

[0006] In one embodiment, the startup circuit further includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, and a second inverter; CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal detected by the phase frequency detector-charge pump respectively. The output end of the phase frequency detector-charge pump is connected to the gate end of the first PMOS transistor. The source end of the first PMOS transistor is connected to the low-dropout linear regulator, and the drain end is connected to the voltage-controlled oscillator. The input terminal of the startup current source is connected to the power supply voltage Vdd, the output terminal is connected to the source terminal of the third PMOS transistor, the gate terminal of the third PMOS transistor is connected to the VBP node, and the drain terminal is connected to the drain terminal of the first PMOS transistor; the source terminal of the second PMOS transistor is connected to the source terminal of the first PMOS transistor, the gate terminal of the second PMOS transistor and the gate terminal of the first PMOS transistor are both connected to the control voltage VCTRL output by the frequency detector and the charge pump, and the drain terminal of the second PMOS transistor is connected to the VBP node; The reference current source has an input terminal connected to the power supply voltage Vdd, an output terminal connected to the drain terminal and gate terminal of the second NMOS transistor, the gate terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor, and the source terminal of the second NMOS transistor is connected to the source terminal of the first NMOS transistor; the drain terminal of the first NMOS transistor is connected to the VBP node; The voltage-controlled oscillator outputs a frequency VCO_CLK, which is AC-coupled to the input of the first inverter via a capacitor. The output of the first inverter and the input of the second inverter are commonly connected to a node N1. The output of the second inverter and the input of the divider are commonly connected to a node N2. The divider outputs a feedback signal DIVIDER_OUT. A resistor is connected between the input and output of the first inverter to determine the AC-coupled common-mode voltage.

[0007] In one embodiment, the mirror current of the stable operating current of the voltage-controlled oscillator passing through the second PMOS tube is greater than the reference current source, and the reference current source is 1 / 2n times the stable operating current of the voltage-controlled oscillator, where n is the size ratio of the first PMOS tube and the second PMOS tube; the stable operating current of the voltage-controlled oscillator is greater than the startup current provided by the startup current source.

[0008] The present invention provides a startup circuit for a phase-locked loop (PLL) oscillator that automatically shuts down. This circuit effectively addresses the problem in which the AC-coupled buffer used in conventional PLLs can be affected by power supply noise, amplifying it and prematurely generating a high-frequency signal that can prevent the PLL's phase and frequency detector from properly determining the signal, thereby affecting the PLL's normal startup. The circuit structure proposed in the present invention ensures that the voltage-controlled oscillator begins oscillating from its initial state through a startup current source. After the PLL begins normal operation, it automatically shuts down the startup circuit using a comparison with a reference current source without affecting the PLL's normal performance. This eliminates the problem of the AC-coupled buffer being affected by power supply noise during PLL startup, causing the PLL to enter deadlock and become unable to start. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The present invention provides a schematic diagram of a startup circuit structure for automatically shutting down a phase-locked loop oscillator. DETAILED DESCRIPTION

[0010] The following, in conjunction with the accompanying drawings and specific embodiments, further details a startup circuit for automatically shutting down a phase-locked loop oscillator, as proposed by the present invention. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0011] The present invention provides a startup circuit for a phase-locked loop oscillator that can automatically shut down, and its block diagram is as follows: Figure 1 As shown, CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal detected by the phase frequency detector (PFD-CP), respectively. The output of the phase frequency detector-charge pump (PFD-CP) is connected to the gate of PMOS transistor MP1. The source of PMOS transistor MP1 is connected to a low-dropout linear regulator (LDO), and the drain is connected to the voltage-controlled oscillator (VCO). VCTRL is the control voltage of the voltage-controlled oscillator (VCO) and is determined by the behavior of the PFD-CP. The loop filter is simply represented by the capacitor connected to VCTRL. The input of startup current source IB2 is connected to the power supply voltage Vdd, and the output is connected to the source of PMOS transistor MP3. The gate of PMOS transistor MP3 is connected to the VBP node, and the drain is connected to the drain of PMOS transistor MP1. The source of PMOS transistor MP2 is connected to the source of PMOS transistor MP1. The gates of PMOS transistors MP2 and MP1 are both connected to the control voltage VCTRL output by the PFD-CP. The drain of PMOS transistor MP2 is connected to the VBP node. The input terminal of the reference current source IB1 is connected to the power supply voltage Vdd, and the output terminal is connected to the drain and gate terminals of the NMOS transistor MN2. The gate terminal of the NMOS transistor MN2 is connected to the gate terminal of the NMOS transistor MN1, and the source terminal of the NMOS transistor MN2 is connected to the source terminal of the NMOS transistor MN1. The drain terminal of the NMOS transistor MN1 is connected to the VBP node. The voltage-controlled oscillator outputs the frequency VCO_CLK through a capacitor to the input terminal of the inverter INV1. The output terminal of the inverter INV1 and the input terminal of the inverter INV2 are commonly connected to the node N1. The output terminal of the inverter INV2 and the input terminal of the divider DIVIDER are commonly connected to the node N2. The divider outputs a feedback signal DIVIDER_OUT. A resistor R1 is connected between the input and output terminals of the inverter INV1.

[0012] The size of the PMOS transistor MP1 is n times the width of the PMOS transistor MP2. IB2 is a startup current source sufficient to enable the voltage-controlled oscillator VCO to operate at a lower frequency. IB1 is a reference current source used to compare with the actual operating current of the voltage-controlled oscillator VCO. Assuming that the stable operating current of the voltage-controlled oscillator VCO is IB, the value of IB1 can be IB / n / 2, and the value of IB2 can be IB / n / 5.

[0013] During the startup of the phase-locked loop, the conventional AC-coupled buffer may be interfered by the power supply noise and amplify it, such as Figure 1 As shown in the figure, before the voltage-controlled oscillator VCO starts, VCO_CLK has not yet started to oscillate and is in a low-level state. Due to the power supply noise, a high-frequency noise signal will be generated at the node N1 in advance, and the amplification effect of the inverter INV2 will generate an amplified high-frequency signal at the node N2, causing the frequency detector in the phase-locked loop to mistakenly input the high-frequency signal DIVIDER_OUT, thereby incorrectly judging the feedback clock frequency, causing the phase-locked loop to enter deadlock and unable to start normally.

[0014] The technical solution of the present invention adopts the following method during the startup process of the phase-locked loop: Figure 1 The circuit shown in Figure 1 is shown. Before the voltage-controlled oscillator (VCO) starts up, VCTRL is at a high level. The current through the PMOS transistors MP1 and MP2 is approximately zero, while the current through the NMOS transistor MN2 is IB1. The mirror relationship between the NMOS transistors MN1 and MN2 pulls node VBP down to a low level, turning on the PMOS transistor MP3. Current source IB2 provides a startup current that allows the VCO to operate at a lower frequency, causing VCO_CLK to begin oscillating. This further transmits the VCO_CLK frequency to nodes N1 and N2, masking the effects of premature high-frequency noise generated by power supply noise. Next, the phase frequency detector (PFD) and charge pump (CP) begin normal operation, gradually pulling VCTRL down to the voltage required for the VCO to operate normally. During the falling process of VCTRL, the current flowing through the PMOS transistors MP1 and MP2 continues to increase. When the mirror current flowing through the PMOS transistor MP2 exceeds the current flowing through the NMOS transistor MN1, the node VBP will rise to a high level, thereby turning off the PMOS transistor MP3, so that IB2 no longer continues to charge the voltage-controlled oscillator VCO, and the startup circuit is turned off. At this time, the phase-locked loop has started normally, and the startup circuit does not affect the working performance of the phase-locked loop.

[0015] The present invention uses a simple circuit structure to eliminate the problem that during the startup of the phase-locked loop, the AC coupling buffer is interfered with by the high-frequency power supply noise and amplifies it, causing the phase-locked loop to enter deadlock and be unable to start. Figure 1In the circuit structure shown, the voltage-controlled oscillator (VCO) starts oscillating from its initial state through startup current source IB2, mirrors the VCO's operating current, and automatically shuts down the startup circuit after the VCO reaches a certain oscillation frequency using reference current source IB1 for comparison. This does not affect the normal operation of the PLL. At this point, the PLL circuit enters a dynamic lock state, eliminating the problem of the PLL entering deadlock and failing to start due to power supply noise interference with the AC-coupled buffer during startup.

[0016] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A startup circuit for a phase-locked loop oscillator capable of automatically shutting down, the phase-locked loop comprising a divider, a phase frequency detector-charge pump, a loop filter, a voltage-controlled oscillator, and a low-dropout linear regulator, characterized in that: The startup circuit includes a reference current source and a startup current source; The startup current source enables the voltage-controlled oscillator in the phase-locked loop to start oscillating from an initial state and performs mirror processing on the operating current of the voltage-controlled oscillator; After the voltage-controlled oscillator reaches a preset oscillation frequency, the reference current source is used for comparison, so that the startup circuit is automatically turned off without affecting the normal working performance of the phase-locked loop.

2. The startup circuit for automatically shutting down a phase-locked loop oscillator according to claim 1, wherein: The startup circuit further includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter and a second inverter; CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal detected by the phase frequency detector-charge pump respectively. The output end of the phase frequency detector-charge pump is connected to the gate end of the first PMOS transistor. The source end of the first PMOS transistor is connected to the low-dropout linear regulator, and the drain end is connected to the voltage-controlled oscillator. The input terminal of the startup current source is connected to the power supply voltage Vdd, the output terminal is connected to the source terminal of the third PMOS transistor, the gate terminal of the third PMOS transistor is connected to the VBP node, and the drain terminal is connected to the drain terminal of the first PMOS transistor; the source terminal of the second PMOS transistor is connected to the source terminal of the first PMOS transistor, the gate terminal of the second PMOS transistor and the gate terminal of the first PMOS transistor are both connected to the control voltage VCTRL output by the frequency detector and the charge pump, and the drain terminal of the second PMOS transistor is connected to the VBP node; The reference current source has an input terminal connected to the power supply voltage Vdd, an output terminal connected to the drain terminal and gate terminal of the second NMOS transistor, the gate terminal of the second NMOS transistor is connected to the gate terminal of the first NMOS transistor, and the source terminal of the second NMOS transistor is connected to the source terminal of the first NMOS transistor; the drain terminal of the first NMOS transistor is connected to the VBP node; The voltage-controlled oscillator outputs a frequency VCO_CLK, which is AC-coupled to the input of the first inverter via a capacitor. The output of the first inverter and the input of the second inverter are commonly connected to a node N1. The output of the second inverter and the input of the divider are commonly connected to a node N2. The divider outputs a feedback signal DIVIDER_OUT. A resistor is connected between the input and output of the first inverter to determine the AC-coupled common-mode voltage.

3. The startup circuit for automatically shutting down a phase-locked loop oscillator according to claim 2, wherein: The mirror current of the stable operating current of the voltage-controlled oscillator passing through the second PMOS tube is greater than the reference current source, and the reference current source is 1 / 2n times the stable operating current of the voltage-controlled oscillator, where n is the size ratio of the first PMOS tube to the second PMOS tube; the stable operating current of the voltage-controlled oscillator is greater than the startup current provided by the startup current source.

Images