Nitride semiconductor device

Abstract

According to the nitride semiconductor device and the power device based on the nitride semiconductor material, grooves which are periodically arranged in the Z direction are formed in a nitride semiconductor layer between a grid electrode structure and a drain electrode contact hole, when the device is turned on, the current direction is the X direction, the current path area in the Y-Z plane is increased, and resistance can be reduced.

Description

Technical Field

[0001] The present invention relates to a power device based on nitride semiconductor materials, in particular to the structure and manufacturing method of a HEMT device. Background Art

[0002] The following is an explanation of the relevant technical background. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. In the specific implementation, there is no restriction on a fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions, trenches, and material layers in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0003] Nitride semiconductor high electron mobility transistors (HEMTs) are high-performance electronic devices based on wide-bandgap semiconductor materials such as gallium nitride (GaN) and aluminum nitride (AlN). Compared to traditional silicon-based devices, they offer significant advantages in on-resistance, power density, switching speed, and loss.

[0004] An existing enhancement mode nitride semiconductor material high electron mobility transistor structure is as follows Figure 1 As shown. It includes: a substrate layer 100 at the bottom, a buffer layer 101 located above the substrate layer, a nitride semiconductor layer 102 located above the buffer layer, and an original barrier layer 103 located above the nitride semiconductor layer. The nitride semiconductor layer 102 is gallium nitride, the original barrier layer 103 is aluminum gallium nitride, and a two-dimensional electron gas is formed at the interface between the nitride semiconductor layer 102 and the original barrier layer 103. In addition, the device also includes: a source metal 222 and a drain metal 221 connected to the semiconductor, and a patterned gate structure located above the original barrier layer 103. A typical gate structure also includes: a P-type nitride semiconductor layer 110, and a gate metal layer 120 located above the P-type nitride semiconductor layer. Furthermore, a passivation layer 104 is grown above the original barrier layer 103 and the gate metal layer 120 to protect the surface of the nitride semiconductor material high electron mobility transistor.

[0005] In the aforementioned device, a two-dimensional electron gas (2DEG) is formed at the interface between the nitride semiconductor layer 102 and the original barrier layer 103, serving as the device's current path and affecting the device's on-resistance. Generally, a higher concentration of 2DEG helps reduce the device's on-resistance. However, increasing the 2DEG concentration is often subject to numerous process and device design limitations. Due to the minimum turn-on voltage, the energy band height of the original barrier layer 103 should not be set too high, thus limiting further increases in the 2DEG concentration and, consequently, reducing the device's on-resistance. Summary of the Invention

[0006] In order to solve the above-mentioned problems, the present invention provides the following technical solution: A nitride semiconductor device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a nitride semiconductor layer above the buffer layer, a barrier layer above the nitride semiconductor layer, a gate structure above the barrier layer, a passivation layer, a source contact hole and a drain contact hole on both sides of the gate structure, and a source metal and a drain metal above the device that pass through the passivation layer and connect to the semiconductor layer. The device is characterized in that the nitride semiconductor layer between the gate structure and the drain contact hole is further provided with one or more grooves periodically arranged in the Z direction, the grooves extending from near the gate structure to the drain contact hole, the barrier layer covering the inner wall of the groove, and a two-dimensional electron gas formed at the interface between the nitride semiconductor layer and the barrier layer.

[0007] Furthermore, the thickness of the barrier layer on the inner wall of the series of trenches is smaller than the thickness of the barrier layer at the gate structure.

[0008] Furthermore, the passivation layer extends into the groove and is disposed on the barrier layer.

[0009] Furthermore, the source metal extends downward into the passivation layer in the trench.

[0010] Furthermore, the width of the source metal extending into the trench gradually decreases along the X direction, or the width of the trench and the source metal extending into the trench gradually decreases along the X direction.

[0011] Furthermore, the depth of the source metal in the trench extending downward gradually becomes shallower in the X direction.

[0012] Furthermore, the groove is an inclined groove that is larger at the top and smaller at the bottom.

[0013] Furthermore, an insulating layer is filled above the barrier layer in the trench, and the passivation layer is provided above the insulating layer.

[0014] Furthermore, the barrier layer in the trench is filled with one or more alternately stacked P-type nitride filling layers and insulating layers.

[0015] Furthermore, the trench is divided into region a, region b, and region c along the X direction, wherein region a is close to one side of the gate structure, an insulating layer is filled above the barrier layer in the trench in region a, and the source metal extends downward into the insulating layer in this region; an insulating material is filled above the barrier layer in the trench in region b, an insulating layer is filled above the insulating material, and the source metal extends downward into the insulating layer in this region; an insulating material is filled above the barrier layer in the trench in region c, and an insulating layer is formed above the trench.

[0016] The present invention provides grooves periodically arranged in the Z direction in the nitride semiconductor layer between the gate structure and the drain contact hole. When the device is turned on, the current direction is in the X direction, and the current path area in the YZ plane is increased, which is beneficial to reducing resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of an existing enhanced nitride semiconductor material high electron mobility transistor.

[0018] Figure 2 Schematic diagram of a series of trench structures of an enhancement mode nitride semiconductor material high electron mobility transistor according to an embodiment of the present invention.

[0019] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure of the device at line A. Figure 4 for Figure 1 The schematic diagram of the structure of the existing device on the YZ plane.

[0020] Figure 5-8 Schematic diagrams of a series of trench structures according to different embodiments of the present invention on the YZ plane.

[0021] Figure 9 FIG. 1 is a schematic diagram of an XZ plane of a trench structure having a field plate structure according to an embodiment of the present invention.

[0022] Figure 10 for Figure 9 An XZ-plane schematic diagram of a trench structure according to a variation of the embodiment basis.

[0023] Figure 11-12 for Figure 10 XZ plane schematic diagram of the groove structure at different positions in the embodiment.

[0024] Figure 13 FIG. 1 is a YZ plane schematic diagram of a trench structure having a field plate structure according to another embodiment of the present invention.

[0025] Figure 14-16 for Figure 13XZ plane schematic diagram of the groove structure at different positions in the embodiment. DETAILED DESCRIPTION

[0026] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0027] A nitride semiconductor material high electron mobility transistor device of the present invention is implemented as follows Figure 2 These include: A substrate layer 100 at the bottom, a buffer layer 101 located above the substrate layer, and a nitride semiconductor layer 102 located above the buffer layer; a barrier layer 203 located above the nitride semiconductor layer 102 and a gate structure 210 located above the barrier layer 203; A source contact hole 221 and a drain contact hole 220 located on both sides of the gate structure 210; Also included is a series of trenches 230 within the nitride semiconductor layer 102 between the gate structure 210 and the drain contact hole 220 ; In addition, it also includes: a source metal 222 and a drain metal 223 located above the device and connected to the semiconductor layer through the passivation layer.

[0028] Generally, the series of trenches 230 extend along the shortest distance direction (X direction) between the gate structure 210 and the drain contact hole 220 , and are periodically arranged in a direction perpendicular to the shortest distance direction (Z direction).

[0029] In a practical embodiment, the depth of the series of grooves 230 is between 0.2-5 um, the width may be between 0.2-5 um, and the interval between adjacent series of grooves may be between 0.5-5 um.

[0030] The series of trenches 230 have a barrier layer 203 therein, and a two-dimensional electron gas is formed in the nitride semiconductor layer 102 adjacent to the sidewalls thereof. In a practical embodiment, the thickness of the barrier layer is between 1 and 20 nm.

[0031] In some embodiments, the barrier layer material structure and thickness within the series of trenches 230 may differ from the barrier layer structure and thickness at the gate structure, thereby facilitating adjustment of the two-dimensional electron gas concentration near the series of trenches 230 without affecting the device turn-on voltage. For example, in one embodiment, the barrier layer 203 at the gate structure has a thickness between 10 and 100 nm, while the barrier layer at the inner wall of the series of trenches 230 has a thickness between 1 and 50 nm, with the barrier layer thickness at the inner wall of the series of trenches 230 being less than the barrier layer 203 at the gate structure.

[0032] Typically, the series of trenches 230 contacts the adjacent drain contact holes 220 and the drain metal 223 in the drain contact holes. The depth of the drain contact holes 220 is shallower than the depth of the series of trenches 230. In a practical embodiment, the depth of the drain contact holes 220 is between 0.1 and 1 μm.

[0033] The drain metal 223 can be made of gold, nickel, titanium, aluminum or other metals, which is conducive to forming an ohmic contact between the drain metal 223 and the two-dimensional electron gas layer in the series of trenches 230, thereby reducing the on-resistance of the device.

[0034] In some variations of the embodiments, the drain metal 223 in the drain contact hole 220 may form a partial Schottky contact (side) with a portion of the nitride semiconductor layer 102 interface and provide a hole path during the switching process, which is beneficial to the reliability of the device.

[0035] Figure 3 The structure of the series of grooves 230 on the YZ plane of the first embodiment of the present invention is shown. Figure 4 for Figure 1 The schematic diagram of the structure of the existing device on the YZ plane.

[0036] like Figure 3 As shown, in addition to the barrier layer 203 on the sidewalls of the series of trenches 230, a passivation layer 204 may be filled in the barrier layer 203. The passivation layer 204 is usually an insulator and has functions such as regulating stress, regulating the concentration of the two-dimensional electron gas, and alleviating electron trapping.

[0037] The two-dimensional electron gas located on the sidewalls of the series of trenches 230 is interconnected with the two-dimensional electron gas formed in the nitride semiconductor layer 102 located on the upper surface of the device and below the barrier layer 203, forming a current path. When the device is turned on, the current is directed in the X direction. The larger the current path area in the YZ plane, the lower the resistance. Figure 4 The YZ plane structural diagram of the existing device in the figure shows that the two-dimensional electron gas path area and the current path area of ​​the device of the present invention are larger, which is beneficial to reducing the on-resistance of the device.

[0038] The following are modified embodiments of the device of the present invention.

[0039] Figure 5 for Figure 3 A schematic diagram of a groove structure on the YZ plane of a variation of the embodiment. Figure 3 Compared with the medium structure, Figure 5The grooves are inclined and larger at the top and smaller at the bottom, with the angle of the groove sidewalls ranging from 30-80 degrees. Typically, the inclined groove depth is between 0.5-4um, the width may be between 0.5-8um, and the spacing between adjacent series of grooves may be between 1-10um.

[0040] and Figure 3 Compared with the vertical grooves in the structure, Figure 5 The embodiment is beneficial to reducing stress caused by deep trenches, improving surface defects of the nitride semiconductor layer 102 and the crystal quality of the barrier layer 203, and is beneficial to reducing the electric field on the sidewalls and bottom of the trench when the device is reverse biased.

[0041] In some embodiments, the bottom of the trench is arc-shaped. Further, in some embodiments, the sidewalls of the trench may be gently arc-shaped.

[0042] In some embodiments, the inclined trenches are formed by isotropic etching, which facilitates the formation of smooth sidewalls.

[0043] Figure 6 for Figure 3 A schematic diagram of a groove structure on the YZ plane of a variation of the embodiment. Figure 3 Compared with the medium structure, Figure 6 In the trench, the barrier layer 203 is filled with a filling insulating layer 211 having a specific thermal expansion coefficient.

[0044] The specific thermal expansion coefficient passivation layer 211 filled in the trench usually has a thermal expansion coefficient that matches the barrier layer material, thereby reducing thermal stress caused by materials with different thermal expansion coefficients during temperature changes and preventing cracks or interface defects in the barrier layer.

[0045] The thermal expansion coefficient of the filling insulating layer 211 may be different from that of the passivation layer 204 on the upper surface, and plays a role in reducing stress in the trench. In some embodiments, the filling insulating layer 211 may be a nitride insulating material or an organic compound such as a polymer.

[0046] In a practical embodiment, the nitride semiconductor 102 is gallium nitride, the barrier layer is aluminum gallium nitride, and the filling insulating layer 211 may be made of hafnium dioxide, aluminum oxide, zirconium oxide, magnesium oxide, etc. The thermal expansion coefficient of the filling insulating layer 211 may be 4.5–5.8×10 -6 K.

[0047] In some alternative embodiments, the filling insulating layer 211 may have a stacked structure of upper and lower layers, each formed of different materials, to alleviate stress at different locations within the deep trench. In one practical embodiment, an upper layer of aluminum oxide and a lower layer of hafnium dioxide are stacked. Both are stable oxides with no significant chemical reaction, resulting in a stable interlayer interface.

[0048] There are various methods for forming the filling insulating layer 211. In some embodiments, the filling material can be deposited by low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or plasma-enhanced chemical vapor deposition (PECVD). The excess STEC passivation layer 211 on the top is then removed by photolithography or self-aligned etching, and the passivation layer 204 is then deposited thereon.

[0049] Figure 7 for Figure 6 A schematic diagram of a groove structure on the YZ plane of a variation of the embodiment. Figure 6 Compared with the structure in FIG, the trench bottom of this structure has a P-type nitride filling layer 212 .

[0050] In some embodiments, the P-type nitride semiconductor layer 212 may be connected to a gate or a drain. In some embodiments, the P-type nitride semiconductor layer 212 may form a Schottky contact with the gate or drain metal and form a hole path.

[0051] The P-type nitride semiconductor layer 212 and barrier layer 203 may form a potential barrier, intercepting the two-dimensional electron gas at the bottom of the trench, at the interface between the barrier layer 203 and the nitride semiconductor layer 102. Adjusting the doping concentration of the P-type nitride semiconductor layer 212 and the thickness of the barrier layer 203 can improve the device's withstand voltage and reduce dynamic resistance and reliability issues caused by hole trapping.

[0052] In some variations of the embodiments, the P-type nitride semiconductor layer 212 and the filling insulating layer 211 may have a structure of stacked layers, and more than one layer may be stacked from the bottom to the top of the trench. The two may be stacked alternately from bottom to top multiple times. Each layer of the P-type nitride semiconductor layer 212 may have a different thickness and doping concentration, further addressing the problem of hole trapping at different positions on both sides outside the trench.

[0053] Figure 8 for Figure 3 A schematic diagram of a groove structure on the YZ plane of a variation of the embodiment. Figure 3 Compared with the structure in FIG4 , the center of the trench of this structure is filled with a filling source metal 222 .

[0054] Filling the source metal 222 is beneficial to reducing the upper surface electric field strength when the device is reverse biased, thereby increasing the breakdown voltage of the device.

[0055] In a practical embodiment, the trench width is between 0.5-5 um, the thickness of the passivation layer 204 on the sidewall is between 0.1-2 um, and the width of the source metal 222 filled in the trench is between 0.05-1 um.

[0056] In some embodiments, the source metal 222 filled in the trench may have a top-larger, bottom-smaller morphology. In some embodiments, the passivation layer 204 filling the sidewalls of the source metal 222 has a top-thinner, bottom-thicker morphology. This top-thinner, bottom-thicker morphology can effectively increase the vertical withstand voltage capability of the device.

[0057] Figure 9 for Figure 8 An XZ-plane top plan view of a series of trench structures according to a variation of the embodiment.

[0058] In this embodiment, the source metal filling 222 in the trench has a varying width along the X direction, being wider near the gate structure 210 and narrower near the drain contact hole 220. This structure helps adjust the electric field distribution on the device surface and increase the lateral breakdown voltage.

[0059] Figure 10-12 for Figure 9 A variation of the embodiment. Figure 10 This is an XZ-plane top view of the series of trench structures of this embodiment. Figure 11 、 Figure 12 is a schematic cross-sectional view of the YZ plane top of this embodiment and corresponds to Figure 10 Tangents A and B in .

[0060] In this embodiment, the series of trenches 230 and the filled source metal 222 have varying widths along the X-direction, with the width being wider near the gate structure 210 and narrower near the drain contact hole 220. In the trenches near the drain contact hole 220, only the passivation layer 204 is present, without the filled source metal 222.

[0061] Typically, in this embodiment, the thickness of the passivation layer 204 on both sides of the source metal 222 in the trench is the same. The above structure is conducive to optimizing the electric field distribution when the device is reverse biased.

[0062] In some embodiments, the depth of the filled source metal 222 along the Z direction varies, with a deeper depth near the gate structure 210 and a shallower depth near the drain contact hole 220, i.e., gradually becoming shallower in the X direction. This structure is beneficial for optimizing the electric field distribution when the device is reverse biased.

[0063] Figure 13-15 for Figure 8 A variation of the embodiment. Figure 13 This is an XZ-plane top view of the series of trench structures of this embodiment. Figure 14 、 Figure 15 、 Figure 16 is a schematic cross-sectional view of the YZ plane top of this embodiment and corresponds to Figure 13 The tangents A, B, and C in .

[0064] like Figure 13-15 As shown, the source metal 222 filled in the trench has different depths along the X-direction. The trench 230 is divided into regions a / b / c along the X-direction. The trench area near the gate structure 210 (region a) is filled with a barrier layer 203, an insulating layer 211, and the source metal 222. The central region of the trench (region b) is filled with a barrier layer 203, an insulating layer 211, and the source metal 222, with an insulator 225 underneath the insulating layer 211. The trench area near the drain contact hole 220 (region c) is filled with a barrier layer 203, an insulating layer 211 (the insulating layer covers the trench 230), and an insulator 225 underneath the insulating layer 211. The materials of the two materials are different. The insulator 225 can be selected from the materials mentioned above or the P-type nitride mentioned below, depending on the topography of the trench bottom.

[0065] In some embodiments, part or all of the fill insulator 225 may be a P-type nitride. In some embodiments, the P-type nitride may be connected to a metal. This configuration helps reduce the charge trapping problem in the device.

[0066] In a formation method of one embodiment, a barrier layer 203 may be formed in the trench first, then filled with an insulating material 225 and etched to form a filling insulating material 225 at a defined position, then filled with an insulating layer 211 , and then the source metal 222 is formed.

[0067] Those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures and manufacturing processes of embodiments of the present invention.

Claims

1. A nitride semiconductor device, comprising a substrate layer (100) at the bottom, a buffer layer (101) located above the substrate layer, a nitride semiconductor layer (102) located above the buffer layer, a barrier layer (203) located above the nitride semiconductor layer (102), a gate structure (210) located above the barrier layer (203), a passivation layer (204), a source contact hole (221) and a drain contact hole (222) located on both sides of the gate structure (210), and a source metal (222) and a drain metal (223) located above the device and connected to the semiconductor layer through the passivation layer, wherein: One or more grooves (230) arranged periodically in the Z direction are further provided in the nitride semiconductor layer (102) between the gate structure (210) and the drain contact hole (222). The grooves (230) extend from the vicinity of the gate structure (210) to the drain contact hole (222). The barrier layer (203) covers the inner wall of the groove (230). A two-dimensional electron gas is formed at the interface between the nitride semiconductor layer (102) and the barrier layer (203).

2. The nitride semiconductor device according to claim 1, wherein The thickness of the barrier layer (203) on the inner wall of the series of trenches (230) is smaller than the thickness of the barrier layer (203) at the gate structure (210).

3. The nitride semiconductor device according to claim 1, wherein The passivation layer (204) extends toward the interior of the groove (230) and is arranged on the barrier layer (203).

4. The nitride semiconductor device according to claim 3, wherein The source metal (222) extends downward into the passivation layer (204) within the trench (230).

5. The nitride semiconductor device according to claim 4, wherein The width of the source metal (222) extending into the groove (230) gradually decreases along the X direction, or the width of the groove (230) and the source metal (222) extending into the groove (230) gradually decreases along the X direction.

6. The nitride semiconductor device according to claim 5, wherein The depth of the source metal (222) extending downward in the trench (230) gradually becomes shallower in the X direction.

7. The nitride semiconductor device according to claim 1, wherein The groove (230) is an inclined groove that is larger at the top and smaller at the bottom.

8. The nitride semiconductor device according to claim 1, wherein An insulating layer (211) is filled above the barrier layer (203) in the groove (230), and the passivation layer (204) is provided above the insulating layer (211).

9. The nitride semiconductor device according to claim 1, wherein The barrier layer (203) in the trench (230) is filled with one or more alternately stacked P-type nitride filling layers (212) and insulating layers (211).

10. The nitride semiconductor device according to claim 1, wherein The groove (230) is divided into region a, region b, and region c along the X direction, wherein region a is close to one side of the gate structure (210), an insulating layer (211) is filled above the barrier layer (203) in the groove of region a, and the source metal (222) extends downward into the insulating layer (211) in this region; an insulating material (225) is filled above the barrier layer (203) in the groove of region b, an insulating layer (211) is filled above the insulating material (225), and the source metal (222) extends downward into the insulating layer (211) in this region; an insulating material (225) is filled above the barrier layer (203) in the groove of region c, and the insulating layer (211) is located above the groove.

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