Class II superlattice medium wave infrared focal plane array chip manufacturing method and infrared detector

Abstract

The invention provides a manufacturing method of a type-II superlattice medium-wave infrared focal plane array chip and an infrared detector, and belongs to the field of infrared focal plane array chips. The problem that in the prior art, the surface leakage current of an infrared focal plane array chip is large due to the fact that the mesa etching depth is large is solved. The method comprises the following steps: growing and cleaning an epitaxial material; hard mask deposition, mesa photoetching and etching: obtaining a required mesa pattern on the hard mask through a photoetching technology, then etching an epitaxial material, etching the epitaxial material to form the mesa pattern, the mesa pattern comprising an upper electrode region and a lower electrode region, etching the upper electrode region to the boundary of the barrier layer and the absorption region, and etching the lower electrode region to the boundary of the barrier layer and the absorption region; etching a lower electrode region to the lower ohmic contact layer; manufacturing a metal electrode; a connecting piece is manufactured on the metal electrode to be connected with a reading circuit, and manufacturing of the infrared focal plane array chip is completed; the invention is applied to the II-type superlattice medium-wave infrared detector.

Description

Technical Field

[0001] The present application relates to the technical field of infrared focal plane array chips, and in particular to a method for manufacturing a type II superlattice medium-wave infrared focal plane array chip and an infrared detector. Background Art

[0002] Infrared detectors are widely used in various fields, including national defense and the national economy, due to their smoke-penetrating capabilities, strong anti-interference capabilities, and all-weather operation. Type II superlattice infrared focal plane array chips have garnered considerable attention due to their wide spectral response range, high detection sensitivity, fast response speed, low noise levels, and excellent integration.

[0003] The Type II superlattice medium-wave infrared focal plane array chip includes an interconnected infrared detection unit array and a readout circuit. The existing method for manufacturing the Type II superlattice medium-wave infrared focal plane array chip is to first prepare the infrared detection unit array and then interconnect it with the readout circuit by reverse soldering. The specific method is as follows: 1. Epitaxial material growth; 2. Epitaxial material cleaning and hard mask deposition; 3. Mesa lithography and etching. Mesa lithography is to make the mesa pattern to be etched on silicon oxide, and use photoresist as a mask to etch silicon oxide into the required mesa pattern. Then, remove the residual photoresist by cleaning. Mesa etching is to use silicon oxide as a mask to etch the epitaxial material into the required mesa pattern. The mesa pattern includes the upper electrode area and the lower electrode area, such as Figure 1 As shown; 4. Make metal electrodes on the etched epitaxial material, such as Figure 2 As shown; 5. Fabricate indium pillars on the metal electrodes and connect the indium pillars to the readout circuit by reverse soldering to complete the infrared focal plane array chip fabrication. Figure 3 shown.

[0004] When etching the mesa with existing technology, the etching depth reaches the boundary between the absorption region and the lower ohmic contact layer, and the mesa etching depth is relatively deep. The mesa etching adopts the ICP etching (Inductively Coupled Plasma Etching) method. After ICP etching, it will cause significant damage to the surface of the etched material. At the same time, some etching products will remain on the etched surface after ICP etching. These etching damages and residual etching products will form leakage current channels, resulting in large surface leakage current. Large surface leakage current will have a harmful effect on the final performance of the infrared focal plane array chip. Figure 4 As shown, the dotted arrows represent the leakage current channel on the etched surface, and the solid arrows represent the current channel generated by the bias voltage loaded on the infrared focal plane array chip.

[0005] The operating principle of a Type II superlattice medium-wave infrared focal plane array chip is the photovoltaic effect. This is when the infrared signal detected by the infrared focal plane array chip reaches the absorption region of the epitaxial material, generating a photocurrent. If the surface leakage channel is large, the bias voltage applied to the infrared focal plane array chip will generate surface leakage current through the surface leakage channel, preventing the photovoltaic current from being output, ultimately degrading the infrared focal plane array chip's performance.

[0006] Therefore, the existing technology has a deep mesa etching depth, which will lead to a larger mesa surface leakage channel, and further lead to a large surface leakage current of the infrared focal plane array chip, which seriously affects the performance of the infrared focal plane array chip. Summary of the Invention

[0007] In order to solve the above technical problems, this application proposes a method for manufacturing a type II superlattice medium-wave infrared focal plane array chip and an infrared detector, which can effectively reduce the surface leakage current of the type II superlattice medium-wave infrared focal plane array chip and improve the comprehensive performance of the type II superlattice medium-wave infrared focal plane array chip.

[0008] The technical solution adopted in this application is: a method for manufacturing a type II superlattice medium-wave infrared focal plane array chip, comprising the following steps: Step 1: epitaxial material growth and cleaning, wherein the epitaxial material includes a substrate, a buffer layer, a lower ohmic contact layer, an absorption region, a barrier layer and an upper ohmic contact layer from bottom to top; Step 2: Hard mask deposition, mesa lithography and etching: The required mesa pattern is obtained on the hard mask by photolithography technology, and then the epitaxial material is etched to form the mesa pattern. The mesa pattern includes the upper electrode area and the lower electrode area. The upper electrode area is etched to the boundary between the barrier layer and the absorption region, and the lower electrode area is etched to the lower ohmic contact layer. Step 3: Fabricate a metal electrode on the epitaxial material after etching the mesa pattern; Step 4: Make connectors on the metal electrodes and connect the metal electrodes to the readout circuit through the connectors to complete the production of the infrared focal plane array chip.

[0009] Furthermore, the hard mask deposition, mesa lithography and etching in step 2 are performed on the upper electrode and the lower electrode respectively, and specifically include the following steps: Step 2.1: Deposition of bottom electrode hard mask; Step 2.2: photolithography of the lower electrode to form a photolithographic pattern of the lower electrode; Step 2.3: Etching the lower electrode hard mask: Etching the lower electrode hard mask to transfer the photolithographic pattern of the lower electrode onto the lower electrode hard mask; Step 2.4: Remove the remaining photoresist on the bottom electrode hard mask by cleaning; Step 2.5: Etching the lower electrode epitaxial material: Etching the lower electrode area to the lower ohmic contact layer; Step 2.6: Upper electrode etching hard mask deposition; Step 2.7: Photolithography of the upper electrode to form a photolithographic pattern of the upper electrode; Step 2.8: Etching the upper electrode hard mask: Etching the upper electrode hard mask to transfer the photolithographic pattern of the upper electrode onto the upper electrode hard mask; Step 2.9: Remove the remaining photoresist on the upper electrode hard mask by cleaning. Step 2.10: Etching the epitaxial material of the top electrode: Etching the epitaxial material until the top electrode region reaches the boundary between the barrier layer and the absorption region; Step 2.11: Passivation film deposition; Step 2.12: Passivation opening etching: Place the epitaxial material on the carrier of the dry etching equipment, and run the dry etching program to perform the opening etching process on the passivation film.

[0010] Furthermore, the compositions of the lower ohmic contact layer, the absorption region and the upper ohmic contact layer are all InAs / InAsSb, the composition of the barrier layer is AlSb / AlAsSb, and the composition of the substrate and the buffer layer is GaSb.

[0011] Furthermore, both the lower ohmic contact layer and the upper ohmic contact layer are N-type ohmic contact layers.

[0012] Furthermore, the lower electrode hard mask and the upper electrode hard mask are both made of silicon oxide.

[0013] Furthermore, in both step 2.3 and step 2.8, the lower electrode hard mask and the upper electrode hard mask are etched by dry etching.

[0014] Furthermore, in both step 2.5 and step 2.10, the epitaxial material is dry-etched using silicon oxide as a mask.

[0015] Furthermore, the production of the metal electrodes in step three includes the production of upper and lower metal electrodes: the production of the upper and lower metal electrodes is completed through the processes of photolithography, evaporation, and organic cleaning and stripping.

[0016] Furthermore, the connecting piece in step 4 is made of indium column, which is manufactured through photolithography, evaporation, and organic cleaning and stripping processes.

[0017] A type II superlattice medium-wave infrared detector comprises an infrared focal plane array chip prepared by adopting the method for preparing the type II superlattice medium-wave infrared focal plane array chip.

[0018] The beneficial effects of the present application compared to the prior art are as follows: when etching the mesa using the method of the present application, the etching depth of the upper electrode area reaches the boundary between the barrier layer and the absorption area, and the etching depth of the lower electrode area reaches the lower ohmic contact layer. Under the premise of ensuring the performance of the medium-wave infrared focal plane array chip, the etched surface area of ​​the mesa sidewall can be reduced, thereby reducing the surface leakage current of the medium-wave infrared focal plane array chip and improving the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present application will be further described below with reference to the accompanying drawings: Figure 1 A schematic diagram of the structure of a mesa pattern formed by etching using existing technology; Figure 2 This is a schematic diagram of the structure after metal electrodes are made on the table using existing technology; Figure 3 This is a schematic diagram of the structure of the indium column manufactured using the existing technology and the indium column and the readout circuit after the reverse solder connection; Figure 4 Schematic diagram of the etched surface and leakage current channel structure formed after etching the mesa using the existing technology; Figure 5 This is a schematic diagram of the structure after etching the mesa using the method proposed in this application; Figure 6 Schematic diagram of the etched surface and leakage current channel structure formed after etching the mesa using the method proposed in this application; Figure 7 This is a schematic diagram of the structure after the metal electrode is made on the table using the method proposed in this application; Figure 8 This is a schematic diagram of the structure after the indium column is manufactured using the method proposed in this application and the indium column and the readout circuit are interconnected by reverse soldering. DETAILED DESCRIPTION

[0020] like Figures 5 to 8 As shown, the present application provides a method for manufacturing a type II superlattice medium-wave infrared focal plane array chip. The main difference from the prior art is that when etching the mesa, the etching depth of the upper electrode area reaches the boundary between the barrier layer and the absorption region, and the etching depth of the lower electrode area reaches the lower ohmic contact layer. Figure 5 This etching depth structure can reduce the etched surface area of ​​the mesa sidewall while ensuring the performance of the MWIR FPA chip, as shown in Figure 2. Figure 6 As shown, the surface leakage current of the medium-wave infrared focal plane array chip is reduced and the chip performance is improved.

[0021] After the etching of the mesa and the lower electrode area is completed, the upper and lower electrodes are fabricated by photolithography, electron beam evaporation coating, and metal stripping and cleaning. Figure 7After the upper and lower electrodes are fabricated, the indium pillars are fabricated by photolithography, electron beam evaporation, and metal stripping and cleaning. After the indium pillars are fabricated, the infrared detection unit array and the readout circuit are interconnected by flip-flop soldering, thus completing the entire process of fabricating the infrared focal plane array chip. Figure 8 The infrared focal plane array chip shown.

[0022] Based on this, the steps for implementing the method for manufacturing a type II superlattice medium-wave infrared focal plane array chip given in the embodiment of the present application are as follows: Step 1: epitaxial material growth and cleaning, wherein the epitaxial material includes a substrate, a buffer layer, a lower ohmic contact layer, an absorption region, a barrier layer and an upper ohmic contact layer from bottom to top; Step 2: Hard mask deposition, mesa lithography, and etching: The required mesa pattern is obtained on the hard mask by photolithography technology, and then the epitaxial material is etched to form the mesa pattern. The mesa pattern includes the upper electrode region and the lower electrode region. The upper electrode region is etched to the boundary between the barrier layer and the absorption region, and the lower electrode region is etched to the lower ohmic contact layer. Step 3: Fabricate a metal electrode on the epitaxial material after etching the mesa pattern; Step 4: Make connectors on the metal electrodes and connect the metal electrodes to the readout circuit through the connectors to complete the production of the infrared focal plane array chip.

[0023] Specifically, the epitaxial material in step 1 is grown using an MBE (Molecular Beam Epitaxy) device. It includes, from bottom to top, a GaSb substrate, a GaSb buffer layer, a lower N-type ohmic contact layer, an absorption region, a barrier layer, and an upper N-type ohmic contact layer. The upper and lower N-type ohmic contact layers and the absorption region of the epitaxial material are all composed of InAs / InAsSb, while the barrier layer is composed of AlSb / AlAsSb.

[0024] After the epitaxial material growth is completed in step 1, the surface of the epitaxial material is organically cleaned using cleaning solvents such as acetone, ethanol, and isopropanol in sequence. The cleaning is performed by heating the surface of the epitaxial material in a water bath at a temperature of 70°C.

[0025] The hard mask deposition, mesa lithography and etching in step 2 are performed on the upper electrode and the lower electrode respectively, and specifically include the following steps: Step 2.1: After cleaning, the lower electrode hard mask is deposited: the lower electrode hard mask is made of silicon oxide, and the deposition method is PECVD (Plasma-Enhanced Chemical Vapor Deposition), with a deposition thickness of 400nm.

[0026] Step 2.2: Photolithography of the lower electrode: Use AZ6130 photoresist with a thickness of 3 μm, an exposure dose of 60 mJ, and a development time of 30 s to form a photolithographic pattern of the lower electrode.

[0027] Step 2.3: Etching the lower electrode hard mask: Use dry etching to etch the lower electrode hard mask, transfer the photolithographic pattern of the lower electrode onto the lower electrode hard mask, and use carbon tetrafluoride and trifluoromethane as etching gases for 15 minutes.

[0028] Step 2.4: Remove the remaining photoresist on the bottom electrode hard mask by cleaning. The cleaning solvent is acetone, heated in a water bath at 70°C, and the cleaning time is 30 minutes.

[0029] Step 2.5: Etching the lower electrode epitaxial material: Etch the lower electrode area to the lower ohmic contact layer, and dry-etch the epitaxial material using silicon oxide as a mask. The equipment used is an ICP etching equipment, and the etching gases are chlorine, boron trichloride, and argon. The etching time is 15 minutes and the etching depth is 4 μm.

[0030] Step 2.6; Deposition of upper electrode etching hard mask: The upper electrode hard mask is made of silicon oxide, deposited by PECVD, and has a deposition thickness of 200 nm.

[0031] Step 2.7: Photolithography of the upper electrode: Use AZ6130 photoresist with a thickness of 3 μm, an exposure dose of 60 mJ, and a development time of 30 s to form a photolithographic pattern of the upper electrode.

[0032] Step 2.8: Etching the upper electrode hard mask: Use dry etching to etch the upper electrode hard mask, transfer the photolithographic pattern of the upper electrode onto the upper electrode hard mask, and use carbon tetrafluoride and trifluoromethane as etching gases for 10 minutes.

[0033] Step 2.9: Remove the remaining photoresist on the upper electrode hard mask by cleaning. The cleaning solvent is acetone, heated in a water bath at 70°C, and the cleaning time is 30 minutes.

[0034] Step 2.10: Etching of epitaxial material of top electrode: Using silicon oxide as mask, dry-etch the epitaxial material and etch the top electrode area to the boundary between the barrier layer and the absorption region. The equipment used is ICP etching equipment, and the etching gas is chlorine, boron trichloride, and argon. The etching time is 3 minutes and the etching depth is 600nm. After the top electrode etching is completed, the following is obtained: Figure 5 The structure shown.

[0035] Step 2.11: Passivation film deposition: The passivation film is made of silicon oxide, deposited by PECVD, and has a deposition thickness of 300 nm.

[0036] Step 2.12: Passivation Opening Etch: Place the epitaxial material onto the carrier of the dry etching equipment and run the dry etching process to perform opening etching on the passivation film. The dry etching process uses carbon tetrafluoride and trifluoromethane as the etching gases, a carrier temperature of 20°C, a process chamber pressure of 30mTorr, and an RF power of 135W.

[0037] The production of metal electrodes in step 3 includes the production of upper and lower metal electrodes: the production of upper and lower metal electrodes is completed through the processes of photolithography, evaporation, organic cleaning and stripping. After the production of the upper and lower electrodes is completed, the following is obtained: Figure 7 The structure shown.

[0038] The connecting parts in step 4 are indium pillars in this embodiment, which are made by photolithography, evaporation, organic cleaning and stripping. Finally, the infrared detection unit array and the readout circuit are interconnected by reverse soldering to obtain the following: Figure 8 The infrared focal plane array chip shown.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a type II superlattice medium-wave infrared focal plane array chip, characterized by: The following steps are involved: Step 1: epitaxial material growth and cleaning, wherein the epitaxial material includes a substrate, a buffer layer, a lower ohmic contact layer, an absorption region, a barrier layer and an upper ohmic contact layer from bottom to top; Step 2: Hard mask deposition, mesa lithography, and etching: The required mesa pattern is obtained on the hard mask by photolithography technology, and then the epitaxial material is etched to form the mesa pattern. The mesa pattern includes the upper electrode area and the lower electrode area. The upper electrode area is etched to the boundary between the barrier layer and the absorption region, and the lower electrode area is etched to the lower ohmic contact layer. Step 3: Fabricate a metal electrode on the epitaxial material after etching the mesa pattern; Step 4: Make connectors on the metal electrodes and connect the metal electrodes to the readout circuit through the connectors to complete the production of the infrared focal plane array chip.

2. The method for fabricating a type II superlattice medium-wave infrared focal plane array chip according to claim 1, characterized in that: The hard mask deposition, mesa lithography and etching in step 2 are performed on the upper electrode and the lower electrode respectively, and specifically include the following steps: Step 2.1: Deposition of bottom electrode hard mask; Step 2.2: photolithography of the lower electrode to form a photolithographic pattern of the lower electrode; Step 2.3: Etching the lower electrode hard mask: Etching the lower electrode hard mask to transfer the photolithographic pattern of the lower electrode onto the lower electrode hard mask; Step 2.4: Remove the remaining photoresist on the bottom electrode hard mask by cleaning; Step 2.5: Etching the lower electrode epitaxial material: Etching the lower electrode area to the lower ohmic contact layer; Step 2.6: Upper electrode etching hard mask deposition; Step 2.7: Photolithography of the upper electrode to form a photolithographic pattern of the upper electrode; Step 2.8: Etching the upper electrode hard mask: Etching the upper electrode hard mask to transfer the photolithographic pattern of the upper electrode onto the upper electrode hard mask; Step 2.9: Remove the remaining photoresist on the upper electrode hard mask by cleaning. Step 2.10: Etching the epitaxial material of the top electrode: Etching the epitaxial material until the top electrode region reaches the boundary between the barrier layer and the absorption region; Step 2.11: Passivation film deposition; Step 2.12: Passivation opening etching: Place the epitaxial material on the carrier of the dry etching equipment, and run the dry etching program to perform the opening etching process on the passivation film.

3. The method for fabricating a type II superlattice medium-wave infrared focal plane array chip according to claim 2, characterized in that: The compositions of the lower ohmic contact layer, the absorption region and the upper ohmic contact layer are all InAs / InAsSb, the composition of the barrier layer is AlSb / AlAsSb, and the composition of the substrate and the buffer layer is GaSb.

4. The method for fabricating a type II superlattice medium-wave infrared focal plane array chip according to claim 3, characterized in that: Both the lower ohmic contact layer and the upper ohmic contact layer are N-type ohmic contact layers.

5. The method for manufacturing a type II superlattice medium-wave infrared focal plane array chip according to claim 2, characterized in that: The lower electrode hard mask and the upper electrode hard mask are both made of silicon oxide.

6. The method for manufacturing a type II superlattice medium-wave infrared focal plane array chip according to claim 2, characterized in that: In both step 2.3 and step 2.8, the lower electrode hard mask and the upper electrode hard mask are etched by dry etching.

7. The method for manufacturing a type II superlattice medium-wave infrared focal plane array chip according to claim 2, characterized in that: In both steps 2.5 and 2.10, the epitaxial material is dry-etched using silicon oxide as a mask.

8. The method for manufacturing a type II superlattice medium-wave infrared focal plane array chip according to claim 1, characterized in that: The production of the metal electrodes in step three includes the production of upper and lower metal electrodes: the production of the upper and lower metal electrodes is completed through the processes of photolithography, evaporation, and organic cleaning and stripping.

9. The method for manufacturing a type II superlattice medium-wave infrared focal plane array chip according to claim 1, characterized in that: The connecting parts in step 4 are made of indium pillars, which are manufactured through photolithography, evaporation, and organic cleaning and stripping processes.

10. A type II superlattice medium-wave infrared detector, characterized in that: The invention comprises an infrared focal plane array chip prepared by adopting the method for preparing a type II superlattice medium-wave infrared focal plane array chip as described in any one of claims 1 to 9.

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