Multiplier circuits and electronic devices

Abstract

This invention relates to the field of multipliers, and discloses a multiplier circuit and electronic device. The multiplier circuit includes a first transistor to a twelfth transistor. The third terminal of the first transistor, the second terminal of the third transistor, and the first terminal of the tenth transistor are interconnected. The first terminal of the third transistor, the first terminal of the fourth transistor, and the third terminal of the tenth transistor are interconnected. The third terminal of the third transistor, the third terminal of the sixth transistor, the first terminal of the ninth transistor, and the second terminal of the ninth transistor are interconnected. The third terminal of the fourth transistor, the third terminal of the fifth transistor, and the second terminal of the eighth transistor are interconnected. The first terminal of the fifth transistor, the first terminal of the sixth transistor, and the third terminal of the eleventh transistor are interconnected. The third terminal of the second transistor is connected to the second terminal of the sixth transistor. This invention eliminates the deviation caused by the transistor base current and reduces the influence of the Erlich effect by setting the transistor collector voltage.

Description

Technical Field

[0001] This invention relates to the field of multipliers, and more particularly to a multiplier circuit and electronic device. Background Technology

[0002] Multipliers, as fundamental modules in integrated circuits, are widely used in many signal processing fields such as artificial neural networks, adaptive filtering, modulation and demodulation, and frequency conversion. Currently, many design techniques and circuit structures are focused on optimizing the performance of multipliers, such as high speed, low power consumption, low supply voltage, and high bandwidth. For example, in power factor correction (PFC) applications, most PFC control chips require multipliers to implement their functions.

[0003] There are various methods for designing multipliers: some utilize the square law relationship between the voltage and current of a MOSFET, some leverage the volt-ampere characteristic of the MOSFET in the linear region, and some use Gilbert cells. These methods generally suffer from drawbacks such as a small linear input range, large nonlinear errors, and high distortion. Another method uses a transistor with a logarithmic voltage-current relationship for multiplication, but this does not consider the Erlich effect of the transistor. Different collector-emitter voltage drops in transistors implementing a logarithmic relationship introduce linear errors; it also neglects the influence of the base current, which, when the transistor gain is not high, also introduces errors. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a multiplier circuit and electronic device that eliminates the deviation caused by the transistor base current, reduces the dependence on transistor amplification factor, process and temperature; and improves linearity by setting the transistor collector voltage to reduce the influence of the transistor Erlich effect.

[0005] The technical solution of the present invention is as follows:

[0006] A multiplier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0007] The first terminal, the second terminal, and the first terminal of the first transistor are used to connect to a first current. The third terminal, the second terminal, and the first terminal of the tenth transistor are interconnected. The first terminal, the first terminal, and the third terminal of the tenth transistor are interconnected. The second terminal of the tenth transistor is used to connect to a power supply. The third terminal, the third terminal, the first terminal, and the second terminal of the ninth transistor are interconnected. The second terminal of the fourth transistor and the first terminal of the twelfth transistor are used to connect to a second current. The third terminal, the third terminal, and the second terminal of the eighth transistor are interconnected. The second terminal of the transistor is used to connect to the power supply. The second terminal of the seventh transistor is used to connect to the power supply. The third terminal of the twelfth transistor and the first terminal of the seventh transistor are used to connect to the first bias current. The third terminal of the seventh transistor and the first terminal of the eighth transistor are used to connect to the second bias current. The second terminal of the fifth transistor and the first terminal of the eleventh transistor are used to connect to the third current. The first terminal of the fifth transistor, the first terminal of the sixth transistor, and the third terminal of the eleventh transistor are interconnected. The second terminal of the eleventh transistor is used to connect to the power supply. The second terminal of the second transistor is used to output the fourth current. The third terminal of the second transistor is connected to the second terminal of the sixth transistor. The third terminal of the ninth transistor and the third terminal of the eighth transistor are grounded.

[0008] Optionally, the first transistor, the second transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are NPN transistors. The first terminal of the first transistor, the second transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is the gate of the NMOS transistor. The second terminal of the first transistor, the second transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is the gate of the NMOS transistor. The third terminal of the first transistor, the second transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is the source of the NMOS transistor. The first terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor is the base of the NPN transistor. The second terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor is the collector of the NPN transistor. The third terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor is the emitter of the NPN transistor.

[0009] Optionally, the first and second transistors are NMOS transistors, and the third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are NPN transistors. The first terminal of the first and second transistors is the gate of the NMOS transistor, the second terminal of the first and second transistors is the drain of the NMOS transistor, and the third terminal of the first and second transistors is the source of the NMOS transistor. The first terminals of the transistors, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor, are the bases of the NPN transistors; the second terminals of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are the collectors of the NPN transistors; and the third terminals of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are the emitters of the NPN transistors.

[0010] Optionally, the NPN transistors are all the same size.

[0011] The present invention also proposes a multiplier circuit, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;

[0012] The first terminal, the second terminal, and the first terminal of the second transistor are used to connect to a first current. The third terminal, the first terminal, the second terminal, and the first terminal of the fourth transistor are interconnected. The third terminal, the third terminal, the first terminal, and the second terminal of the ninth transistor are interconnected. The second terminal of the fourth transistor and the first terminal of the seventh transistor are used to connect to a second current. The third terminal, the third terminal, and the second terminal of the eighth transistor are interconnected. The second terminal of the seventh transistor is used to connect to a power supply. The third terminal of the seventh transistor and the first terminal of the eighth transistor are used to connect to a third bias current. The first terminal, the second terminal, and the first terminal of the fifth transistor are used to connect to the third current. The second terminal of the second transistor is used to output a fourth current. The third terminal of the second transistor is connected to the second terminal of the sixth transistor. The third terminal of the ninth transistor and the third terminal of the eighth transistor are grounded.

[0013] Optionally, the first and second transistors are NMOS transistors, and the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors are NPN transistors. The first terminal of the first and second transistors is the gate of the NMOS transistor, the second terminal of the first and second transistors is the drain of the NMOS transistor, and the third terminal of the first and second transistors is the source of the NMOS transistor. The first terminal of the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors is the base of the NPN transistor, the second terminal of the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors is the collector of the NPN transistor, and the third terminal of the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors is the emitter of the NPN transistor.

[0014] Optionally, the amplification factor of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is greater than a preset amplification factor.

[0015] The present invention also proposes an electronic device comprising a plurality of multiplier circuits as described above or a plurality of multiplier circuits as described above, wherein the plurality of multiplier circuits are cascaded.

[0016] Optionally, the electronic device further includes:

[0017] Multiple current mirrors are provided, with their input terminals connected one-to-one to the output terminals of the multiple multiplier circuits. The current mirrors are used to convert the current signal output by the multiplier circuits into a current source for output.

[0018] Optionally, the electronic device further includes:

[0019] The processor has its input terminal connected to the output terminals of the plurality of current mirrors. The processor is used to receive current sources output by the plurality of current mirrors and to perform conversion processing on the current sources.

[0020] The multiplication and division relationships of the multiplier circuit of this invention are unaffected by parameters such as the transistor's amplification factor, and it has low dependence on process technology and temperature. The input current is introduced into negative feedback through the seventh and eighth transistors, improving circuit stability and enabling voltage matching of the fourth transistor, thus reducing the Earliest effect. This invention requires no additional operational amplifier, has a simple circuit structure, features negative feedback, and exhibits high stability. Furthermore, the matching between transistors gives the circuit structure advantages such as high linearity, low error, and low distortion, and it is free from the Earliest effect. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the multiplier circuit of the present invention.

[0023] Figure 2 This is a schematic diagram of the circuit structure of another embodiment of the multiplier circuit of the present invention.

[0024] Figure 3 This is a schematic diagram of the circuit structure of another embodiment of the multiplier circuit of the present invention.

[0025] Explanation of reference numerals in the attached diagram: MN1, first transistor; MN2, second transistor; Q1, third transistor; Q2, fourth transistor; Q3, fifth transistor; Q4, sixth transistor; Q5, seventh transistor; Q6, eighth transistor; Q7, ninth transistor; Q8, tenth transistor; Q9, eleventh transistor; Q10, twelfth transistor; I1, first current; I2, second current; I3, third current; I4, fourth current; Ibia1, first bias current; Ibia2, second bias current; Ibia3, third bias current; VCC, power supply. Detailed Implementation

[0026] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0027] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0028] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0029] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0030] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0031] Multipliers, as fundamental modules in integrated circuits, are widely used in many signal processing fields such as artificial neural networks, adaptive filtering, modulation and demodulation, and frequency conversion. Currently, many design techniques and circuit structures are focused on optimizing the performance of multipliers, such as high speed, low power consumption, low supply voltage, and high bandwidth. For example, in power factor correction (PFC) applications, most PFC control chips require multipliers to implement their functions.

[0032] There are various methods for designing multipliers: some utilize the square law relationship between the voltage and current of a MOSFET, some leverage the volt-ampere characteristic of the MOSFET in the linear region, and some use Gilbert cells. These methods generally suffer from drawbacks such as a small linear input range, large nonlinear errors, and high distortion. Another method uses a transistor with a logarithmic voltage-current relationship for multiplication, but this does not consider the Erlich effect of the transistor. Different collector-emitter voltage drops in transistors implementing a logarithmic relationship introduce linear errors; it also neglects the influence of the base current, which, when the transistor gain is not high, also introduces errors.

[0033] To address the above problems, this invention proposes a multiplier circuit.

[0034] Reference Figure 1 In one embodiment, the multiplier circuit includes a first transistor MN1, a second transistor MN2, a third transistor Q1, a fourth transistor Q2, a fifth transistor Q3, a sixth transistor Q4, a seventh transistor Q5, an eighth transistor Q6, a ninth transistor Q7, a tenth transistor Q8, an eleventh transistor Q9, and a twelfth transistor Q10.

[0035] The first terminal of the first transistor MN1, the second terminal of the first transistor MN1, and the first terminal of the second transistor MN2 are used to connect a first current. The third terminal of the first transistor MN1, the second terminal of the third transistor Q1, and the first terminal of the tenth transistor Q8 are interconnected. The first terminal of the third transistor Q1, the first terminal of the fourth transistor Q2, and the third terminal of the tenth transistor Q8 are interconnected. The second terminal of the tenth transistor Q8 is used to connect a power supply. The third terminal of the third transistor Q1, the third terminal of the sixth transistor Q4, the first terminal of the ninth transistor Q7, and the second terminal of the ninth transistor Q7 are interconnected. The second terminal of the fourth transistor Q2 and the first terminal of the twelfth transistor Q10 are used to connect a second current. The third terminal of the fourth transistor Q2, the third terminal of the fifth transistor Q3, and the second terminal of the eighth transistor Q6 are interconnected. The second terminal of the twelfth transistor Q10 is connected to a power source, the second terminal of the seventh transistor Q5 is connected to a power source, the third terminal of the twelfth transistor Q10 and the first terminal of the seventh transistor Q5 are connected to a first bias current, the third terminal of the seventh transistor Q5 and the first terminal of the eighth transistor Q6 are connected to a second bias current, the second terminal of the fifth transistor Q3 and the first terminal of the eleventh transistor Q9 are connected to a third current, the first terminal of the fifth transistor Q3, the first terminal of the sixth transistor Q4 and the third terminal of the eleventh transistor Q9 are interconnected, the second terminal of the eleventh transistor Q9 is connected to a power source, the second terminal of the second transistor MN2 is used to output a fourth current, the third terminal of the second transistor MN2 is connected to the second terminal of the sixth transistor Q4, and the third terminal of the ninth transistor Q7 and the third terminal of the eighth transistor Q6 are grounded.

[0036] In this circuit, the transistors can be MOSFETs or bipolar junction transistors (BJTs). The multiplier circuit utilizes the logarithmic voltage-current relationship of the BJTs; multiplication and division of current are achieved by adding or subtracting the BJT voltage. In this embodiment, the connection relationship of the above structure ensures that the multiplication and division relationship of the multiplier circuit is unaffected by parameters such as the transistor's amplification factor, and it has low dependence on process technology and temperature. The input current is introduced into negative feedback through the seventh transistor Q5, the eighth transistor Q6, and the twelfth transistor Q10, improving circuit stability and ensuring voltage matching of the fourth transistor Q2, reducing the Earliest effect. This invention requires no additional operational amplifier, has a simple circuit structure, a negative feedback structure, high circuit stability, and the matching between transistors gives the circuit structure advantages such as high linearity, low error, and low distortion, and it is free from the Earliest effect.

[0037] Furthermore, referring to Figure 1In one embodiment, the first transistor MN1, the second transistor MN2, the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 are NMOS transistors, and the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, and the seventh transistor Q5 are NPN transistors. The first terminal of the first transistor MN1, the second transistor MN2, the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 is the gate of the NMOS transistor. The second terminal of transistor Q10 is the drain of an NMOS transistor. The third terminals of the first transistor MN1, the second transistor MN2, the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 are the sources of NMOS transistors. The first terminals of the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, and the seventh transistor Q5 are the bases of NPN transistors. The second terminals of the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, and the seventh transistor Q5 are the collectors of NPN transistors. The third terminals of the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, and the seventh transistor Q5 are the emitters of NPN transistors.

[0038] It should be noted that when the transistor is an NMOS transistor, it includes the source, drain, gate, and substrate, and the substrate of the NMOS transistor is connected to the source by default.

[0039] right Figure 1 The circuit shown is analyzed as follows:

[0040] Because the transistor operates in the amplification region, its collector current I C With base-emitter voltage drop V BE The relationship is:

[0041] ;

[0042] Among them I S V is a constant used to describe the transfer characteristics of a transistor in the forward amplification region, typically ranging from approximately 10exp(-14) A to 10exp(-16) A; CE V is the collector-emitter voltage drop of the transistor; AThis is the Urlie voltage, typically ranging from approximately 10V to 100V; V T This is the thermal voltage, approximately 26mV at room temperature; in this embodiment, the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, and the sixth transistor Q4 can be perfectly matched transistors of the same size, and their I... S and V A The same applies. For the third transistor Q1, its collector current is I1, and the base-emitter voltage drop V of the third transistor Q1 can be obtained. BE1 The relationship is:

[0043] ;

[0044] Where V CE1 The collector-emitter voltage drop is the third transistor Q1; similarly, the collector current I2 of the fourth transistor Q2, the collector current I3 of the fifth transistor Q3, and the collector current I4 of the sixth transistor Q4 are as follows:

[0045] ;

[0046] ;

[0047] ;

[0048] Where V CE2 V is the collector-emitter voltage drop of the fourth transistor Q2. CE3 V is the collector-emitter voltage drop of the fifth transistor Q3. CE4 V is the collector-emitter voltage drop of the sixth transistor Q4. BE2 V is the base-emitter voltage drop of the fourth transistor Q2. BE3 V is the base-emitter voltage drop of the fifth transistor Q3. BE4 This represents the base-emitter voltage drop of the sixth transistor Q4. The difference between the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, and the sixth transistor Q4 is related to the Erlie voltage V. A Compared to being two orders of magnitude smaller, then V A The effect is negligible, meaning the difference in collector-emitter voltage drop between different transistors is within several hundred mV, and the Earlier voltage V A The impact is relatively small. The third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, and the sixth transistor Q4 are identical transistors, so their base-emitter voltage drops can be approximated as equal. The other transistors have matching dimensions, so their gate-source voltages can be approximated as equal. I1 is the same as the first current I1, I2 is the same as the second current I2, I3 is the same as the third current I3, and I4 is the same as the fourth current I4. Furthermore, according to... Figure 1 From the circuit connection relationship, we can obtain:

[0049] ;

[0050] ;

[0051] ;

[0052] ;

[0053] Among them, V GS4 V is the gate-source voltage difference of the tenth transistor Q8. GS5 V is the gate-source voltage difference of the eighth transistor Q6. BE5 V is the base-emitter voltage drop of the seventh transistor Q5. GS6 V is the gate-source voltage difference of the twelfth transistor. GS7 V is the gate-source voltage difference of the ninth transistor. GS3 V is the gate-source voltage difference of the eleventh transistor. GS1 V is the gate-source voltage difference of the first transistor MN1. GS2 The gate-source voltage difference of the second transistor MN2, and V BE and V GS It represents a voltage value result, not the voltage value of a specific transistor; that is, Dividing I1 / I2 and I4 / I3 respectively, we get:

[0054] ;

[0055] ;

[0056] Depend on Figure 1 The connection relationship, the V of the third transistor Q1 BE1 Subtract V of the fourth transistor Q2 BE2 V equal to the sixth transistor Q4 BE4 Subtract V of the fifth transistor Q3 BE3 ,Right now:

[0057] ;

[0058] Therefore, we can conclude that:

[0059] ;

[0060] And it can be further obtained that:

[0061] ;

[0062] From the above analysis, it can be seen that this invention ensures that the output current I4 has a fixed multiplication and division relationship with the input currents I1, I2, and I3, where I1, I2, I3, and I4 correspond to the first current I1, the second current I2, the third current I3, and the fourth current I4, respectively. If the input current I2 is set as a fixed current, the product of the output current I4 and I1 and I3 is a predetermined ratio; if the input current I1 (or I3) is set as a fixed current, the output current I4 is the product of I3 (or I1) divided by I2, resulting in a predetermined ratio with minimal linearity error. Furthermore, the above multiplication and division relationships are unaffected by the transistor's amplification factor or V. BE V T V A and I S The influence of parameters such as these is reduced, decreasing dependence on process and temperature. The input current I2 forms a negative feedback structure through the seventh transistor Q5 and the eighth transistor Q6, which not only improves circuit stability but also reduces the V of the fourth transistor Q2. CE2 Matching reduces the Earliest effect of the fourth transistor Q2. The first bias current Ibia1 and the second bias current Ibia2 are used to provide the quiescent operating point.

[0063] It should be noted that in this example, the second current I2 passes through the negative feedback structure formed by the seventh transistor Q5, the eighth transistor Q6, and the twelfth transistor Q10. When the gate voltage of the twelfth transistor Q10 increases, the base voltage of the seventh transistor Q5 increases, and further, the gate voltage of the eighth transistor Q6 increases, causing the emitter voltage of the fourth transistor Q2 to decrease, which in turn causes the gate voltage of the eighth transistor Q6 to decrease, thus forming negative feedback. This not only improves the stability of the circuit but also reduces the voltage of the fourth transistor Q2. CE2 Matching reduces the Earliest effect of the fourth transistor Q2. Furthermore, current multiplier circuits assume a high transistor gain, thus neglecting base current. This invention can... Figure 1 The amplification structure in the transistor provides the base current, thereby eliminating the bias caused by the base current and eliminating the requirement for the transistor's amplification factor. The specific amplification structure is... Figure 1 The transistors Q1 and Q6 form the third transistor and Q3 and Q5 respectively. The base current of the third transistor Q1 is provided by the tenth transistor Q8. Therefore, I1 is exactly equal to the collector current of the third transistor Q1, thus avoiding the shunting of the base of the third transistor Q1.

[0064] In summary, this invention does not require an additional operational amplifier, has a simple circuit structure, a negative feedback structure, high circuit stability, and good matching between transistors, which gives the structure advantages such as extremely high linearity, small error and low distortion, and no Ehrlich effect.

[0065] Furthermore, referring to Figure 2In one embodiment, the first transistor MN1 and the second transistor MN2 are NMOS transistors, and the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 are NPN transistors. The first terminal of the first transistor MN1 and the second transistor MN2 is the gate of the NMOS transistor, the second terminal of the first transistor MN1 and the second transistor MN2 is the drain of the NMOS transistor, and the third terminal of the first transistor MN1 and the second transistor MN2 is the source of the NMOS transistor. The third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, and the twelfth transistor Q10 are NPN transistors. The first terminals of the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 are the bases of the NPN transistors; the second terminals of the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 are the collectors of the NPN transistors; and the third terminals of the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, the eighth transistor Q6, the ninth transistor Q7, the tenth transistor Q8, the eleventh transistor Q9, and the twelfth transistor Q10 are the emitters of the NPN transistors.

[0066] In this embodiment, the circuit structure is implemented in a different way, according to... Figure 2 From the circuit connection relationship, we can obtain:

[0067] ;

[0068] ;

[0069] ;

[0070] ;

[0071] Among them, V BE8 V is the base-emitter voltage drop of the seventh transistor Q5. BE6 V is the base-emitter voltage drop of the tenth transistor Q8. BE5 V is the base-emitter voltage drop of the eleventh transistor Q9. BE10 V is the base-emitter voltage drop of the ninth transistor Q7.BE7 V is the base-emitter voltage drop of the twelfth transistor Q10. BE2 V is the base-emitter voltage drop of the fourth transistor Q2. BE3 V is the base-emitter voltage drop of the fifth transistor Q3. BE9 V is the base-emitter voltage drop of the eighth transistor Q6. GS1 V is the gate-source voltage difference of the first transistor MN1. GS2 The gate-source voltage difference of the second transistor MN2, and V BE It represents a voltage value result, not the voltage value of a specific transistor, that is, ;

[0072] Its subsequent implementation principle and Figure 1 The same applies here, so it will not be repeated. It should be noted that in this example, the second current I2 passes through the negative feedback structure formed by the seventh transistor Q5, the eighth transistor Q6, and the twelfth transistor Q10. When the base voltage of the twelfth transistor Q10 increases, the base voltage of the seventh transistor Q5 increases, and further, the base voltage of the eighth transistor Q6 increases, causing the emitter voltage of the fourth transistor Q2 to decrease, resulting in a decrease in the base voltage of the eighth transistor Q6, thus forming negative feedback. The first bias current Ibia1 and the second bias current Ibia2 are used to provide the quiescent operating point.

[0073] In one embodiment, the NPN transistors are of the same size.

[0074] It is understandable that, in the two circuit structure implementations mentioned above, using NPN transistors of the same size can achieve relatively better matching.

[0075] The present invention also proposes a multiplier circuit.

[0076] Reference Figure 3 In one embodiment, the multiplier circuit includes a first transistor MN1, a second transistor MN2, a third transistor Q1, a fourth transistor Q2, a fifth transistor Q3, a sixth transistor Q4, a seventh transistor Q5, an eighth transistor Q6, and a ninth transistor Q7.

[0077] The first terminal of the first transistor MN1, the second terminal of the first transistor MN1, and the first terminal of the second transistor MN2 are used to connect to the first current I1. The third terminal of the first transistor MN1, the first terminal of the third transistor Q1, the second terminal of the third transistor Q1, and the first terminal of the fourth transistor Q2 are interconnected. The third terminal of the third transistor Q1, the third terminal of the sixth transistor Q4, the first terminal of the ninth transistor Q7, and the second terminal of the ninth transistor Q7 are interconnected. The second terminal of the fourth transistor Q2 and the first terminal of the seventh transistor Q5 are used to connect to the second current I2. The third terminal of the fourth transistor Q2 and the first terminal of the fifth transistor Q5 are interconnected. The third terminal of transistor Q3 is interconnected with the second terminal of the eighth transistor Q6. The second terminal of the seventh transistor Q5 is connected to the power supply VCC. The third terminal of the seventh transistor Q5 and the first terminal of the eighth transistor Q6 are connected to the third bias current Ibia3. The first terminal of the fifth transistor Q3, the second terminal of the fifth transistor Q3, and the first terminal of the sixth transistor Q4 are connected to the third current I3. The second terminal of the second transistor MN2 is used to output the fourth current I4. The third terminal of the second transistor MN2 is connected to the second terminal of the sixth transistor Q4. The third terminal of the ninth transistor Q7 and the third terminal of the eighth transistor Q6 are grounded.

[0078] In this circuit, the transistors can be MOSFETs or bipolar junction transistors (BJTs). The multiplier circuit utilizes the logarithmic voltage-current relationship of the BJTs; multiplication and division of current are achieved by adding or subtracting the BJT voltage. In this embodiment, the connection relationship of the above structure ensures that the multiplication and division relationship of the multiplier circuit is unaffected by parameters such as the transistor's amplification factor, and it has low dependence on process technology and temperature. The input current is introduced into negative feedback through the seventh transistor Q5 and the eighth transistor Q6, improving circuit stability and ensuring voltage matching of the fourth transistor Q2, reducing the Earliest effect. Furthermore, the third bias current Ibia3 is used to provide the quiescent operating point. This invention requires no additional operational amplifier, has a simple circuit structure, a negative feedback structure, high circuit stability, and the matching between transistors gives the circuit structure advantages such as high linearity, low error, and low distortion, and it is free from the Earliest effect.

[0079] Further, in one embodiment, the first transistor MN1 and the second transistor MN2 are NMOS transistors, and the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, the eighth transistor Q6, and the ninth transistor Q7 are NPN transistors. The first terminal of the first transistor MN1 and the second transistor MN2 is the gate of the NMOS transistor, the second terminal of the first transistor MN1 and the second transistor MN2 is the drain of the NMOS transistor, and the third terminal of the first transistor MN1 and the second transistor MN2 is the source of the NMOS transistor. The third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, the eighth transistor Q6, and the ninth transistor Q7 are NPN transistors. The first terminals of transistors Q2, Q3, Q4, Q5, Q6, and Q7 are the bases of the NPN transistors; the second terminals of transistors Q1, Q2, Q3, Q4, Q5, Q6, and Q7 are the collectors of the NPN transistors; and the third terminals of transistors Q1, Q2, Q3, Q4, Q5, Q6, and Q7 are the emitters of the NPN transistors.

[0080] according to Figure 3 From the circuit connection relationship, we can obtain:

[0081] ;

[0082] ;

[0083] ;

[0084] ;

[0085] Among them, V BE1 V is the base-emitter voltage drop of the third transistor Q1. BE2 V is the base-emitter voltage drop of the fourth transistor Q2. BE3 V is the base-emitter voltage drop of the fifth transistor Q3. BE5 V is the base-emitter voltage drop of the seventh transistor Q5. BE6 V is the base-emitter voltage drop of the eighth transistor Q6. BE7 V is the base-emitter voltage drop of the ninth transistor Q7. GS1 V is the gate-source voltage difference of the first transistor MN1. GS2 The gate-source voltage difference of the second transistor MN2, and V BEIt represents a voltage value result, not the voltage value of a specific transistor, that is, ;

[0086] Its subsequent implementation principle and Figure 1 The same applies, so I won't repeat it here.

[0087] From the above analysis, it can be seen that this invention ensures that the output current I4 has a fixed multiplication and division relationship with the input currents I1, I2, and I3, where I1, I2, I3, and I4 correspond to the first current I1, the second current I2, the third current I3, and the fourth current I4, respectively. If the input current I2 is set as a fixed current, the product of the output current I4 and I1 and I3 is a predetermined ratio; if the input current I1 (or I3) is set as a fixed current, the output current I4 is the product of I3 (or I1) divided by I2, resulting in a predetermined ratio with minimal linearity error. Furthermore, the above multiplication and division relationships are unaffected by the transistor's amplification factor or V. BE V T V A and I S The influence of parameters such as these is reduced, decreasing dependence on process and temperature. The input current I2 forms a negative feedback structure through the seventh transistor Q5 and the eighth transistor Q6, which not only improves circuit stability but also reduces the V of the fourth transistor Q2. CE2 Matching reduces the Earliest effect of the fourth transistor Q2.

[0088] In one embodiment, the amplification factor of the third transistor Q1, the fourth transistor Q2, the fifth transistor Q3, the sixth transistor Q4, the seventh transistor Q5, the eighth transistor Q6, and the ninth transistor Q7 is greater than a preset amplification factor.

[0089] In this embodiment, when the third transistor Q1, fourth transistor Q2, fifth transistor Q3, sixth transistor Q4, seventh transistor Q5, eighth transistor Q6, and ninth transistor Q7 are transistors, their amplification factor needs to meet a preset factor, thus eliminating the need for amplification structures for the transistors. Specifically, the amplification factor for the third transistor Q1, fourth transistor Q2, fifth transistor Q3, sixth transistor Q4, seventh transistor Q5, eighth transistor Q6, and ninth transistor Q7 can be selected based on the actual circuit design and user requirements.

[0090] The present invention also proposes an electronic device.

[0091] In one embodiment, the electronic device includes a plurality of multiplier circuits as described above, wherein the plurality of multiplier circuits are cascaded.

[0092] In this embodiment, it is understood that since the above-described multiplier circuit is used in the electronic device of the present invention, the embodiments of the electronic device of the present invention include all the technical solutions of all embodiments of the above-described multiplier circuit, and the achieved technical effects are exactly the same, which will not be repeated here. In order to achieve more current multiplication and division, multiple multiplier circuits can be cascaded, for example, two multiplier circuits are connected, and the fourth current output by one multiplier circuit can be used as the input current of another multiplier circuit.

[0093] In one embodiment, the electronic device further includes:

[0094] Multiple current mirrors are provided, with their input terminals connected one-to-one to the output terminals of the multiple multiplier circuits. The current mirrors are used to convert the current signal output by the multiplier circuits into a current source for output.

[0095] In this embodiment, the current signal output by the multiplier circuit refers to the current magnitude of I4 in the above embodiment. I4 is a current drain, which can be converted into a current source output to the subsequent circuit for processing through the current mirror.

[0096] In one embodiment, the electronic device further includes:

[0097] The processor has its input terminal connected to the output terminals of the plurality of current mirrors. The processor is used to receive current sources output by the plurality of current mirrors and to perform conversion processing on the current sources.

[0098] In this embodiment, the processor can be a digital signal processor (DSP), a programmable logic device (PLD), a microprocessor, an MCU, or other electronic components. The processor can convert the current sources output from multiple current mirrors, i.e., analog signals, into digital signals for subsequent data processing.

[0099] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A multiplier circuit, characterized in that, Including the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor; The first terminal, the second terminal, and the first terminal of the first transistor are used to connect to a first current. The third terminal, the second terminal, and the first terminal of the tenth transistor are interconnected. The first terminal, the first terminal, and the third terminal of the tenth transistor are interconnected. The second terminal of the tenth transistor is used to connect to a power supply. The third terminal, the third terminal, the first terminal, and the second terminal of the ninth transistor are interconnected. The second terminal of the fourth transistor and the first terminal of the twelfth transistor are used to connect to a second current. The third terminal, the third terminal, and the second terminal of the eighth transistor are interconnected. The second terminal of the transistor is used to connect to the power supply. The second terminal of the seventh transistor is used to connect to the power supply. The third terminal of the twelfth transistor and the first terminal of the seventh transistor are used to connect to the first bias current. The third terminal of the seventh transistor and the first terminal of the eighth transistor are used to connect to the second bias current. The second terminal of the fifth transistor and the first terminal of the eleventh transistor are used to connect to the third current. The first terminal of the fifth transistor, the first terminal of the sixth transistor, and the third terminal of the eleventh transistor are interconnected. The second terminal of the eleventh transistor is used to connect to the power supply. The second terminal of the second transistor is used to output the fourth current. The third terminal of the second transistor is connected to the second terminal of the sixth transistor. The third terminal of the ninth transistor and the third terminal of the eighth transistor are grounded.

2. The multiplier circuit as described in claim 1, characterized in that, The first, second, eighth, ninth, tenth, eleventh, and twelfth transistors are NMOS transistors, and the third, fourth, fifth, sixth, and seventh transistors are NPN transistors. The first terminal of each of the first, second, eighth, ninth, tenth, eleventh, and twelfth transistors is the gate of the NMOS transistor, and the second terminal of each of the first, second, eighth, ninth, tenth, eleventh, and twelfth transistors is... The drain of the NMOS transistor, the third terminal of the first transistor, the second transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are the source of the NMOS transistor, the first terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the base of the NPN transistor, the second terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the collector of the NPN transistor, and the third terminal of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are the emitter of the NPN transistor.

3. The multiplier circuit as described in claim 1, characterized in that, The first and second transistors are NMOS transistors, and the third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are NPN transistors. The first terminal of the first and second transistors is the gate of the NMOS transistor, the second terminal of the first and second transistors is the drain of the NMOS transistor, and the third terminal of the first and second transistors is the source of the NMOS transistor. The first terminals of the third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are the bases of the NPN transistors; the second terminals of the third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are the collectors of the NPN transistors; and the third terminals of the third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth transistors are the emitters of the NPN transistors.

4. The multiplier circuit as described in any one of claims 2 or 3, characterized in that, The NPN transistors are all the same size.

5. A multiplier circuit, characterized in that, Including the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor; The first terminal, the second terminal, and the first terminal of the second transistor are used to connect to a first current. The third terminal, the first terminal, the second terminal, and the first terminal of the fourth transistor are interconnected. The third terminal, the third terminal, the first terminal, and the second terminal of the ninth transistor are interconnected. The second terminal of the fourth transistor and the first terminal of the seventh transistor are used to connect to a second current. The third terminal, the third terminal, and the second terminal of the eighth transistor are interconnected. The second terminal of the seventh transistor is used to connect to a power supply. The third terminal of the seventh transistor and the first terminal of the eighth transistor are used to connect to a third bias current. The first terminal, the second terminal, and the first terminal of the fifth transistor are used to connect to the third current. The second terminal of the second transistor is used to output a fourth current. The third terminal of the second transistor is connected to the second terminal of the sixth transistor. The third terminal of the ninth transistor and the third terminal of the eighth transistor are grounded.

6. The multiplier circuit as described in claim 5, characterized in that, The first and second transistors are NMOS transistors, and the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors are NPN transistors. The first terminal of the first and second transistors is the gate of the NMOS transistor, the second terminal of the first and second transistors is the drain of the NMOS transistor, and the third terminal of the first and second transistors is the source of the NMOS transistor. The first terminal of the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors is the base of the NPN transistor, the second terminal of the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors is the collector of the NPN transistor, and the third terminal of the third, fourth, fifth, sixth, seventh, eighth, and ninth transistors is the emitter of the NPN transistor.

7. The multiplier circuit as described in claim 6, characterized in that, The amplification factor of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is greater than the preset amplification factor.

8. An electronic device, characterized in that, It includes multiple multiplier circuits as described in any one of claims 1-4 or multiple multiplier circuits as described in any one of claims 5-7, wherein the multiple multiplier circuits are cascaded.

9. The electronic device as claimed in claim 8, characterized in that, The electronic device also includes: Multiple current mirrors are provided, with their input terminals connected one-to-one to the output terminals of the multiple multiplier circuits. The current mirrors are used to convert the current signal output by the multiplier circuits into a current source and then output it.

10. The electronic device as claimed in claim 9, characterized in that, The electronic device also includes: The processor has its input terminal connected to the output terminals of the plurality of current mirrors. The processor is used to receive current sources output by the plurality of current mirrors and to perform conversion processing on the current sources.

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