Processor instruction reading control method and system and electronic equipment

Abstract

The invention provides a processor instruction reading control method and system and electronic equipment, and relates to the field of chip instruction control, in the scheme, an instruction buffer area is additionally arranged between an instruction fetch queue unit and a decoding unit, and a subsequently hit instruction fetch block is allowed to be read in advance and cached to a specific position in the instruction buffer area. Before the instruction data are output to the decoding unit, the instruction data are rearranged according to the sequence of the instruction fetching blocks, it is ensured that the instruction data are still executed in sequence from external logic, global blocking caused by failure of the instruction fetching process in the prior art is solved, and the performance advantage of a wide-emission CPU can be fully exerted.

Description

Technical Field

[0001] The present invention relates to the field of chip instruction control, and in particular to a processor instruction reading control method, system and electronic equipment. Background Art

[0002] The front-end of a modern CPU typically includes branch prediction, an instruction fetch queue, an iCache, an iTLB structure, and other pipelines. Processor instructions must flow into the decode unit strictly in program order (in-order). This limitation means that if the front-end instruction fetch stage encounters an iCache or iTLB failure, subsequent instructions must still wait in line until they are backfilled before continuing through the pipeline. Therefore, in a wide-issue CPU, if the front-end is blocked, the back-end will not receive sufficient instruction flow, significantly affecting throughput. Summary of the Invention

[0003] In view of this, the present invention aims to provide a processor instruction read control method, system, and electronic device. This solution provides an additional instruction buffer between the instruction fetch queue unit and the decode unit, allowing subsequent hit instruction fetch blocks to be read first and cached to a specific location in the instruction buffer. Before output to the decode unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that execution remains in order from the perspective of external logic. This solves the global blocking caused by instruction fetch failure in the prior art and fully utilizes the performance advantages of wide-issue CPUs.

[0004] In a first aspect, an embodiment of the present invention provides a method for controlling processor instruction reading, the method comprising: An instruction buffer corresponding to the instruction fetch unit is constructed based on an instruction fetch queue unit and a decoding unit included in the instruction fetch unit of the processor; wherein the instruction buffer is arranged between the instruction fetch queue unit and the decoding unit; When detecting that a response to an instruction fetch request instruction corresponding to the instruction fetch queue unit fails, obtaining a first size parameter of a current instruction fetch block corresponding to the instruction fetch request instruction and response failure information, controlling the instruction buffer to reserve a first address interval corresponding to the first size parameter, and controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to an execution order of the instruction fetch request instruction; When it is detected that the response failure information disappears, the instruction fetch queue unit is controlled to make an instruction fetch request for the current instruction fetch block and obtain backfill data corresponding to the current instruction fetch block; The instruction buffer is controlled to write the backfill data into a reserved first address interval, and the first processor instruction corresponding to the backfill data is controlled to be sent to the decoding unit using the first address interval.

[0005] Optionally, obtaining a first size parameter of a current instruction fetch block corresponding to an instruction fetch request instruction and response failure information, and controlling an instruction buffer to reserve a first address interval corresponding to the first size parameter, includes: Determine the instruction cache tag array corresponding to the instruction fetch request instruction, and obtain a first size parameter corresponding to the current instruction fetch block; Determine response failure information corresponding to the current instruction fetch block using the instruction cache tag array, and set the first flag bit corresponding to the first address interval to the first flag; wherein the response failure information at least includes: no data in the instruction cache and instruction conversion detection buffer address translation failure; According to the address length value corresponding to the first size parameter, the control instruction buffer reserves a first address interval consistent with the address length value according to a preset starting point.

[0006] Optionally, controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions includes: After calling back the first size parameter to the instruction fetch queue unit, determining the execution order of the instruction fetch request instructions based on the number information of the instruction fetch blocks corresponding to the instruction fetch request instructions; Obtain the current number corresponding to the current instruction fetch block, and determine the adjacent numbers corresponding to the current number based on the execution order; The subsequent instruction fetch block corresponding to the current instruction fetch block is determined by using the adjacent numbers, and the instruction fetch queue unit is controlled to make an instruction fetch request to the subsequent instruction fetch block.

[0007] Optionally, when it is detected that the response failure information disappears, controlling the instruction fetch queue unit to make an instruction fetch request for the current instruction fetch block and obtaining backfill data corresponding to the current instruction fetch block includes: When it is detected that the response failure information disappears, a wake-up instruction corresponding to the current instruction fetch block is generated; The instruction fetch queue unit is controlled to control the current instruction fetch block to perform an instruction fetch request based on the wake-up instruction, obtain backfill data corresponding to the current instruction fetch block, and obtain a first size parameter through the instruction fetch queue unit.

[0008] Optionally, controlling the instruction buffer to write the backfill data into a reserved first address interval, and using the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, includes: After the control instruction buffer writes the backfill data into the reserved first address interval according to the first size parameter, the first flag bit corresponding to the first address interval is set to the second flag; When it is detected that the first flag bit is the second flag, the instruction buffer is controlled to send the first processor instruction corresponding to the backfill data to the decoding unit.

[0009] Optionally, after controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions, the method further includes: Determine a subsequent instruction fetch request instruction corresponding to a subsequent instruction fetch block; When detecting that a subsequent instruction fetch request instruction corresponding to the instruction fetch queue unit is successfully responded to, obtaining a second size parameter and instruction data corresponding to the subsequent instruction fetch block, and controlling the instruction buffer to determine a second address interval corresponding to the second size parameter; wherein the second address interval is adjacent to the first address interval; The instruction buffer is controlled to write instruction data into the second address interval, and a flag bit corresponding to the second address interval is set to a second flag.

[0010] Optionally, obtaining a second size parameter and instruction data corresponding to a subsequent instruction fetch block includes: Determine the instruction cache data array corresponding to the subsequent instruction fetch request instruction, and obtain the second size parameter corresponding to the subsequent instruction fetch block; The instruction cache data array is used to obtain the instruction data corresponding to the subsequent instruction fetch block.

[0011] Optionally, after the step of controlling the instruction buffer to write the backfill data into the reserved first address interval and using the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, the method further includes: Obtaining a second flag bit corresponding to the second address interval; When it is detected that the second flag bit is the second flag, the instruction buffer is controlled to send the second processor instruction corresponding to the instruction data to the decoding unit.

[0012] In a second aspect, the present invention provides a processor instruction reading control system, the system comprising: An instruction buffer construction module is used to construct an instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit included in the instruction fetch unit of the processor; wherein the instruction buffer is set between the instruction fetch queue unit and the decoding unit; an instruction fetch request exception handling module for, upon detecting that a response to an instruction fetch request instruction corresponding to an instruction fetch request unit fails, obtaining a first size parameter of a current instruction fetch block corresponding to the instruction fetch request instruction and response failure information, controlling the instruction buffer to reserve a first address interval corresponding to the first size parameter, and controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block in the execution order of the instruction fetch request instruction; The normal instruction fetch request processing module is used to control the instruction fetch queue unit to make an instruction fetch request for the current instruction fetch block and obtain the backfill data corresponding to the current instruction fetch block when detecting that the response failure information disappears; The processor instruction control module is used to control the instruction buffer to write the backfill data into the reserved first address interval, and use the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0013] In a third aspect, an embodiment of the present invention further provides an electronic device comprising a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the steps of the processor instruction reading control method provided in the first aspect.

[0014] In a fourth aspect, an embodiment of the present invention further provides a storage medium storing computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the steps of the processor instruction reading control method provided in the first aspect.

[0015] A processor instruction reading control method, system and electronic device provided by an embodiment of the present invention, in the process of using an instruction fetch unit to control the reading of processor instructions, first, an instruction buffer corresponding to the instruction fetch unit is constructed based on the instruction fetch queue unit and the decoding unit contained in the processor's instruction fetch unit; wherein the instruction buffer is arranged between the instruction fetch queue unit and the decoding unit; when it is detected that the instruction fetch request instruction corresponding to the instruction fetch queue unit fails to respond, the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information are obtained, the instruction buffer is controlled to reserve a first address interval corresponding to the first size parameter, and the instruction fetch queue unit is controlled to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction; when it is detected that the response failure information disappears, the instruction fetch queue unit is controlled to perform an instruction fetch request on the current instruction fetch block, and then the backfill data corresponding to the current instruction fetch block is obtained; finally, the instruction buffer is controlled to write the backfill data into the reserved first address interval, and the first processor instruction corresponding to the backfill data is controlled to be sent to the decoding unit using the first address interval. This solution places an additional instruction buffer between the instruction fetch queue unit and the decode unit, allowing subsequent hit instruction fetch blocks to be read first and cached in a specific location within the instruction buffer. Before output to the decode unit, instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that execution remains in order from the external logic perspective. This solves the global blocking caused by instruction fetch failures in existing technologies and fully leverages the performance advantages of wide-issue CPUs.

[0016] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A flowchart of a processor instruction reading control method provided by an embodiment of the present invention; Figure 2 A flowchart of obtaining a first size parameter of a current instruction fetch block corresponding to an instruction fetch request instruction and response failure information in step S102 of a processor instruction fetch control method provided by an embodiment of the present invention, and controlling an instruction buffer to reserve a first address interval corresponding to the first size parameter; Figure 3 A flowchart of controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of a current instruction fetch block according to the execution order of instruction fetch request instructions in step S102 of a processor instruction reading control method provided by an embodiment of the present invention; Figure 4 A flowchart of step S103 in a processor instruction reading control method provided by an embodiment of the present invention; Figure 5 A flowchart of step S104 in a processor instruction reading control method provided by an embodiment of the present invention; Figure 6 A flowchart after controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions in step S102 of a processor instruction reading control method provided by an embodiment of the present invention; Figure 7 A flowchart of obtaining a second size parameter and instruction data corresponding to a subsequent instruction fetch block in step S602 of a processor instruction fetch control method provided by an embodiment of the present invention; Figure 8 This is a flowchart after step S104 in a processor instruction reading control method provided by an embodiment of the present invention; Figure 9 A flowchart of another processor instruction reading control method provided by an embodiment of the present invention; Figure 10 A schematic diagram of the structure of a processor instruction reading control system provided by an embodiment of the present invention; Figure 11 A schematic structural diagram of an electronic device provided by an embodiment of the present invention.

[0020] icon: 1010 - instruction buffer construction module; 1020 - instruction fetch request exception processing module; 1030 - instruction fetch request normal processing module; 1040 - processor instruction control module; 101 - processor; 102 - memory; 103 - bus; 104 - communication interface. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0022] The front-end of a modern CPU typically includes branch prediction, an instruction fetch queue, an iCache, an iTLB structure, and pipelines. Processor instructions must flow into the decode unit strictly in program order (in-order). This limitation means that if the front-end instruction fetch stage encounters an iCache or iTLB processing failure, subsequent hit instructions must still wait in line until they are backfilled before continuing the pipeline. Therefore, in a wide-issue CPU, if the front-end is blocked, the back-end will not receive sufficient instruction flow, significantly affecting throughput. Specifically, when an iCache Miss or iTLB Miss occurs, subsequent hit instruction blocks cannot be fetched, resulting in wasted front-end bandwidth. In addition, when the front-end is blocked by a Miss and cannot meet the instruction supply to the back-end, the performance of the wide-issue pipeline is limited.

[0023] Based on this, the present invention provides a processor instruction read control method, system, and electronic device. This solution provides an additional instruction buffer between the instruction fetch queue unit and the decode unit, allowing subsequent hit instruction fetch blocks to be read first and cached to a specific location in the instruction buffer. Before output to the decode unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that execution remains in order from the perspective of external logic. This solves the global blocking caused by instruction fetch failure in the existing technology and fully utilizes the performance advantages of wide-issue CPUs.

[0024] To facilitate understanding of this embodiment, a processor instruction reading control method disclosed in an embodiment of the present invention is first described in detail. Figure 1As shown, the method includes: Step S101: constructing an instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit included in the instruction fetch unit of the processor; wherein the instruction buffer is set between the instruction fetch queue unit and the decoding unit.

[0025] The core of this step is to build an intermediate data buffer structure for the processor's instruction fetch unit. Specifically, based on the two key components of the instruction fetch unit: the instruction fetch queue unit (responsible for initiating instruction read requests and temporarily storing pending instruction fetch tasks) and the decode unit (responsible for parsing and preprocessing read instructions), a dedicated "instruction buffer" is set up between the two.

[0026] The role of this buffer is similar to a "data transfer station". Its design purpose is to resolve the contradiction between temporary blockages that may occur during the instruction fetch process (such as storage system response delay) and the continuous working requirements of the decoding unit, ensuring that the instruction fetch and decoding processes can be carried out more flexibly and in coordination, avoiding the "interruption" of the decoding unit directly caused by instruction fetch interruptions.

[0027] Step S102: When it is detected that the instruction fetch request instruction corresponding to the instruction fetch queue unit fails to respond, the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information are obtained, the instruction buffer is controlled to reserve the first address interval corresponding to the first size parameter, and the instruction fetch queue unit is controlled to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction.

[0028] When the instruction fetch queue unit initiates an instruction fetch request to the cache or memory, if it detects that the request response fails (possibly due to a cache miss, bus conflict, etc., resulting in a temporary inability to obtain instruction data), the following operations are performed: Obtain key information: Extract the first size parameter of the "current instruction fetch block" corresponding to the currently failed instruction fetch request (i.e., characteristic parameters such as the instruction length contained in the instruction fetch block and the occupied storage size), and record the specific information of the response failure (such as the failure reason, failure time, etc.).

[0029] Reserve buffer space: The control instruction buffer reserves a first address range that matches the first size parameter for the current instruction fetch block, ensuring that when the data of the instruction fetch block is available later, there is dedicated space to store it without disrupting the instruction sequence.

[0030] Continuing subsequent instruction fetches: To prevent the entire instruction fetch process from being blocked due to a failed instruction fetch block, the instruction fetch queue unit is controlled to execute instruction fetch requests in the original order, skipping the failed instruction fetch block and continuing to initiate instruction fetch requests for subsequent instruction fetch blocks. This design maximizes instruction fetch bandwidth and reduces latency.

[0031] Step S103: When it is detected that the response failure information disappears, the instruction fetch queue unit is controlled to make an instruction fetch request for the current instruction fetch block, and then obtain backfill data corresponding to the current instruction fetch block.

[0032] When the failure message that caused the instruction fetch failure disappears (i.e., the cache has returned to normal and can respond to the original instruction fetch request), reprocessing of the current instruction fetch block is immediately triggered. The instruction fetch queue unit is controlled to re-initiate an instruction fetch request for the current instruction fetch block. Upon success, the complete instruction data corresponding to the instruction fetch block is retrieved and used as backfill data. Backfilling here emphasizes that this data supplements the previously reserved space and is a key operation after process recovery.

[0033] Step S104: controlling the instruction buffer to write the backfill data into the reserved first address interval, and using the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0034] After obtaining the backfill data for the current instruction fetch block, the final instruction flow is completed. The backfill data is first written to the reserved first address range. The instruction buffer is controlled to accurately write the backfill data into the first address range reserved in step S102, ensuring that the data storage location is consistent with the previous plan and maintaining the continuity of the instruction sequence. The backfill data is then sent to the decoding unit in sequence. Using the address information (such as the starting address and ending address) of the first address range, the control buffer sends the first processor instructions corresponding to the backfill data (i.e., the instructions contained in the current instruction fetch block) to the decoding unit in the correct order. These instructions are then connected to the previously fetched instructions from the subsequent instruction fetch block, ensuring that the decoding unit can process the instructions in the original instruction stream order.

[0035] In summary, this method effectively improves the processor's ability to cope with temporary failures during instruction fetching by introducing mechanisms such as instruction buffer, dynamic reserved space, priority processing of subsequent instruction fetches, and backfilling after failure, thereby reducing the impact of instruction fetch interrupts on the overall instruction execution efficiency.

[0036] Optionally, a first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and response failure information are obtained, and the instruction buffer is controlled to reserve a first address interval corresponding to the first size parameter, such as Figure 2 Shown, including: Step S201: Determine the instruction cache tag array corresponding to the instruction fetch request instruction, and obtain a first size parameter corresponding to the current instruction fetch block.

[0037] When the instruction fetch request response of the instruction fetch queue unit fails, it is necessary to clarify the basic information and positioning basis of the current instruction fetch block. The specific operations include: Locating the instruction cache tag array (iCache Tag Array): The instruction cache tag array is a key metadata structure stored in the instruction cache, which records the index tag, address mapping relationship, validity flag and other information of each instruction fetch block in the cache. According to the target address (such as virtual address or physical address) of the current instruction fetch request instruction, the instruction cache tag array entry corresponding to the request can be located, which serves as the basis for subsequent judgment of the instruction fetch status.

[0038] The first size parameter is determined by parsing the attributes of the current instruction fetch block (which can be obtained from the instruction cache tag array or the instruction fetch request instruction itself). This parameter includes the number of instructions in the instruction fetch block, the length of the memory occupied, and the address span (the difference between the starting and ending addresses). This information directly determines the amount of buffer space that needs to be reserved.

[0039] Step S202: Determine the response failure information corresponding to the current instruction fetch block using the instruction cache tag array, and set the first flag bit corresponding to the first address interval to the first flag; wherein the response failure information at least includes: no data in the instruction cache and instruction conversion detection buffer address translation failure.

[0040] After obtaining the instruction cache tag array and the first size parameter, it is necessary to determine the specific reason for the instruction fetch failure and mark the status of the reserved space. Specifically, when parsing the response failure information, the status flags in the instruction cache tag array (such as "valid bit" and "hit flag") can be used to determine the specific reason for the current instruction fetch block response failure. According to the description, the failure information includes at least two core scenarios: No data in instruction cache (iCache Miss): This means that the instruction cache misses (there is no matching valid entry in the tag array). The data of the current instruction fetch block is not cached and needs to be read from a lower level of storage (such as main memory), resulting in temporary unresponsiveness.

[0041] Translation Lookaside Buffer (TLB) address translation failure (iTLBMiss): When an instruction fetch request uses a virtual address, the TLB must translate the virtual address into a physical address. If there is no corresponding translation entry in the TLB (a TLB miss) or a permission error occurs during the translation process, the address will be invalid and the instruction fetch request will fail.

[0042] At this point, a status flag (the first flag) is set in the instruction buffer for the first address range to be reserved, and its value is set to "not ready." This flag indicates to the system that this range has been allocated to the failed instruction fetch block, but the data has not yet been filled and is temporarily unavailable to the decode unit to avoid malfunctions in subsequent processes.

[0043] Step S203: According to the address length value corresponding to the first size parameter, the instruction buffer is controlled to reserve a first address interval consistent with the address length value according to a preset starting point.

[0044] After parameter acquisition and status marking are complete, accurate storage space must be reserved in the instruction buffer for the current instruction fetch block. First, the address length value is determined. Based on the first size parameter obtained in step S201, the corresponding "address length value" (i.e., the length of the contiguous address space required to fully store the current instruction fetch block, typically in bytes) is extracted.

[0045] Then the interval is allocated according to the preset starting point. There is a preset space allocation rule inside the instruction buffer (such as continuous allocation from low address to high address, or a fixed starting offset divided by block). According to this rule, a "preset starting point" (that is, the starting address of the reserved interval) is determined, and then starting from this starting point, a continuous space that completely matches the "address length value" is divided as the first address interval.

[0046] This operation ensures that the subsequent "backfill data" of the current instruction fetch block has exclusive, size-adapted storage space, and the location of this interval complies with the buffer management specifications, providing a basis for the orderliness of subsequent data writing and instruction sending.

[0047] Optionally, the instruction fetch queue unit is controlled to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction, such as Figure 3 Shown, including: Step S301: after calling back the first size parameter to the instruction fetch queue unit, the execution order of the instruction fetch request instructions is determined based on the numbering information of the instruction fetch blocks corresponding to the instruction fetch request instructions.

[0048] After the instruction fetch request response for the current instruction fetch block fails, the instruction fetch queue unit performs two key operations to ensure that it can correctly process subsequent instruction fetch blocks: First size parameter callback: Feedback (callback) the first size parameter of the current instruction fetch block (e.g., instruction block length, address span, etc.) obtained in step S201 to the instruction fetch queue unit. This operation allows the instruction fetch queue unit to identify the "space occupancy characteristics" of the currently failed instruction fetch block, providing a basis for calculating the starting address of subsequent instruction fetch blocks and avoiding address conflicts.

[0049] Determining execution order based on numbering information: Each instruction fetch block corresponding to an instruction fetch request contains unique "numbering information" (which can be understood as the logical sequence of the instruction fetch block, such as the consecutive numbers Block 0, Block 1, Block 2, etc. assigned according to the program execution flow, or the index number associated with the physical address). By parsing this numbering information, the original execution order of all instruction fetch blocks is determined. This is usually consistent with the order of the program instruction flow (that is, arranged in the increasing direction of the program counter PC), ensuring that subsequent instruction fetches do not disrupt the logical execution sequence of instructions.

[0050] Step S302: Obtain the current number corresponding to the current instruction fetch block, and determine the adjacent number corresponding to the current number based on the execution order.

[0051] After determining the instruction fetch execution order, we need to locate the specific identifier of the "subsequent instruction fetch block." First, we obtain the current number. This number is extracted from the metadata of the currently failed instruction fetch block (for example, if the current instruction fetch block is the fifth instruction fetch block, its number is "5"). This number serves as the basis for locating the subsequent instruction fetch block.

[0052] Next, the adjacent number is determined. Based on the execution order determined in step S301 (e.g., ascending order), the next number immediately adjacent to the current number in the sequence is found, i.e., the "adjacent number." For example, if the current number is "5" and the execution order is ascending, the adjacent number is "6." This adjacent number directly points to the "next instruction fetch block to the current instruction fetch block" and serves as the target identifier for subsequent instruction fetches.

[0053] Step S303: using the adjacent numbers to determine the subsequent instruction fetch block corresponding to the current instruction fetch block, and controlling the instruction fetch queue unit to make an instruction fetch request to the subsequent instruction fetch block.

[0054] After locking onto the target using the adjacent number, the actual control of subsequent instruction fetches is completed. First, the subsequent instruction fetch block is determined. Specifically, using the adjacent number as an index, the corresponding instruction fetch block is located in the instruction fetch task list of the instruction fetch queue unit. This is known as the "subsequent instruction fetch block of the current instruction fetch block." This instruction fetch block is the instruction block that should immediately follow the current instruction fetch block according to the original execution order. Its address range is calculated based on the size parameters of the preceding instruction fetch block (such as the first size parameter of the current instruction fetch block). For example, the end address of the current instruction fetch block + 1 is the starting address of the subsequent instruction fetch block. The instruction fetch queue unit is then controlled to initiate a request, skipping the currently failed instruction fetch block and initiating an instruction fetch request for the located subsequent instruction fetch block according to the original execution order. This operation ensures that the instruction fetch process will not be stalled by the failure of a single instruction fetch block, but will continue to move forward, maximizing instruction fetch bandwidth, reducing latency, and reserving data for the decoding and execution of subsequent instructions.

[0055] Optionally, when it is detected that the response failure information disappears, the instruction fetch queue unit is controlled to fetch the instruction request for the current instruction fetch block, and then the backfill data corresponding to the current instruction fetch block is obtained in step S103, such as Figure 4 Shown, including: Step S401: When it is detected that the response failure information disappears, a wake-up instruction corresponding to the current instruction fetch block is generated.

[0056] When real-time monitoring mechanisms (such as storage system status feedback and TLB (Translation Check Buffer) update notifications) detect that the response failure message that previously caused the instruction fetch failure has disappeared (for example, the instruction cache has completed loading the data for the current instruction fetch block, and the TLB has successfully completed address translation and cached a valid mapping), it means that the instruction fetch conditions for the current instruction fetch block have returned to normal. At this point, the system performs a key operation: generating a "wake-up instruction" corresponding to the current instruction fetch block.

[0057] This wake-up instruction is a control signal specifically for the blocked current instruction fetch block. Its core functions include: Mark the instruction fetch condition of the instruction fetch block as satisfied, switching from the "waiting state" to the "executable state"; Carry key identification information of the current instruction fetch block (such as number, original instruction fetch address, etc.) to ensure that the instruction fetch queue unit can accurately locate the corresponding instruction fetch task; The instruction fetch queue unit is triggered to give priority to processing the re-request of the instruction fetch block to avoid it being blocked for a long time by subsequent instruction fetch tasks.

[0058] Step S402: controlling the instruction fetch queue unit to control the current instruction fetch block to make an instruction fetch request based on the wake-up instruction, obtaining backfill data corresponding to the current instruction fetch block, and obtaining a first size parameter through the instruction fetch queue unit.

[0059] After the wake-up instruction is generated, the instruction fetch queue unit is further controlled to complete the specific instruction fetch operation and data acquisition: Responding to the wake-up instruction and initiating an instruction fetch request: Upon receiving the wake-up instruction, the instruction fetch queue unit locates the original instruction fetch request record for that instruction fetch block from the task queue based on the identifier carried in the instruction (such as the number and address of the current instruction fetch block). It then re-initiates the instruction fetch request to the storage system (such as the instruction cache that has cached data or the target storage unit after address translation). Because the obstacles that could prevent a response have been eliminated, the request is usually successfully responded to.

[0060] Obtaining backfill data: After a successful instruction fetch request, the complete instruction data corresponding to the current instruction fetch block is received, also known as the "backfill data." This data contains the critical instruction information that was previously missing due to the instruction fetch failure and needs to be subsequently written to the first reserved address range in the instruction buffer to complete the instruction stream.

[0061] Re-obtaining the first size parameter: While retrieving the backfill data, the instruction queue unit re-extracts the first size parameter of the current instruction fetch block (consistent with the parameters obtained in step S201, such as the instruction block length and address span). This operation aims to verify whether the actual size of the backfill data matches the reserved first address interval, ensuring data integrity (avoiding data truncation or redundancy due to storage system anomalies). It also provides an accurate size basis for subsequent instruction buffer write operations, ensuring that the data is accurately filled into the reserved interval without occupying space in other instruction fetch blocks.

[0062] Optionally, the control instruction buffer writes the backfill data into the reserved first address interval, and uses the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit in step S104, such as Figure 5 Shown, including: Step S501: After controlling the instruction buffer to write backfill data into a reserved first address interval according to a first size parameter, a first flag bit corresponding to the first address interval is set to a second flag.

[0063] When the instruction fetch queue unit successfully obtains the backfill data of the current instruction fetch block, it stores the data accurately in the instruction buffer and updates the space status to indicate that the data is ready.

[0064] Writing backfill data by size: The instruction buffer writes the backfill data completely into the first address range reserved in step S203 based on the first size parameter (e.g., address length, number of instructions, etc.) obtained in step S201. During the writing process, two checks are performed: 1. Verify that the actual length of the backfill data matches the first size parameter (to avoid data truncation or redundancy); and 2. Verify that the write address is strictly within the first address range (to prevent out-of-bounds writes that interfere with the space of other instruction fetch blocks).

[0065] This operation ensures that the backfill data is correctly stored in the buffer and the location is exactly the same as the previous plan.

[0066] Setting the first flag bit to the second flag bit: After data writing is complete, the first flag bit corresponding to the first address range (originally "not ready" (i.e., the first flag bit) is updated to the second flag bit (usually "ready," indicating ready). This flag bit state change is a key signal, serving several functions: declaring that the data in the address range is complete and available for subsequent calls; distinguishing between "ready" and "not ready" instruction fetch block data in the buffer to prevent the decode unit from reading invalid or incomplete instructions; and serving as a trigger for instruction transmission, providing a basis for determining the execution of step S502.

[0067] Step S502: When it is detected that the first flag bit is the second flag, the instruction buffer is controlled to send the first processor instruction corresponding to the backfill data to the decoding unit.

[0068] When the first flag is updated to the second flag, the change is detected through the status monitoring mechanism (such as real-time polling or interrupt triggering), and the instruction sending process is started: Flag bit status detection: The control logic of the instruction buffer continuously monitors the flag bit status of each address range. When the first flag bit of the first address range is detected to be the second flag ("ready"), it confirms that the backfill data in this range has met the sending conditions.

[0069] The control instruction is sent to the decoding unit: according to the address information of the first address range (such as the starting address and the ending address), the "first processor instruction" corresponding to the backfill data in the range is read from the buffer (that is, the complete instruction sequence contained in the current instruction fetch block) and sent to the decoding unit in the original order of the instructions (consistent with the program execution flow).

[0070] The "sequential sending" here is particularly important: since the subsequent instruction fetch blocks of the current instruction fetch block may have been fetched in advance and temporarily stored in the buffer (the operation result of step S303), it will ensure that the instructions of the current instruction fetch block are sent before the instructions of the subsequent instruction fetch blocks to maintain the logical continuity of the entire instruction stream and avoid execution errors caused by the decoding unit processing out-of-order instructions.

[0071] Optionally, after the instruction fetch queue unit is controlled to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction, as shown in FIG. Figure 6 Said method further comprises: Step S601: Determine a subsequent instruction fetch request instruction corresponding to a subsequent instruction fetch block.

[0072] In step S303, the instruction fetch queue unit has initiated instruction fetch requests for subsequent instruction fetch blocks of the current instruction fetch block in the execution order. The core of this step is to clarify the correspondence between these subsequent instruction fetch blocks and the specific request instructions: Using the instruction fetch task list recorded in the instruction fetch queue unit and the subsequent instruction fetch block numbering information (such as the adjacent and subsequent incrementing numbers determined in step S302), the "subsequent instruction fetch request instructions" corresponding to each subsequent instruction fetch block are located. These request instructions contain key information such as the target address (virtual or physical address) and fetch range of the instruction fetch block, which serves as the basis for subsequent data acquisition and storage.

[0073] The purpose of this operation is to establish an accurate mapping of "instruction fetch block-request instruction" to ensure that subsequent data processing can correspond to the original instruction fetch requirements and avoid address or range confusion.

[0074] Step S602: When it is detected that the subsequent instruction fetch request instruction corresponding to the instruction fetch queue unit is responded successfully, a second size parameter and instruction data corresponding to the subsequent instruction fetch block are obtained, and the instruction buffer is controlled to determine a second address interval corresponding to the second size parameter; wherein the second address interval is adjacent to the first address interval.

[0075] When the instruction fetch queue unit detects that the subsequent instruction fetch request instruction response is successful (that is, the storage unit normally returns the instruction data of the instruction fetch block), it performs the following key operations: Obtain the second size parameter and instruction data: Extract the "second size parameter" of the subsequent instruction fetch block, whose content is similar to the first size parameter, including the number of instructions in the instruction fetch block, storage byte length, address span, etc., which is used to determine the required buffer space size; receive the complete "instruction data" of the subsequent instruction fetch block returned by the storage unit, that is, all processor instructions contained in the instruction fetch block.

[0076] Determine a second address interval adjacent to the first address interval: the instruction buffer allocates storage space for subsequent instruction fetch blocks according to the following rules: take the first address interval reserved in step S203 (the reserved space of the current instruction fetch block) as the basis, and use its end address as the starting address of the second address interval (i.e., the "adjacent" rule); calculate the address length value based on the second size parameter, and divide a continuous space matching the length value from the starting address as the "second address interval".

[0077] The core purpose of this "adjacent allocation" mechanism is to arrange data in the instruction buffer strictly according to the execution order of the instruction fetch blocks, ensuring that the instruction data of the current instruction fetch block (to be backfilled in the future) and the subsequent instruction fetch blocks are physically continuous in storage, laying the foundation for subsequent sequential sending to the decoding unit.

[0078] Step S603: Control the instruction buffer to write the instruction data into the second address interval, and set the flag bit corresponding to the second address interval to the second flag.

[0079] After the second address range is determined, the instruction data of the subsequent instruction fetch block is stored in the buffer and the status is marked: Writing instruction data to the second address range: The instruction buffer is controlled to write the instruction data for the subsequent instruction fetch block obtained in step S602 completely into the determined second address range. During the writing process, two checks are performed: 1. The actual length of the instruction data matches the second size parameter (to ensure data integrity, without missing or redundant data); and 2. The write address is strictly confined to the second address range (to prevent cross-boundary writes that interfere with the space of other instruction fetch blocks).

[0080] Set the flag bit in the second address range to the second flag: After data writing is complete, set the flag bit corresponding to the second address range (which may initially be unallocated or to be filled) to the second flag (usually "ready"). This flag indicates that the instruction data for the subsequent instruction fetch block is ready in the buffer and can be used by the decoding unit at any time. This flag is compared with the flag bit in the first address range (if the first address range is still "not ready," it means that the current instruction fetch block has not been backfilled), providing a basis for the subsequent "in-order send" logic (which must wait for the previous instruction fetch block to be ready before sending the entire block).

[0081] Optionally, obtain the second size parameter and instruction data corresponding to the subsequent instruction fetch block, such as Figure 7 Shown, including: Step S701: Determine the instruction cache data array corresponding to the subsequent instruction fetch request instruction, and obtain a second size parameter corresponding to the subsequent instruction fetch block.

[0082] When the subsequent instruction fetch request instruction responds successfully (ie, the storage unit has returned the data of the instruction fetch block normally), it is first necessary to locate the core structure storing the data from the instruction cache and extract the key size information.

[0083] Locating the instruction cache data array (iCache Data Array): The instruction cache typically consists of two components: a tag array and a data array. The tag array stores metadata such as address mapping and validity (as mentioned in step S201), while the instruction cache data array physically stores the instruction binary data. Based on the target address of the subsequent instruction fetch request (the translated physical address or cache index), the instruction cache locates the entry in the instruction cache corresponding to the subsequent instruction fetch block, specifically the location where the instruction data for that instruction fetch block is stored.

[0084] Extracting the second size parameter: Each entry in the instruction cache data array contains not only instruction data but also metadata describing the properties of the data block (such as stored in the header of the data array or in an associated control field). The system parses this metadata to obtain the "second size parameter" for the subsequent instruction fetch block. This parameter specifically includes: the total byte length of the instruction fetch block (such as 32 bytes or 64 bytes, depending on the cache block size or instruction length); the number of valid instructions contained (for example, if each instruction is 4 bytes, a 32-byte instruction fetch block may contain 8 instructions); and address boundary information (such as the offset of the starting address and the ending address to ensure data integrity).

[0085] The acquisition of the second size parameter is the key basis for subsequently allocating the second address range in the instruction buffer (which must strictly match the range size) and is also the basis for verifying data integrity.

[0086] Step S702: using the instruction cache data array to obtain instruction data corresponding to the subsequent instruction fetch block.

[0087] After locating the corresponding instruction cache data array entry and obtaining the second size parameter, actual instruction data of the subsequent instruction fetch block can be extracted therefrom.

[0088] Reading the valid data area: In the instruction cache data array, each entry corresponds to a contiguous section of storage space, only part of which stores valid instruction data (the rest may be padding or invalid data). Based on the "valid length" and "address boundary information" in the second size parameter, the contents of the valid area are accurately read from the data array entry. This is the "instruction data" for the subsequent instruction fetch block. This data is a binary instruction sequence (such as machine code) that the processor can directly execute.

[0089] Data integrity check: A check is performed during the reading process to ensure that the length of the instruction data read is exactly the same as the second size parameter (for example, if the second size parameter is 32 bytes, the read data must be exactly 32 bytes), avoiding partial data loss due to cache data corruption or address calculation errors.

[0090] Format adaptation processing: If the instruction data stored in the instruction cache data array contains additional auxiliary information such as additional check bits and flag bits, these non-instruction contents will be stripped off after reading, retaining only the pure instruction sequence, ensuring that the data passed to the instruction buffer is "clean data" that can be directly parsed by the decoding unit.

[0091] Optionally, after step S104 of controlling the instruction buffer to write the backfill data into the reserved first address interval and using the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, as shown in FIG. Figure 8 As shown, the method further includes: Step S801: Obtain a second flag bit corresponding to a second address interval.

[0092] In step S104, the backfill data of the current instruction fetch block has been written into the first address interval and marked as "ready" (second flag), and its corresponding first processor instruction has been successfully sent to the decoding unit. At this time, it is necessary to pay attention to the status of subsequent instruction fetch blocks in the instruction buffer. The specific operations are: Obtain the current state of the "second flag bit" corresponding to the "second address interval." The second address interval is the storage space adjacent to the first address interval allocated in step S602 for the subsequent instruction fetch block. The second flag bit is a status indicator used to identify whether the instruction data within that interval is ready (as described in step S603, when the instruction data for the subsequent instruction fetch block is written, the flag bit is set to the second flag "ready").

[0093] There are usually two ways to obtain the flag bit status: Active polling: The control logic of the instruction buffer periodically scans the flag bits of each address interval and updates the status information in real time; Interrupt trigger: When the second flag switches from "not ready" to "ready", the status notification is automatically triggered without continuous scanning.

[0094] The core purpose of this operation is to determine whether the instruction data of the subsequent instruction fetch block has met the sending conditions, providing a decision basis for the next step of instruction sending.

[0095] Step S802: When it is detected that the second flag bit is the second flag, the instruction buffer is controlled to send the second processor instruction corresponding to the instruction data to the decoding unit.

[0096] When the state of the second flag bit is confirmed to be the second flag ("ready") in step S801, it means that the instruction data of the subsequent instruction fetch block is completely ready in the buffer, and the instruction of the current instruction fetch block has been sent to the decoding unit in advance (the result of step S104). At this time, the sending process of the subsequent instructions can be triggered: The control instruction buffer reads the instruction data of the subsequent instruction fetch block stored in the second address interval according to the address information (start address, end address) of the second address interval, namely the "second processor instruction", and sends it to the decoding unit in the original execution order of the instruction (consistent with the growth direction of the program counter PC).

[0097] This process must strictly follow the "sequential transmission" principle: since the second processor instruction is logically the subsequent instruction of the first processor instruction (corresponding to the next section of the program execution flow), it must be sent after the first processor instruction is sent, so as to ensure that the instruction stream received by the decoding unit is completely consistent with the execution order of the program design, and avoid instruction dependency errors caused by out-of-order processing (such as confusion in the execution logic of jump instructions and data-dependent instructions).

[0098] In addition, a final check is performed before sending: confirming that the instruction data length of the second address range matches the second size parameter, and that the sending order does not span other unready instruction fetch blocks (if there are more subsequent instruction fetch blocks), ensuring the continuity and integrity of the entire instruction stream.

[0099] like Figure 9A flowchart of another processor fetch control method describes an additional instruction ordering buffer (IFU) within the CPU front-end, located after the instruction fetch pipeline and before the decoder. The in-order path (orange arrow) accesses the instruction cache's tag array, iCache TagArray, to determine if the current instruction fetch block matches (tag matching is a sequential operation, ensuring "check first, process later").

[0100] The out-of-order path (pink arrow) indicates access to the instruction cache's data array, iCacheData Array. If the tag matches (i.e., a hit), the instruction data can be read directly in parallel / out of order (improving efficiency and avoiding unnecessary waiting).

[0101] The Instruction Ordering Buffer is used to receive the "hit data" and "tag matching results (hit / miss signals)" from the instruction cache iCache. It is responsible for temporarily storing instructions, sorting the order, and finally outputting them to the Decode Unit in the program logic order.

[0102] When an iCache Miss or iTLB Miss (failed to respond to an instruction fetch request) occurs for a fetch block in the instruction fetch queue, the fetch block size is read and space is reserved for it in the instruction ordering buffer, pending backfill. The next or subsequent fetch blocks, if a hit, can continue accessing the pipeline normally, reading the instruction data and writing it to the instruction ordering buffer according to the previously reserved space.

[0103] The instruction buffer is arranged as follows: The Instruction Ordering Buffer reserves space based on the order and size of the fetch blocks. For example, if fetch block 0 is 16 bytes, the reserved range is addresses 0-15. If fetch block 0 misses but fetch block 1 hits, the instruction data for block 1 can be placed first at the 16-byte position. After fetch block 0 is backfilled, the data is written to positions 0-15. When outputting to the decoder, the instruction buffer outputs fetch block 0 first, followed by fetch block 1, to ensure that the decoder appears in-order.

[0104] The workflow is as follows: The Fetch Queue initiates instruction fetch requests sequentially (Fetch Block 0, Fetch Block 1, ...). If Fetch Block 0 misses, the instruction is written to the Instruction Ordering Buffer, and Fetch Block 0 is set to the not ready state. The location in the Instruction Ordering Buffer is also stored in the Fetch Queue. If Block 1 is a hit, the data is immediately written to Block 1 and set to the ready state.

[0105] When Fetch Block 0 is backfilled, a wake-up signal is generated, and Fetch Block 0 will re-enter the instruction fetch pipeline. After obtaining the backfilled data, it will write the instruction to the correct location based on the location information of the Instruction Ordering Buffer stored in the Fetch Queue.

[0106] At the output of the instruction buffer, only when the Fetch Block 0 area is ready can the FetchBlock 0 instruction be sent to the Decode unit; then the Block 1 instruction is sent to maintain the logical order; The same process is applied to subsequent Fetch Blocks. Even if a Miss occurs, the entire front-end will not be blocked. Subsequent hit instruction blocks can be fetched first and temporarily stored in the corresponding buffer location.

[0107] As can be seen from the processor instruction read control method described in the above embodiment, this method sets up an additional instruction buffer between the instruction fetch queue unit and the decode unit, allowing subsequent hit instruction fetch blocks to be read first and cached in a specific location in the instruction buffer. Before being output to the decode unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that execution remains in order from the external logic perspective. This solves the global blocking caused by instruction fetch failure in the prior art and fully utilizes the performance advantages of wide-issue CPUs.

[0108] Corresponding to the above processor instruction reading control method embodiment, the embodiment of the present invention also provides a processor instruction reading control system, such as Figure 10 As shown, the system includes: An instruction buffer construction module 1010 is configured to construct an instruction buffer corresponding to the instruction fetch unit based on an instruction fetch queue unit and a decoding unit included in the instruction fetch unit of the processor; wherein the instruction buffer is provided between the instruction fetch queue unit and the decoding unit; an instruction fetch request exception handling module 1020 for, upon detecting that a response to an instruction fetch request instruction corresponding to the instruction fetch request unit fails, obtaining a first size parameter of a current instruction fetch block corresponding to the instruction fetch request instruction and response failure information, controlling the instruction buffer to reserve a first address interval corresponding to the first size parameter, and controlling the instruction fetch queue unit to execute instruction fetch requests for subsequent instruction fetch blocks of the current instruction fetch block in the execution order of the instruction fetch request instruction; The instruction fetch request normal processing module 1030 is configured to control the instruction fetch queue unit to make an instruction fetch request for the current instruction fetch block and obtain backfill data corresponding to the current instruction fetch block when detecting that the response failure information disappears; The processor instruction control module 1040 is used to control the instruction buffer to write the backfill data into the reserved first address interval, and use the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0109] The processor's instruction read control system, described above, incorporates an additional instruction buffer between the instruction fetch queue unit and the decode unit, allowing subsequent hit instruction fetch blocks to be read first and cached in a specific location within the instruction buffer. Before being output to the decode unit, instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that execution remains in order from the perspective of external logic. This resolves the global blocking caused by instruction fetch failures in existing technologies and fully leverages the performance advantages of wide-issue CPUs.

[0110] The processor instruction reading control system provided in the embodiment of the present invention has the same implementation principle and technical effects as the aforementioned processor instruction reading control method embodiment. For the sake of brief description, for matters not mentioned in the system embodiment, reference can be made to the corresponding content in the aforementioned processor instruction reading control method embodiment.

[0111] This embodiment also provides an electronic device. The structural diagram of the electronic device is as follows: Figure 11 As shown, the device includes a processor 101 and a memory 102; wherein the memory 102 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the steps of the above-mentioned processor instruction reading control method.

[0112] Figure 11 The electronic device shown further includes a bus 103 and a communication interface 104 , and the processor 101 , the communication interface 104 and the memory 102 are connected via the bus 103 .

[0113] The memory 102 may include a high-speed random access memory (RAM) and may also include a non-volatile memory, such as at least one disk storage. The bus 103 may be an ISA bus, a PCI bus, or an EISA bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 11 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0114] The communication interface 104 is used to connect to at least one user terminal and other network units through a network interface, and send the encapsulated IPv4 message or IPv4 message to the user terminal through the network interface.

[0115] The processor 101 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 101 or by instructions in the form of software. The above-mentioned processor 101 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present disclosure can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in memory 102, and processor 101 reads information in memory 102 and, in conjunction with its hardware, completes the steps of the method of the aforementioned embodiment.

[0116] An embodiment of the present invention further provides a storage medium storing a computer program. When the computer program is executed by a processor, the steps of the processor instruction reading control method in the above embodiment are executed.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, equipment and methods can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0118] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0119] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0120] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes instructions for enabling a computer device (which can be a personal computer, electronic device, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0121] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A processor instruction reading control method, characterized in that: The method comprises: An instruction buffer corresponding to the instruction fetch unit is constructed based on an instruction fetch queue unit and a decoding unit included in the instruction fetch unit of the processor; wherein the instruction buffer is arranged between the instruction fetch queue unit and the decoding unit; When detecting that a response to an instruction fetch request instruction corresponding to the instruction fetch queue unit fails, obtaining a first size parameter of a current instruction fetch block corresponding to the instruction fetch request instruction and response failure information, controlling the instruction buffer to reserve a first address interval corresponding to the first size parameter, and controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction; When it is detected that the response failure information disappears, controlling the instruction fetch queue unit to perform an instruction fetch request on the current instruction fetch block, and obtaining backfill data corresponding to the current instruction fetch block; The instruction buffer is controlled to write the backfill data into the reserved first address interval, and the first address interval is used to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

2. The processor instruction reading control method according to claim 1, characterized in that: Obtaining a first size parameter of a current instruction fetch block corresponding to the instruction fetch request instruction and response failure information, and controlling the instruction buffer to reserve a first address interval corresponding to the first size parameter, including: Determine an instruction cache tag array corresponding to the instruction fetch request instruction, and obtain the first size parameter corresponding to the current instruction fetch block; Determining the response failure information corresponding to the current instruction fetch block using the instruction cache tag array, and setting the first flag bit corresponding to the first address interval to a first flag; wherein the response failure information at least includes: no data in the instruction cache and address translation failure in the instruction conversion detection buffer; According to the address length value corresponding to the first size parameter, the instruction buffer is controlled to reserve the first address interval consistent with the address length value according to a preset starting point.

3. The processor instruction reading control method according to claim 2, characterized in that: Controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction, comprising: After calling back the first size parameter to the instruction fetch queue unit, determining the execution order of the instruction fetch request instructions based on the number information of the instruction fetch blocks corresponding to the instruction fetch request instructions; Obtaining a current number corresponding to the current instruction fetch block, and determining an adjacent number corresponding to the current number based on the execution order; The subsequent instruction fetch block corresponding to the current instruction fetch block is determined by using the adjacent number, and the instruction fetch queue unit is controlled to make an instruction fetch request to the subsequent instruction fetch block.

4. The processor instruction reading control method according to claim 3, characterized in that: When it is detected that the response failure information disappears, controlling the instruction fetch queue unit to perform an instruction fetch request on the current instruction fetch block, and obtaining backfill data corresponding to the current instruction fetch block, including: When it is detected that the response failure information disappears, generating a wake-up instruction corresponding to the current instruction fetch block; The instruction fetch queue unit is controlled to control the current instruction fetch block to make an instruction fetch request based on the wake-up instruction, obtain backfill data corresponding to the current instruction fetch block, and obtain the first size parameter through the instruction fetch queue unit.

5. The processor instruction reading control method according to claim 4, characterized in that: Controlling the instruction buffer to write the backfill data into the reserved first address interval, and using the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, including: After controlling the instruction buffer to write the backfill data into the reserved first address interval according to the first size parameter, setting a first flag bit corresponding to the first address interval to a second flag; When it is detected that the first flag bit is the second flag, the instruction buffer is controlled to send the first processor instruction corresponding to the backfill data to the decoding unit.

6. The processor instruction reading control method according to claim 5, characterized in that: After controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction, the method further includes: Determining a subsequent instruction fetch request instruction corresponding to the subsequent instruction fetch block; When detecting that the subsequent instruction fetch request instruction corresponding to the instruction fetch queue unit is successfully responded to, obtaining a second size parameter and instruction data corresponding to the subsequent instruction fetch block, and controlling the instruction buffer to determine a second address interval corresponding to the second size parameter; wherein the second address interval is adjacent to the first address interval; The instruction buffer is controlled to write the instruction data into the second address interval, and a flag bit corresponding to the second address interval is set to the second flag.

7. The processor instruction reading control method according to claim 6, characterized in that: Obtaining a second size parameter and instruction data corresponding to the subsequent instruction fetch block includes: Determine an instruction cache data array corresponding to the subsequent instruction fetch request instruction, and obtain the second size parameter corresponding to the subsequent instruction fetch block; The instruction cache data array is used to obtain the instruction data corresponding to the subsequent instruction fetch block.

8. The processor instruction reading control method according to claim 6, characterized in that: After the steps of controlling the instruction buffer to write the backfill data into the reserved first address interval, and using the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, the method further includes: Obtaining a second flag bit corresponding to the second address interval; When it is detected that the second flag bit is the second flag, the instruction buffer is controlled to send the second processor instruction corresponding to the instruction data to the decoding unit.

9. A processor instruction reading control system, characterized in that: The system comprises: An instruction buffer construction module is used to construct an instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit included in the instruction fetch unit of the processor; wherein the instruction buffer is arranged between the instruction fetch queue unit and the decoding unit; an instruction fetch request exception handling module for, when detecting that a response to an instruction fetch request instruction corresponding to the instruction fetch request instruction of the instruction fetch queue unit fails, obtaining a first size parameter of a current instruction fetch block corresponding to the instruction fetch request instruction and response failure information, controlling the instruction buffer to reserve a first address interval corresponding to the first size parameter, and controlling the instruction fetch queue unit to perform instruction fetch requests on subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction; an instruction fetch request normal processing module, configured to, when detecting that the response failure information disappears, control the instruction fetch queue unit to make an instruction fetch request for the current instruction fetch block and obtain backfill data corresponding to the current instruction fetch block; A processor instruction control module is used to control the instruction buffer to write the backfill data into the reserved first address interval, and use the first address interval to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

10. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the steps of the processor instruction reading control method according to any one of claims 1 to 8.

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