Resistive random access memory architecture
By setting transistors and level converters outside the RRAM, the problems of large area occupied by the gate tube and high voltage power consumption are solved, and a high-density and low-cost memory design is achieved.
Patent Information
- Application Number
- CN202510242418.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-03
- Publication Date
- 2025-10-03
AI Technical Summary
In existing RRAM memories, the gate transistors occupy a large area and require high voltage, resulting in large chip area and high power consumption.
The bit line transistor and source line transistor are set outside the resistive memory to replace the internal selection tube, and the initial control voltage signal is converted by using a level converter to reduce the voltage input to reduce the unit area and power consumption.
The storage density is improved, the unit area and storage cost are reduced, the power consumption is reduced, and the stability of the memory is guaranteed.
Smart Images
Figure CN120748463A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of circuit technology, and more particularly to a resistive random access memory architecture. Background Art
[0002] RRAM (Resistive Random Access Memory) is a non-volatile memory that uses changes in a material's resistance to store data. Unlike traditional memory technologies, RRAM stores data based on the resistance state of the storage medium, rather than on charge or magnetic fields. It encodes data by changing resistance, meaning data is stored in high and low resistance states.
[0003] In RRAM design, the selector is a switch used to control access, but the area of this selector is large, which causes each memory cell to occupy more chip area. In addition, during the RRAM programming process, a higher voltage is usually required, which may lead to higher power consumption. Summary of the Invention
[0004] In view of the above problems, the present disclosure provides a resistive switching memory architecture.
[0005] According to a first aspect of the present disclosure, a resistive random access memory architecture is provided, comprising: a resistive random access memory; an address decoder for converting a received address signal into a control signal; a word line driver module electrically connected to the address decoder, the word line driver module comprising a word line and a word line driver, the word line driver for receiving a control signal and adjusting a level state of the word line based on the control signal to control the resistive random access memory to be in an on state; a control module comprising: a level converter for level-converting an initial control voltage signal off-chip to obtain a target control voltage signal, the level of the target control voltage signal being higher than the level of the initial control voltage signal; a bit line transistor for controlling a bit line of the control module to be in an on state according to the target control voltage signal; and a source line transistor for controlling a source line of the control module to be in an on state according to the target control voltage signal. The source line in the on state and the bit line in the on state are both electrically connected to the resistive random access memory, and the source line and bit line level signals are transmitted to the resistive random access memory. The resistive random access memory in the on state adjusts its resistance state in response to the source line and bit line level signals and executes a data write instruction based on the resistance state.
[0006] According to an embodiment of the present disclosure, the bit line transistor includes a first N-type field effect transistor and a first P-type field effect transistor; the drain of the first N-type field effect transistor is electrically connected to the bit line, the source of the first N-type field effect transistor is electrically connected to the bit line, and the gate of the first N-type field effect transistor is electrically connected to the level converter; the drain of the first P-type field effect transistor is electrically connected to the bit line, the source of the first P-type field effect transistor is electrically connected to the bit line, and the gate of the first P-type field effect transistor is electrically connected to the level converter.
[0007] According to an embodiment of the present disclosure, the target control voltage signal includes a first target control voltage signal and a second target control voltage signal; the gate of the first N-type field effect transistor is in a first level state in response to the first target control voltage signal to control the first N-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the drain of the first N-type field effect transistor to the source of the first N-type field effect transistor; the gate of the first P-type field effect transistor is in a second level state in response to the second target control voltage signal to control the first P-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the source of the first P-type field effect transistor to the drain of the first P-type field effect transistor, wherein the level corresponding to the first level state is higher than the level of the second level state.
[0008] According to an embodiment of the present disclosure, the source line transistor includes a second N-type field effect transistor and a second P-type field effect transistor; the drain of the second N-type field effect transistor is electrically connected to the source line, the drain of the second N-type field effect transistor is electrically connected to the source line, and the gate of the second N-type field effect transistor is electrically connected to the level converter; the drain of the second P-type field effect transistor is electrically connected to the source line, the drain of the second P-type field effect transistor is electrically connected to the source line, and the gate of the second P-type field effect transistor is electrically connected to the level converter.
[0009] According to an embodiment of the present disclosure, the target control voltage signal also includes a third target control voltage signal and a fourth target control voltage signal; the gate of the second N-type field effect transistor is in a first level state in response to the third target control voltage signal to control the second N-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the drain of the second N-type field effect transistor to the source of the second N-type field effect transistor; the gate of the second P-type field effect transistor is in a second level state in response to the fourth target control voltage signal to control the second P-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the source of the second P-type field effect transistor to the drain of the second P-type field effect transistor.
[0010] According to an embodiment of the present disclosure, the source line level signal includes a first source line level signal, and the bit line level signal includes a first bit line level signal; when the resistive memory performs an initialization operation, the resistive memory controls the resistance state of the resistive memory to be converted to the first resistance state in response to the first source line level signal and the first bit line level signal, wherein the voltage value corresponding to the first source line level signal is higher than the voltage value corresponding to the first bit line level signal.
[0011] According to an embodiment of the present disclosure, the source line level signal also includes a second source line level signal, and the bit line level signal also includes a second bit line level signal; when the resistive memory performs a set operation, the resistive memory responds to the second source line level signal and the second bit line level signal to control the resistance state of the resistive memory to maintain the first resistance state, wherein the voltage value corresponding to the second source line level signal is higher than the voltage value corresponding to the second bit line level signal.
[0012] According to an embodiment of the present disclosure, the source line level signal also includes a third source line level signal, and the bit line level signal also includes a third bit line level signal; when the resistive memory performs a reset operation, the resistive memory responds to the third source line level signal and the third bit line level signal to control the resistance state of the resistive memory to be converted into a second resistance state, wherein the voltage value corresponding to the third bit line level signal is higher than the voltage value corresponding to the third source line level signal, and the resistance value corresponding to the second resistance state is higher than the resistance value corresponding to the first resistance state.
[0013] According to an embodiment of the present disclosure, the above architecture further includes: a read module electrically connected to the resistive random access memory via a bit line, and configured to execute a data read instruction.
[0014] According to an embodiment of the present disclosure, the above-mentioned architecture also includes: a connecting switch, which is arranged between the bit line and the read-out module. When the read-out module performs a read operation on the resistive random access memory, the connecting switch is in an on state in response to a preset voltage signal outside the chip, so that the read-out module reads the stored data of the resistive random access memory.
[0015] According to an embodiment of the present disclosure, a resistive random access memory (RRAM) is provided; a control module includes: a level converter for performing level conversion on an initial control voltage signal outside the chip to obtain a target control voltage signal; a bit line transistor for controlling the bit line of the control module to be in a conductive state according to the target control voltage signal; and a source line transistor for controlling the source line of the control module to be in a conductive state according to the target control voltage signal. The RRAM in the conductive state adjusts its resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state. Since the bit line transistor and source line transistor are provided outside the RRAM to replace the gate transistor inside the RRAM, the problem of the RRAM being too large is avoided, so that the RRAM reduces the unit area and storage cost while increasing the storage density. In addition, since the level converter is used to perform level conversion on the initial control voltage signal outside the chip, the problem of high power consumption of the architecture caused by directly receiving high voltage is avoided, and the stability of the RRAM is guaranteed while reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0017] Figure 1 Schematically shows a structural block diagram of a memory architecture according to an embodiment of the present disclosure;
[0018] Figure 2 Schematically shows a schematic diagram of a bit line transistor according to an embodiment of the present disclosure;
[0019] Figure 3 A schematic diagram of a resistive random access memory according to an embodiment of the present disclosure is schematically shown;
[0020] Figure 4 A schematic diagram schematically illustrates a memory architecture according to an embodiment of the present disclosure;
[0021] Figure 5 The diagram schematically shows a layout of a resistive random access memory according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0025] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).
[0026] Figure 1 The structural block diagram of the memory architecture according to an embodiment of the present disclosure is schematically shown.
[0027] According to a first aspect of the present disclosure, a resistive random access memory 300 architecture is provided, such as Figure 1 As shown, it includes: a resistive random access memory 300; an address decoder 100, which is used to convert the received address signal into a control signal; a word line driver module 200, which is electrically connected to the address decoder 100, and the word line driver module 200 includes a word line and a word line driver, and the word line driver is used to receive the control signal and adjust the level state of the word line based on the control signal to control the resistive random access memory 300 to be in a conductive state; a control module 400, which includes: a level converter 410, which is used to convert the level of the initial control voltage signal outside the chip to obtain a target control voltage signal, and the level of the target control voltage signal is high. at the level of the initial control voltage signal; a bit line transistor 420, for controlling the bit line of the control module 400 to be in an on state according to the target control voltage signal; a source line transistor 430, for controlling the source line of the control module 400 to be in an on state according to the target control voltage signal; the source line in the on state and the bit line in the on state are both electrically connected to the resistive random access memory 300, transmitting source line and bit line level signals to the resistive random access memory 300, and the resistive random access memory 300 in the on state adjusts the resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state.
[0028] According to an embodiment of the present disclosure, resistive random access memory (RRAM) 300 consists of two layers of electrodes and a resistor material. The electrodes are typically a top electrode and a bottom electrode. The middle resistor layer is typically made of a metal oxide (such as TiO2, HfO2, NiOx, etc.). This material has the ability to change its resistance characteristics under different voltages. This resistor layer is the core component for storing information.
[0029] According to an embodiment of the present disclosure, the address decoder 100 is used to convert address signals sent by the processor into control signals corresponding to the word line driver modules 200 .
[0030] According to an embodiment of the present disclosure, the word line driver applies different word line level signals to the word line in response to the control signal. Since the resistive memory 300 is controlled by a P-type field effect transistor in its conduction state, and the gate of the P-type field effect transistor is connected to the word line, when the level state of the word line is in a low level state, the resistive memory 300 is turned on. At this time, read and write operations can be performed on the resistive memory 300.
[0031] According to an embodiment of the present disclosure, since the resistive random access memory 300 adjusts the resistance state in response to the source line and bit line level signals, a large voltage difference is required between the source line and bit line level signals. In order to ensure that the high-voltage source line level signal can pass through the source line input value resistive random access memory 300, the gate voltage of the gate of the source line transistor 430 should also reach a corresponding high-voltage state.
[0032] Therefore, the level converter 410 can level-convert the input low-voltage initial control voltage signal and convert it into a target control voltage signal. For example, the level converter 410 can be used to convert the initial control voltage signal of 0.9V into a target control voltage signal of 2.5V, thereby controlling the conduction of the source line transistor 430, so that the high-voltage source line level signal can be input into the resistive memory 300; in addition, since the initial control voltage signal outside the chip input to the memory architecture is low voltage, the power consumption of the memory architecture can be reduced, and the problem of heat accumulation inside the architecture causing architectural instability can be avoided.
[0033] According to the embodiments of the present disclosure, the resistance state of the resistive layer of the resistive random access memory 300 is changed by applying an electric field, thereby achieving information storage. Under different voltages, the resistive layer is "programmed" into a high resistance state (HRS) or a low resistance state (LRS). These different resistance states represent a binary "0" or "1."
[0034] According to an embodiment of the present disclosure, the bit line transistor 420 and the source line transistor 430 respectively correspond to the target control voltage signal, control the source line and the bit line to be in the on state, and transmit the source line and bit line level signals to the resistive memory 300 to change the source line and bit line level signals in the resistive memory 300 to have a larger voltage difference, so that the resistance state of the resistance layer in the resistive memory 300 changes, and then the data write instruction is executed based on the resistance state.
[0035] According to an embodiment of the present disclosure, the resistive random access memory 300 architecture includes the resistive random access memory 300; a control module 400, including: a level converter 410, used to perform level conversion on an initial control voltage signal outside the chip to obtain a target control voltage signal; a bit line transistor 420, used to control the bit line of the control module 400 to be in an on state according to the target control voltage signal; a source line transistor 430, used to control the source line of the control module 400 to be in an on state according to the target control voltage signal; the resistive random access memory 300 in the on state adjusts the resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state. Since the bit line transistor 420 and the source line transistor 430 are provided outside the resistive random access memory 300 to replace the gate transistor inside the resistive random access memory 300, the problem of the resistive random access memory 300 being too large is avoided. As a result, the RRAM improves the storage density while reducing the unit area and lowering the storage cost. In addition, since the level converter 410 is used to convert the initial control voltage signal outside the chip, the problem of high power consumption of the architecture caused by directly receiving a high voltage is avoided. Therefore, the stability of the resistive random access memory 300 is ensured while reducing power consumption.
[0036] Figure 2 A schematic diagram of a bit line transistor according to an embodiment of the present disclosure is schematically shown.
[0037] According to the embodiments of the present disclosure, Figure 2 As shown, the bit line transistor includes a first N-type field effect transistor and a first P-type field effect transistor; the drain D1 of the first N-type field effect transistor is electrically connected to the bit line, the source S1 of the first N-type field effect transistor is electrically connected to the bit line, and the gate G1 of the first N-type field effect transistor is electrically connected to the level converter; the drain D2 of the first P-type field effect transistor is electrically connected to the bit line, the source S2 of the first P-type field effect transistor is electrically connected to the bit line, and the gate G2 of the first P-type field effect transistor is electrically connected to the level converter.
[0038] According to an embodiment of the present disclosure, the gate G1 of the first N-type field effect transistor is electrically connected to the level converter to receive the target control voltage signal BL Gn, so that the level state of the gate G1 of the first N-type field effect transistor changes, thereby controlling the conduction state of the first N-type field effect transistor.
[0039] According to an embodiment of the present disclosure, the first N-type field effect transistor is in the on state, and the bit line level signal is transmitted from the drain D1 of the first N-type field effect transistor to the source S1 of the first N-type field effect transistor to be transmitted into the resistive random access memory.
[0040] According to an embodiment of the present disclosure, the gate G2 of the first P-type field effect transistor is electrically connected to the level converter to receive the target control voltage signal BL Gp , so that the level state of the gate G2 of the first P-type field effect transistor changes, thereby controlling the conduction state of the first P-type field effect transistor.
[0041] According to an embodiment of the present disclosure, the first N-type field effect transistor is in the on state, and the bit line level signal is transmitted from the source S2 of the first P-type field effect transistor to the drain D2 of the first P-type field effect transistor to be transmitted to the resistive random access memory.
[0042] According to an embodiment of the present disclosure, the target control voltage signal includes a first target control voltage signal and a second target control voltage signal; the gate of the first N-type field effect transistor is in a first level state in response to the first target control voltage signal to control the first N-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the drain of the first N-type field effect transistor to the source of the first N-type field effect transistor; the gate of the first P-type field effect transistor is in a second level state in response to the second target control voltage signal to control the first P-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the source of the first P-type field effect transistor to the drain of the first P-type field effect transistor, wherein the level corresponding to the first level state is higher than the level of the second level state.
[0043] According to an embodiment of the present disclosure, the first level state can be a high level state. For example, the first target control voltage signal input to the gate of the first N-type field effect transistor may have a corresponding voltage value of 2.5V. The first N-type field effect transistor with the gate in the high level state is turned on, and the bit line level signal is transmitted from the drain of the first N-type field effect transistor to the source of the first N-type field effect transistor.
[0044] According to an embodiment of the present disclosure, the second level state can be a low level state. For example, the first target control voltage signal input to the gate of the first P-type field effect transistor may have a corresponding voltage value of 0v. The first P-type field effect transistor with the gate in a high level state is turned on, and the bit line level signal is transmitted from the source of the first P-type field effect transistor to the drain of the first P-type field effect transistor.
[0045] According to an embodiment of the present disclosure, the source line transistor includes a second N-type field effect transistor and a second P-type field effect transistor; the drain of the second N-type field effect transistor is electrically connected to the source line, the drain of the second N-type field effect transistor is electrically connected to the source line, and the gate of the second N-type field effect transistor is electrically connected to the level converter; the drain of the second P-type field effect transistor is electrically connected to the source line, the drain of the second P-type field effect transistor is electrically connected to the source line, and the gate of the second P-type field effect transistor is electrically connected to the level converter.
[0046] According to an embodiment of the present disclosure, the gate of the second N-type field effect transistor is electrically connected to the level converter to receive a target control voltage signal, so that the level state of the gate of the second N-type field effect transistor changes, thereby controlling the conduction state of the second N-type field effect transistor.
[0047] According to an embodiment of the present disclosure, in the on-state second N-type field effect transistor, a source line level signal is transmitted from the drain of the second N-type field effect transistor to the source of the second N-type field effect transistor, so as to be transmitted to the resistive random access memory.
[0048] According to an embodiment of the present disclosure, the gate of the second P-type field effect transistor is electrically connected to the level converter to receive a target control voltage signal, so that the level state of the gate of the second P-type field effect transistor changes, thereby controlling the conduction state of the second P-type field effect transistor.
[0049] According to an embodiment of the present disclosure, in the on-state second N-type field effect transistor, a source line level signal is transmitted from the source of the second P-type field effect transistor to the drain of the second P-type field effect transistor to be transmitted to the resistive random access memory.
[0050] According to an embodiment of the present disclosure, the target control voltage signal also includes a third target control voltage signal and a fourth target control voltage signal; the gate of the second N-type field effect transistor is in a first level state in response to the third target control voltage signal to control the second N-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the drain of the second N-type field effect transistor to the source of the second N-type field effect transistor; the gate of the second P-type field effect transistor is in a second level state in response to the fourth target control voltage signal to control the second P-type field effect transistor to be in an on state, so that the bit line level signal is transmitted from the source of the second P-type field effect transistor to the drain of the second P-type field effect transistor.
[0051] According to an embodiment of the present disclosure, the second level state can be a high level state. For example, the third target control voltage signal input to the gate of the second N-type field effect transistor may have a corresponding voltage value of 2.5V. The second N-type field effect transistor with the gate in the high level state is turned on, and the source line level signal is transmitted from the drain of the second N-type field effect transistor to the source of the second N-type field effect transistor.
[0052] According to an embodiment of the present disclosure, the second level state can be a low level state. For example, the fourth target control voltage signal input to the gate of the second P-type field effect transistor may have a corresponding voltage value of 0v. The second P-type field effect transistor with the gate in a high level state is turned on, and the source line level signal is transmitted from the source of the second P-type field effect transistor to the drain of the second P-type field effect transistor.
[0053] Figure 3 The figure schematically shows a resistive random access memory according to an embodiment of the present disclosure.
[0054] According to the embodiments of the present disclosure, Figure 3 As shown, the resistive random access memory includes multiple transistors (core tubes) and resistors, wherein the gate of the transistor is electrically connected to the word line WL, and the source line SL and the bit line BL are respectively connected to the two ends of each resistor to adjust the resistance state in response to the source line level signal (SLn, SLp) and the bit line level signal (BLn, BLp), and execute data write instructions based on the resistance state.
[0055] According to an embodiment of the present disclosure, the source line level signal includes a first source line level signal, and the bit line level signal includes a first bit line level signal; when the resistive memory performs an initialization operation, the resistive memory controls the resistance state of the resistive memory to be converted to the first resistance state in response to the first source line level signal and the first bit line level signal, wherein the voltage value corresponding to the first source line level signal is higher than the voltage value corresponding to the first bit line level signal.
[0056] According to the embodiments of the present disclosure, forming is the initialization process for RRAM when it is first used. This process involves applying a high voltage (typically several volts) to the resistive layer, causing a sudden change in the material's resistance. This change in the resistive layer of the RRAM creates a "conductive channel" within it, which makes it easier to change resistance during subsequent programming operations. The forming process results in the RRAM's resistive layer being "pre-tuned" to a programmable state, providing a foundation for subsequent programming operations.
[0057] According to an embodiment of the present disclosure, a resistive memory generates a voltage difference between a source line and a bit line within the resistive memory in response to a first source line level signal and a first bit line level signal, causing a sudden change in the resistance connected to the source line and the bit line, thereby forming a "conductive channel" within the resistive memory to complete the initialization operation. For example, the voltage value corresponding to the first source line level signal may be Analog1 = 2.5V, and the voltage value corresponding to the first bit line level signal may be Analog1 = 0.9V. The voltage difference generated between the source line and the bit line causes a sudden change in the resistance within the resistive memory, wherein the first bit line level signal and the first source line level signal may be input from off-chip.
[0058] According to an embodiment of the present disclosure, the source line level signal also includes a second source line level signal, and the bit line level signal also includes a second bit line level signal; when the resistive memory performs a set operation, the resistive memory responds to the second source line level signal and the second bit line level signal to control the resistance state of the resistive memory to maintain the first resistance state, wherein the voltage value corresponding to the second source line level signal is higher than the voltage value corresponding to the second bit line level signal.
[0059] According to an embodiment of the present disclosure, the set operation is such that the relative relationship between the voltages of the source line and the bit line is consistent with that during the initialization operation. For example, in the initialization operation, the voltage value corresponding to the first source line level signal is higher than the voltage value corresponding to the first bit line level signal. Then, in the set operation, the voltage value corresponding to the second source line level signal is higher than the voltage value corresponding to the second bit line level signal, so that the relative relationship between the voltages of the source line and the bit line is consistent with that during the initialization operation. For example, the voltage value corresponding to the second source line level signal can be High-V = 2.5v, and the voltage value corresponding to the second bit line level signal can be Analog3 = 0.7v. The relative relationship between the voltages of the source line and the bit line is consistent with that during the initialization operation. The resistance state of the resistive memory is maintained in a low resistance state, and the state of the resistance layer is converted to store "1".
[0060] According to an embodiment of the present disclosure, the source line level signal also includes a third source line level signal, and the bit line level signal also includes a third bit line level signal; when the resistive memory performs a reset operation, the resistive memory responds to the third source line level signal and the third bit line level signal to control the resistance state of the resistive memory to be converted into a second resistance state, wherein the voltage value corresponding to the third bit line level signal is higher than the voltage value corresponding to the third source line level signal, and the resistance value corresponding to the second resistance state is higher than the resistance value corresponding to the first resistance state.
[0061] According to an embodiment of the present disclosure, a reset operation is performed such that the relative relationship between the voltages of the source line and the bit line is opposite to that during the initialization operation. For example, in the initialization operation, the voltage value corresponding to the first source line level signal is higher than the voltage value corresponding to the first bit line level signal. Then, in the reset operation, the voltage value corresponding to the third bit line level signal is higher than the voltage value corresponding to the third source line level signal, so that the relative relationship between the voltages of the source line and the bit line is opposite to that during the initialization operation. For example, the voltage value corresponding to the third source line level signal may be Analog4 = 0.7v, and the voltage value corresponding to the third bit line level signal may be High-V = 2.5v. The relative relationship between the voltages of the source line and the bit line is opposite to that during the initialization operation, and the resistance state of the resistive memory is maintained in a high resistance state, and the state of the resistance layer is converted to store "0".
[0062] According to an embodiment of the present disclosure, the above architecture further includes: a read module electrically connected to the resistive random access memory via a bit line, and configured to execute a data read instruction.
[0063] According to an embodiment of the present disclosure, when the read module executes a data read instruction, it reads data from the resistive random access memory through the bit line. At this time, both the source line transistor and the bit line transistor are in the off state to interrupt the data writing operation of the resistive random access memory and avoid affecting the data reading operation.
[0064] According to an embodiment of the present disclosure, the above-mentioned architecture also includes: a connecting switch, which is arranged between the bit line and the read-out module. When the read-out module performs a read operation on the resistive random access memory, the connecting switch is in an on state in response to a preset voltage signal outside the chip, so that the read-out module reads the stored data of the resistive random access memory.
[0065] According to an embodiment of the present disclosure, a connection switch is placed between the bit line and the readout module. When a preset voltage signal is applied to the connection switch, the connection switch is turned on, allowing the readout module to read data from the resistive random access memory through the bit line. For example, when the readout module is performing a data read operation, core-V = 0.9V can be applied to the connection switch, turning the connection switch on. If the readout module stops performing the read operation, GND = 0V is applied to the connection switch, turning the connection switch off to avoid affecting the data write operation of the resistive random access memory.
[0066] Figure 4 The diagram schematically shows a memory architecture according to an embodiment of the present disclosure.
[0067] According to the embodiments of the present disclosure, Figure 4As shown, after the address decoder converts the received address signal into a control signal, the wordline driver responds to the control signal and applies a voltage to the wordline to control the conduction of the resistive random access memory. Furthermore, an initial control voltage signal from outside the chip is input into the resistive random access memory architecture and converted into a target control voltage signal via a level converter. The bitline transistor and the source line transistor both respond to the target control voltage signal to control the bitline transistor and the source line transistor to be in a conductive state. This enables the resistive random access memory in a conductive state to respond to the source line and bitline level signals input from outside the chip into the memory architecture to adjust the resistance state and execute data write instructions based on the resistance state. When executing a data read instruction, the bitline transistor and the source line transistor are both controlled to be in an off state, and the connection switch is controlled to be conductive, so that the read module can read data from the resistive random access memory through the bitline. In this case, data write instructions and data read instructions can be executed based on Table 1.
[0068]
[0069] Figure 5 The diagram schematically shows a layout of a resistive random access memory according to an embodiment of the present disclosure.
[0070] According to the embodiments of the present disclosure, Figure 5 As shown, 510 is the active area, which serves as the source, drain, and substrate regions of the RRAM transistors; 520 is the gate of the RRAM transistors; 530 is the source line; 540 is the word line; and 550 is the bit line. Source line 530 is perpendicular to word line 540 and connects to the source and drain of the two RRAM transistors in the active area 510. Source line 530 is fabricated using multiple layers of metal to ensure current density. 560 is the contact through which word line 540 connects to the gate 520 of the transistor. The RRAM resistors and transistors are located in the vias (through-holes). The RRAM is fabricated using a 28nm HKMG process. Through its compact layout design, the RRAM achieves superior storage density compared to previous similar structures, achieving an array density of 17.4Mb / mm² and a macrocell density of 15.8Mb / mm².
[0071] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.
[0072] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A resistive random access memory architecture, characterized in that: The architecture includes: Resistive RAM; An address decoder, configured to convert a received address signal into a control signal; a word line driver module electrically connected to the address decoder, the word line driver module comprising a word line and a word line driver, the word line driver being configured to receive the control signal and adjust a level state of the word line based on the control signal to control the resistive random access memory to be in an on state; Control module, including: a level converter, configured to perform level conversion on an initial control voltage signal outside the chip to obtain a target control voltage signal, wherein the level of the target control voltage signal is higher than the level of the initial control voltage signal; A bit line transistor, configured to control the bit line of the control module to be in an on state according to the target control voltage signal; a source line transistor, configured to control the source line of the control module to be in an on state according to the target control voltage signal; The source line in the on state and the bit line in the on state are both electrically connected to the resistive memory, and source line and bit line level signals are transmitted to the resistive memory. The resistive memory in the on state adjusts its resistance state in response to the source line and bit line level signals, and executes a data write instruction based on the resistance state.
2. The architecture according to claim 1, wherein: The bit line transistor includes a first N-type field effect transistor and a first P-type field effect transistor; The drain of the first N-type field effect transistor is electrically connected to the bit line, the source of the first N-type field effect transistor is electrically connected to the bit line, and the gate of the first N-type field effect transistor is electrically connected to the level shifter; A drain of the first P-type field effect transistor is electrically connected to the bit line, a source of the first P-type field effect transistor is electrically connected to the bit line, and a gate of the first P-type field effect transistor is electrically connected to the level shifter.
3. The architecture according to claim 2, characterized in that The target control voltage signal includes a first target control voltage signal and a second target control voltage signal; The gate of the first N-type field effect transistor is in a first level state in response to the first target control voltage signal, so as to control the first N-type field effect transistor to be in a conductive state, so that the bit line level signal is transmitted to the source of the first N-type field effect transistor through the drain of the first N-type field effect transistor; The gate of the first P-type field effect transistor is in a second level state in response to the second target control voltage signal to control the first P-type field effect transistor to be in an on state, so that the bit line level signal is transmitted to the drain of the first P-type field effect transistor through the source of the first P-type field effect transistor, wherein the level corresponding to the first level state is higher than the level of the second level state.
4. The architecture according to claim 3, wherein: The source line transistor includes a second N-type field effect transistor and a second P-type field effect transistor; The drain of the second N-type field effect transistor is electrically connected to the source line, the drain of the second N-type field effect transistor is electrically connected to the source line, and the gate of the second N-type field effect transistor is electrically connected to the level converter; A drain of the second P-type field effect transistor is electrically connected to the source line, a gate of the second P-type field effect transistor is electrically connected to the level shifter.
5. The architecture according to claim 4, characterized in that The target control voltage signal further includes a third target control voltage signal and a fourth target control voltage signal; The gate of the second N-type field effect transistor is in the first level state in response to the third target control voltage signal, so as to control the second N-type field effect transistor to be in a conductive state, so that the bit line level signal is transmitted to the source of the second N-type field effect transistor through the drain of the second N-type field effect transistor; The gate of the second P-type field effect transistor is in the second level state in response to the fourth target control voltage signal to control the second P-type field effect transistor to be in the on state, so that the bit line level signal is transmitted to the drain of the second P-type field effect transistor through the source of the second P-type field effect transistor.
6. The architecture according to claim 1, wherein: The source line level signal includes a first source line level signal, and the bit line level signal includes a first bit line level signal; When the resistive memory performs an initialization operation, the resistive memory controls the resistance state of the resistive memory to be converted into a first resistance state in response to the first source line level signal and the first bit line level signal, wherein the voltage value corresponding to the first source line level signal is higher than the voltage value corresponding to the first bit line level signal.
7. The architecture according to claim 1, wherein: The source line level signal further includes a second source line level signal, and the bit line level signal further includes a second bit line level signal; When the resistive memory performs a set operation, the resistive memory controls the resistance state of the resistive memory to maintain the first resistance state in response to the second source line level signal and the second bit line level signal, wherein the voltage value corresponding to the second source line level signal is higher than the voltage value corresponding to the second bit line level signal.
8. The architecture according to claim 1, wherein: The source line level signal further includes a third source line level signal, and the bit line level signal further includes a third bit line level signal; When the resistive memory performs a reset operation, the resistive memory controls the resistance state of the resistive memory to be converted into a second resistance state in response to the third source line level signal and the third bit line level signal, wherein a voltage value corresponding to the third bit line level signal is higher than a voltage value corresponding to the third source line level signal, and a resistance value corresponding to the second resistance state is higher than a resistance value corresponding to the first resistance state.
9. The architecture according to claim 1, wherein: The architecture also includes: A readout module is electrically connected to the resistive random access memory through the bit line and is used to execute a data readout instruction.
10. The architecture according to claim 9, characterized in that The architecture also includes: A connecting switch is arranged between the bit line and the read module. When the read module performs the read operation on the resistive memory, the connecting switch is in an on state in response to a preset voltage signal outside the chip, so that the read module reads the stored data of the resistive memory.