Ripple elimination circuit, DC-DC converter, method, chip and equipment

Abstract

The invention provides a ripple elimination circuit, a DC-DC converter, a method, a chip and equipment. And fourth current can be obtained through the ripple elimination circuit according to the first current and the third current. The ripple elimination circuit can obtain a first signal according to the second current and the fourth current. Thus, the ripple elimination circuit can generate a pulse width modulation signal according to the first signal and the second signal. The third current changes along with the change of the input voltage of the DC-DC converter, so that the fourth current also changes along with the change of the input voltage. Therefore, the flip point of the first signal changes along with the change of the input voltage, so that the rising edge of the pulse width modulation signal changes along with the change of the input voltage. Furthermore, the pulse width modulation signal can change along with the change of the input voltage. Therefore, the DC-DC converter can eliminate the influence of the input voltage on the output voltage ripple, reduce the output voltage ripple, and ensure the stability of the output voltage.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a ripple elimination circuit, a DC-DC converter, a method, a chip, and a device. Background Art

[0002] Direct current-direct current (DC-DC) converters are widely used in electronic products due to their high efficiency and high voltage regulation capabilities. Currently, pulse width modulation (PWM) control is used to ensure the stability of the DC-DC output voltage.

[0003] However, because the PWM technology used in related technologies cannot quickly respond to changes in the DC-DC input voltage, it results in large output voltage ripple. Consequently, when DC-DC is used in electronic products, it can cause screen ripples. Screen ripples refer to alternating light and dark stripes on the screen of an electronic product. Summary of the Invention

[0004] The present application provides a ripple elimination circuit, a DC-DC converter, a method, a chip, and a device, which can reduce output voltage ripple and prevent screen ripples on electronic products.

[0005] In a first aspect, the present application provides a ripple elimination circuit, wherein the ripple elimination circuit is applied to a DC-DC converter;

[0006] The first input terminal of the ripple elimination circuit is used to receive a first current, which is used to represent the load current of the DC-DC converter; the second input terminal of the ripple elimination circuit is used to receive a second current, which is used to represent the change of the inductor current in the DC-DC converter; the output terminal of the ripple elimination circuit is used to output a pulse width modulation signal, which is used to control the conduction or shutdown of the power transistor in the DC-DC converter;

[0007] The ripple elimination circuit is configured to obtain a fourth current based on the first current and the third current, wherein the third current varies in response to a change in an input voltage of the DC-DC converter, and the fourth current is configured to represent a valley value of an inductor current in the DC-DC converter;

[0008] The ripple elimination circuit is further configured to obtain a first signal according to the second current and the fourth current, wherein the first signal is used to determine a rising edge of the pulse width modulation signal;

[0009] The ripple elimination circuit is further configured to generate the pulse width modulation signal according to the first signal and the second signal, wherein the second signal is used to determine a switching period of the DC-DC converter.

[0010] The ripple cancellation circuit provided in the first aspect can generate a fourth current, used to characterize the valley value of the inductor current in the DC-DC converter, based on the first current and the third current. The ripple cancellation circuit can also generate a first signal, used to determine the rising edge of the pulse-width modulation signal, based on the second current and the fourth current. Thus, the ripple cancellation circuit can generate a pulse-width modulation signal based on the first signal and the second signal, used to determine the switching period of the DC-DC converter. Because the third current varies with changes in the input voltage of the DC-DC converter, the fourth current also varies with changes in the input voltage of the DC-DC converter. Thus, the flip point of the first signal, i.e., the moment when the first signal flips from the first level to the second level, also varies with changes in the input voltage of the DC-DC converter, causing the rising edge of the pulse-width modulation signal to vary with changes in the input voltage of the DC-DC converter. Furthermore, the pulse-width modulation signal can vary with changes in the input voltage of the DC-DC converter, enabling the DC-DC converter to quickly respond to changes in the input voltage. Therefore, the DC-DC converter can eliminate the influence of input voltage on output voltage ripple, reduce output voltage ripple, ensure output voltage stability, and avoid screen ripples in electronic products using DC-DC converters.

[0011] In one possible design, the ripple elimination circuit includes: a fourth current output circuit, a first comparator, an oscillator, and a driver;

[0012] The input end of the fourth current output circuit is used to receive the first current, the output end of the fourth current output circuit is electrically connected to the first input end of the first comparator, the second input end of the first comparator is used to receive the second current, the output end of the first comparator is electrically connected to the first input end of the driver, the output end of the oscillator is electrically connected to the second input end of the driver, and the output end of the driver is used to output the pulse width modulation signal;

[0013] the fourth current output circuit is configured to determine a current difference between the first current and the third current as the fourth current, and transmit the fourth current to the first comparator;

[0014] The first comparator is configured to compare the magnitude of the fourth current and the second current to obtain the first signal, and transmit the first signal to the driver;

[0015] The oscillator is configured to generate the second signal and transmit the second signal to the driver;

[0016] The driver is configured to generate the pulse width modulation signal according to the first signal and the second signal.

[0017] Based on this, the fourth current output circuit can determine the current difference between the first current and the third current as a fourth current and transmit the fourth current to the first comparator, allowing the first comparator to obtain the fourth current. In this way, the first comparator can compare the magnitude of the fourth current with the second current to obtain a first signal, and transmit the first signal to the driver, allowing the driver to obtain the first signal. The oscillator can generate a second signal and transmit the second signal to the driver, allowing the driver to obtain the second signal. Consequently, the driver can generate a pulse-width modulated signal based on the first and second signals, allowing the ripple cancellation circuit to generate a pulse-width modulated signal.

[0018] In one possible design, the fourth current output circuit includes: a first current source and a second current source;

[0019] A first terminal of the first current source is used to receive a first current, a second terminal of the first current source is electrically connected to a first terminal of the second current source, a second terminal of the second current source is grounded, and a first input terminal of the first comparator is electrically connected between the second terminal of the first current source and the first terminal of the second current source;

[0020] The first current source is configured to output the first current;

[0021] The second current source is configured to output the third current.

[0022] Based on this, the first current source can output the first current. The second current source can output the third current. Thus, the fourth current output circuit can determine the current difference between the first current and the third current as the fourth current.

[0023] In one possible design, the second current is calculated according to the following formula 1:

[0024] I2=Iavg-(A*I_ripple-Islope) Formula 1

[0025] Wherein, I2 is the second current, Iavg is the average inductor current, A is the inductor current ripple coefficient, I_ripple is the inductor current ripple, Islope is the ramp compensation current, and the slope of the ramp compensation current is the same as the rising slope of the inductor current.

[0026] In one possible design, the third current is calculated according to the following formula 2:

[0027] I_DC=A*I_ripple-Islope formula 2

[0028] Wherein, I_DC is the third current, A is the inductor current ripple coefficient, I_ripple is the inductor current ripple, Islope is the ramp compensation current, and the slope of the ramp compensation current is the same as the rising slope of the inductor current.

[0029] In one possible design, when the DC-DC converter is a buck converter, the inductor current ripple is calculated according to the following formula 3, and the ramp compensation current is calculated according to the following formula 4:

[0030] I_ripple=[(VIN-VOUT) / VIN)]*Ts*(-VOUT) / LFormula 3

[0031] Islope=0.5*[(VIN-VOUT) / VIN)]*Ts*(VIN-VOUT) / L Formula 4

[0032] Wherein, VIN is the input voltage of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, Ts is the switching period of the DC-DC converter, and L is the inductance of the inductor in the DC-DC converter.

[0033] In one possible design, when the DC-DC converter is a boost converter, the inductor current ripple is calculated according to the following formula 5, and the ramp compensation current is calculated according to the following formula 6:

[0034] I_ripple=(VIN / VOUT)*Ts*(VIN-VOUT) / LFormula 5

[0035] Islope=0.5*(VIN / VOUT)*Ts*VIN / L Formula 6

[0036] Wherein, VIN is the input voltage of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, Ts is the switching period of the DC-DC converter, and L is the inductance of the inductor in the DC-DC converter.

[0037] In one possible design, when the DC-DC converter is a buck-boost converter, the inductor current ripple is calculated according to the following formula 7, and the ramp compensation current is calculated according to the following formula 8:

[0038] I_ripple=0.5*VIN / (VIN+|VOUT|)*Ts*(-|VOUT|) / LFormula 7

[0039] Islope=0.5*VIN / (VIN+|VOUT|)*Ts*(VIN / L) Formula 8

[0040] Wherein, VIN is the input voltage of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, Ts is the switching period of the DC-DC converter, and L is the inductance of the inductor in the DC-DC converter.

[0041] In a possible design, the inductor current ripple factor is 0.5.

[0042] In a second aspect, the present application provides a DC-DC converter, the DC-DC converter comprising: a first current output circuit, a second current output circuit, a voltage conversion circuit, and the ripple elimination circuit in the first aspect and in each possible design of the first aspect;

[0043] The input end of the voltage conversion circuit is used to connect to the input voltage of the DC-DC converter, and the output end of the voltage conversion circuit is used to output the output voltage of the DC-DC converter. The output end of the voltage conversion circuit is also electrically connected to the input end of the first current output circuit, and the output end of the first current output circuit is electrically connected to the first input end of the ripple elimination circuit. The input end of the second current output circuit is used to collect the inductor current of the inductor in the voltage conversion circuit, the output end of the second current output circuit is electrically connected to the second input end of the ripple elimination circuit, and the output end of the ripple elimination circuit is electrically connected to the control end of the voltage conversion circuit.

[0044] In one possible design, when the DC-DC converter is a buck converter, the first current output circuit includes: a feedback circuit and a second comparator;

[0045] The input end of the feedback circuit is electrically connected to the output end of the voltage conversion circuit, the output end of the feedback circuit is electrically connected to the second input end of the second comparator, the first input end of the second comparator is used to access the reference voltage, and the output end of the second comparator is electrically connected to the first input end of the ripple elimination circuit.

[0046] In one possible design, when the DC-DC converter is a boost converter or a buck-boost converter, the first current output circuit includes: a feedback circuit, a multiplier, and a second comparator;

[0047] The input end of the feedback circuit is electrically connected to the output end of the voltage conversion circuit, the output end of the feedback circuit is electrically connected to the second input end of the second comparator, the first input end of the second comparator is used to access the reference voltage, the output end of the second comparator is electrically connected to the first input end of the multiplier, the second input end of the multiplier is used to access the input voltage, the third input end of the multiplier is used to access the output voltage, and the output end of the multiplier is electrically connected to the first input end of the ripple elimination circuit.

[0048] In one possible design, the voltage conversion circuit includes: a high-side power transistor, a low-side power transistor, and an inductor;

[0049] When the DC-DC converter is a buck converter, the drain terminal of the high-side power transistor is used to access the input voltage, the source terminal of the high-side power transistor is electrically connected to the drain terminal of the low-side power transistor and the first end of the inductor respectively, the gate terminal of the high-side power transistor and the gate terminal of the low-side power transistor are both electrically connected to the output terminal of the ripple elimination circuit, the source terminal of the low-side power transistor is grounded, and the second end of the inductor is used to output the output voltage;

[0050] Alternatively, when the DC-DC converter is a boost converter, the source terminal of the high-side power transistor is used to output the output voltage, the drain terminal of the high-side power transistor is electrically connected to the first terminal of the inductor and the drain terminal of the low-side power transistor respectively, the gate terminal of the high-side power transistor and the gate terminal of the low-side power transistor are both electrically connected to the output terminal of the ripple elimination circuit, the second terminal of the inductor is used to access the input voltage, and the source terminal of the low-side power transistor is grounded;

[0051] Alternatively, when the DC-DC converter is a buck-boost converter, the drain terminal of the high-side power transistor is used to access the input voltage, the source terminal of the high-side power transistor is electrically connected to the first end of the inductor and the drain terminal of the low-side power transistor respectively, the gate terminal of the high-side power transistor and the gate terminal of the low-side power transistor are both electrically connected to the output terminal of the ripple elimination circuit, the source terminal of the low-side power transistor is used to output the output voltage, and the second end of the inductor is grounded.

[0052] The beneficial effects of the DC-DC converter provided in the second aspect and each possible design of the second aspect can be referred to the beneficial effects brought about by the first aspect and each possible implementation method of the first aspect, and will not be repeated here.

[0053] In a third aspect, the present application provides a ripple elimination method, which is performed by a ripple elimination circuit in the first aspect and various possible designs of the first aspect, wherein the ripple elimination circuit is applied to a DC-DC converter, wherein a first input terminal of the ripple elimination circuit is used to receive a first current, wherein the first current is used to characterize the load current of the DC-DC converter, a second input terminal of the ripple elimination circuit is used to receive a second current, wherein the second current is used to characterize a change in an inductor current in the DC-DC converter, and an output terminal of the ripple elimination circuit is used to output a pulse width modulation signal, wherein the pulse width modulation signal is used to control the on or off of a power transistor in the DC-DC converter; the method comprising:

[0054] The ripple elimination circuit obtains a fourth current based on the first current and the third current, wherein the third current changes in response to a change in the input voltage of the DC-DC converter, and the fourth current is used to characterize a valley value of the inductor current in the DC-DC converter;

[0055] The ripple elimination circuit obtains a first signal according to the second current and the fourth current, wherein the first signal is used to determine a rising edge of the pulse width modulation signal;

[0056] The ripple elimination circuit generates the pulse width modulation signal according to the first signal and the second signal, and the second signal is used to determine the switching period of the DC-DC converter.

[0057] In a fourth aspect, the present application provides a chip, comprising: the ripple elimination circuit in the above-mentioned first aspect and each possible design of the above-mentioned first aspect, or the DC-DC converter in the above-mentioned second aspect.

[0058] In a fifth aspect, the present application provides an electronic device, comprising: the chip in the fourth aspect above.

[0059] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, they can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] Figure 1A schematic structural diagram of a ripple elimination circuit provided in one embodiment of the present application;

[0062] Figure 2 A schematic flow chart of a ripple elimination method provided in one embodiment of the present application;

[0063] Figure 3 for Figure 1 Schematic diagram of the principle of generating pulse width modulation signal by ripple elimination circuit;

[0064] Figure 4 A schematic diagram of operating waveforms of a ripple elimination circuit provided in one embodiment of the present application;

[0065] Figure 5 for Figure 1 A schematic diagram of the principle of generating a first signal by a ripple elimination circuit;

[0066] Figure 6 A schematic diagram of the working principle of a ripple elimination circuit provided in one embodiment of the present application;

[0067] Figure 7 A schematic structural diagram of a DC-DC converter provided in one embodiment of the present application;

[0068] Figure 8 A schematic structural diagram of another DC-DC converter provided in one embodiment of the present application;

[0069] Figure 9 A schematic structural diagram of another DC-DC converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0071] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0072] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0073] First, the professional terms involved in the embodiments of this application are explained.

[0074] A direct current-direct current (DC-DC) converter is a device that converts a fixed DC voltage into a variable DC voltage. The main function of a DC-DC converter is to convert one DC voltage into another. The output voltage of a DC-DC converter can be higher than the input voltage of the DC-DC converter, or lower than the input voltage of the DC-DC converter. Based on their basic topology, DC-DC converters can be divided into three basic types: buck converters (Buck), boost converters (Boost), and buck-boost converters (Buck-Boost).

[0075] The switching cycle refers to the duration of each on and off of a power transistor. The switching cycle is equal to the sum of the on-time Ton and the off-time Toff of the power transistor.

[0076] Switching frequency refers to the number of times a power transistor turns on and off per unit time. It is usually represented by f and is measured in Hertz. Switching frequency = 1 / switching period.

[0077] Pulse-width modulation (PWM) is an analog control method that modulates the bias of the transistor base or the gate of the field-effect transistor according to the change of the corresponding load to change the conduction time of the transistor or field-effect transistor, thereby changing the output of the switching regulated power supply.

[0078] Valley comparison mode is also known as constant on-time control (COT). In this mode, the on-time of the power transistor is fixed, while the off-time is dynamically adjusted based on changes in load conditions, input voltage, and output voltage.

[0079] Output voltage ripple refers to the AC fluctuations in the output voltage of a DC-DC converter. This AC fluctuation is usually related to the switching action of the DC-DC converter.

[0080] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a ripple elimination circuit provided in one embodiment of the present application. Figure 3 Shown Figure 1 Schematic diagram of the principle of generating pulse width modulation signal by ripple elimination circuit. Figure 1 As shown, a first input terminal of the ripple elimination circuit 100 is used to receive a first current ICOMP, which is used to represent the load current IO of the DC-DC converter 1000. A second input terminal of the ripple elimination circuit 100 is used to receive a second current I2, which is used to represent the change of the inductor current IIND in the DC-DC converter 1000. An output terminal of the ripple elimination circuit 100 is used to output a pulse width modulation signal PWM, which is used to control the on or off of the power transistor in the DC-DC converter 1000.

[0081] Below, refer to Figure 2 , Figure 2 A flowchart of a ripple elimination method provided in one embodiment of the present application is provided.

[0082] S101: A ripple elimination circuit obtains a fourth current according to a first current and a third current.

[0083] The third current I_DC varies with the input voltage VIN of the DC-DC converter 1000 . The fourth current I4 represents the valley value IVAL of the inductor current IIND in the DC-DC converter 1000 .

[0084] S102: The ripple elimination circuit obtains a first signal according to the second current and the fourth current.

[0085] The first signal VAL_PULSE is used to determine the rising edge of the pulse width modulation signal PWM.

[0086] S103 : The ripple elimination circuit generates a pulse width modulation signal according to the first signal and the second signal.

[0087] The second signal VOSC is used to determine the switching period Ts of the DC-DC converter 1000 .

[0088] The ripple cancellation circuit 100 can obtain a fourth current I4 according to the first current ICOMP and the third current I_DC.

[0089] The third current I_DC varies with the input voltage VIN of the DC-DC converter 1000 , and the fourth current I4 is used to represent the valley value of the inductor current IIND in the DC-DC converter 1000 .

[0090] The third current I_DC can be calculated according to the following formula (1):

[0091] I_DC=A*I_ripple-Islope (1)

[0092] Wherein, I_DC is the third current, A is the inductor current ripple coefficient, I_ripple is the inductor current ripple, Islope is the ramp compensation current, and the slope Islope of the ramp compensation current is the same as the rising slope IIND of the inductor current.

[0093] In some examples, the inductor current ripple factor A is 0.5.

[0094] The inductor current ripple coefficient A refers to a coefficient related to the inductor current ripple I_ripple. Different values ​​of the inductor current ripple coefficient A correspond to different characteristics of the inductor current ripple. When the inductor current ripple coefficient A is 0.5, 0.5I_ripple represents half the ripple of the inductor current ripple I_ripple. For ease of explanation, the embodiments of this application use half the ripple of the inductor current ripple I_ripple as an example.

[0095] Among them, the inductor current ripple coefficient A can be 0.48, the inductor current ripple coefficient A can also be 0.51, and the inductor current ripple coefficient A can also be any value close to 0.5, all of which are within the protection scope of the embodiments of the present application.

[0096] The ripple cancellation circuit 100 can obtain a first signal VAL_PULSE according to the second current I2 and the fourth current I4 .

[0097] The first signal VAL_PULSE is used to determine the rising edge of the pulse width modulation signal PWM.

[0098] The second current I2 can be calculated according to the following formula (2):

[0099] I2=Iavg-(0.5I_ripple-Islope) (2)

[0100] Wherein, I2 is the second current, Iavg is the average inductor current, I_ripple is the inductor current ripple, Islope is the ramp compensation current, and the slope of the ramp compensation current Islope is the same as the rising slope of the inductor current IIND.

[0101] In this way, the ripple elimination circuit 100 can generate the following signals according to the first signal VAL_PULSE and the second signal VOSC: Figure 3 The pulse width modulation signal PWM is shown.

[0102] For example, when the first signal VAL_PULSE flips from a first level to a second level, the pulse-width modulation signal PWM changes from a low level to a high level. In other words, the first signal VAL_PULSE can determine the rising edge of the pulse-width modulation signal PWM. At the end of the switching period Ts of the DC-DC converter 1000, as determined by the second signal VOSC, the pulse-width modulation signal PWM changes from a high level to a low level. In other words, the second signal VOSC can determine the falling edge of the pulse-width modulation signal PWM. Thus, the ripple cancellation circuit 100 can generate the pulse-width modulation signal PWM based on the first signal VAL_PULSE and the second signal VOSC.

[0103] When the pulse width modulation signal PWM is the first pulse width modulation signal LSD_ON in the pulse width modulation signal PWM, the low-side power transistor LS in the DC-DC converter 1000 is turned on, and the high-side power transistor HS in the DC-DC converter 1000 is turned off. When the pulse width modulation signal PWM is the second pulse width modulation signal HSD_ON in the pulse width modulation signal PWM, the low-side power transistor LS in the DC-DC converter 1000 is turned off, and the high-side power transistor HS in the DC-DC converter 1000 is turned on.

[0104] The second signal VOSC is used to determine the switching period Ts of the DC-DC converter 1000 .

[0105] Because the third current I_DC varies with changes in the input voltage VIN of the DC-DC converter 1000, the fourth current I4 also varies with changes in the input voltage VIN of the DC-DC converter 1000. Thus, the switching point of the first signal VAL_PULSE, i.e., the moment when the first signal VAL_PULSE switches from the first level to the second level, also varies with changes in the input voltage VIN of the DC-DC converter 1000. This causes the rising edge of the pulse-width modulation signal PWM to vary with changes in the input voltage VIN of the DC-DC converter 1000. Furthermore, the pulse-width modulation signal PWM can vary with changes in the input voltage VIN of the DC-DC converter 1000, enabling the DC-DC converter 1000 to quickly respond to changes in the input voltage VIN. Therefore, the DC-DC converter 1000 can eliminate the influence of the input voltage VIN on the output voltage ripple VOUT_RIPPLE, reduce the output voltage ripple VOUT_RIPPLE, ensure the stability of the output voltage of the DC-DC converter 1000, and avoid the generation of screen ripples in electronic products using the DC-DC converter 1000.

[0106] Reference Figure 4 , Figure 4 This is a schematic diagram of the working waveform of a ripple elimination circuit provided in an embodiment of the present application. Figure 4 As shown, in the related art, when the input voltage VIN changes, the duty cycle of the DC-DC converter 1000 changes, causing the first current ICOMP to become current I_COMP1. Because current I_COMP1 is greater than the load current IO, that is, the current I_COMP1 provided by the DC-DC converter 1000 exceeds the load current IO required by the load. Therefore, the excess current in current I_COMP1 charges the output capacitor of the DC-DC converter 1000, causing the output voltage VOUT to increase, resulting in a large output voltage ripple VOUT_RIPPLE1, for example, on the order of tens of millivolts.

[0107] In the embodiment of the present application, since the third current I_DC varies with changes in the input voltage VIN of the DC-DC converter 1000, the first current ICOMP actively varies with changes in the input voltage VIN of the DC-DC converter 1000. Therefore, the first current ICOMP becomes current I_COMP2. Thus, the change in I_COMP2 is small, resulting in a very small current I_COMP2 provided by the DC-DC converter 1000. Consequently, compared to the output voltage ripple VOUT_RIPPLE1 in the related art, the output voltage ripple VOUT_RIPPLE2 of the DC-DC converter 1000 in the present application is significantly reduced, for example, to 5 mV.

[0108] In particular, if the influence of process variations on the DC-DC converter 1000 is not considered, the first current ICOMP can always be equal to the load current IO due to the third current I_DC. In other words, the first current ICOMP will not be affected by the input voltage VIN of the DC-DC converter 1000. Therefore, the output voltage VOUT of the DC-DC converter 1000 does not have an output voltage ripple VOUT_RIPPLE when the input voltage VIN of the DC-DC converter 1000 changes.

[0109] The ripple cancellation circuit, DC-DC converter, method, chip, and electronic device provided herein can generate a fourth current, used to characterize the valley value of the inductor current in the DC-DC converter, based on a first current and a third current. The ripple cancellation circuit can also generate a first signal, used to determine the rising edge of a pulse-width modulation signal, based on the second current and the fourth current. Thus, the ripple cancellation circuit can generate a pulse-width modulation signal based on the first signal and a second signal, used to determine the switching period of the DC-DC converter. Because the third current varies with changes in the input voltage of the DC-DC converter, the fourth current also varies with changes in the input voltage of the DC-DC converter. Thus, the flip point of the first signal, i.e., the moment when the first signal flips from the first level to the second level, also varies with changes in the input voltage of the DC-DC converter, causing the rising edge of the pulse-width modulation signal to vary with changes in the input voltage of the DC-DC converter. Furthermore, the pulse-width modulation signal can vary with changes in the input voltage of the DC-DC converter, enabling the DC-DC converter to quickly respond to changes in the input voltage. Therefore, the DC-DC converter can eliminate the influence of input voltage on output voltage ripple, reduce output voltage ripple, ensure output voltage stability, and avoid screen ripples in electronic products using DC-DC converters.

[0110] Based on the description of the above embodiment, a possible implementation of the ripple elimination circuit 100 is exemplified. Figure 1 As shown, the ripple elimination circuit 100 may include: a fourth current output circuit 110 , a first comparator 120 , an oscillator 130 and a driver 140 .

[0111] The input end of the fourth current output circuit 110 is used to access the first current ICMP, the output end of the fourth current output circuit 110 is electrically connected to the first input end of the first comparator 120, the second input end of the first comparator 120 is used to access the second current I2, the output end of the first comparator 120 is electrically connected to the first input end of the driver 140, the output end of the oscillator 130 is electrically connected to the second input end of the driver 140, and the output end of the driver 140 is used to output the pulse width modulation signal PWM.

[0112] Among them, the fourth current output circuit 110, the first comparator 120, the oscillator 130 and the driver 140 can be set separately or integrated, and the embodiment of the present application does not make any specific limitation on this.

[0113] The input end of the fourth current output circuit 110 is the first input end of the ripple elimination circuit 100 , the second input end of the first comparator 120 is the second input end of the ripple elimination circuit 100 , and the output end of the driver 140 is the output end of the ripple elimination circuit 100 .

[0114] Exemplarily, the first input terminal of the first comparator 120 is a positive phase input terminal of the first comparator 120 , and the second input terminal of the first comparator 120 is a negative phase input terminal of the first comparator 120 .

[0115] The fourth current output circuit 110 may determine the current difference between the first current ICOMP and the third current I_DC as the fourth current I4 and transmit the fourth current I4 to the first comparator 120 so that the first comparator 120 can obtain the fourth current I4.

[0116] In this way, the first comparator 120 can compare the magnitude of the fourth current I4 with the second current I2 to obtain the first signal VAL_PULSE. In addition, the first comparator 120 can transmit the first signal VAL_PULSE to the driver 140 so that the driver 140 can obtain the first signal VAL_PULSE.

[0117] For example, when the fourth current I4 is greater than the second current I2, the first signal VAL_PULSE is at a high level. When the fourth current I4 is less than the second current I2, the first signal VAL_PULSE is at a low level. When the fourth current I4 is equal to the second current I2, the first signal VAL_PULSE flips from a low level to a high level. Figure 5 As shown, Figure 5 Shown Figure 1 Schematic diagram of the principle of the ripple elimination circuit generating the first signal. When the second current I2 drops to the fourth current I4, the first signal VAL_PULSE can flip from a low level to a high level.

[0118] The oscillator 130 may generate a second signal VOSC and transmit the second signal VOSC to the driver 140 so that the driver 140 may obtain the second signal VOSC.

[0119] Therefore, the driver 140 can generate the pulse width modulation signal PWM according to the first signal VAL_PULSE and the second signal VOSC, so that the ripple cancellation circuit 100 can generate the pulse width modulation signal PWM.

[0120] In summary, the fourth current output circuit can determine the current difference between the first current and the third current as the fourth current, and transmit the fourth current to the first comparator, so that the first comparator can obtain the fourth current. In this way, the first comparator can compare the magnitude of the fourth current with the second current to obtain a first signal, and transmit the first signal to the driver, so that the driver can obtain the first signal. The oscillator can generate a second signal and transmit the second signal to the driver, so that the driver can obtain the second signal. Consequently, the driver can generate a pulse-width modulated signal based on the first and second signals, allowing the ripple cancellation circuit to generate a pulse-width modulated signal.

[0121] Based on the description of the above embodiment, a possible implementation of the fourth current output circuit 110 is exemplified. Figure 1 As shown, the fourth current output circuit 110 may include: a first current source and a second current source.

[0122] The first end of the first current source is used to connect to the first current ICOMP, the second end of the first current source is electrically connected to the first end of the second current source, the second end of the second current source is grounded, and the first input end of the first comparator 120 is electrically connected between the second end of the first current source and the first end of the second current source.

[0123] The first end of the first current source is the input end of the fourth current output circuit 110 , and the output end of the fourth current output circuit 110 is located between the second end of the first current source and the first end of the second current source.

[0124] The first current source may output a first current ICOMP. The second current source may output a third current I_DC. Thus, the fourth current output circuit 110 may determine the current difference between the first current ICOMP and the third current I_DC as a fourth current I4 based on Kirchhoff's current law (i.e., KCL node current law).

[0125] In summary, the first current source can output the first current, the second current source can output the third current, and thus the fourth current output circuit can determine the current difference between the first current and the third current as the fourth current.

[0126] The following combination Figure 6 , Figure 6 This is a schematic diagram of the working principle of a ripple elimination circuit provided in one embodiment of the present application. The working principle of the ripple elimination circuit 100 is described in detail as follows:

[0127] like Figure 6As shown, the average inductor current Iavg (i.e., the center value of the inductor current IIND) is located at half the ripple of the inductor current I_ripple (i.e., 0.5I_ripple). In other words, the current difference between the average inductor current Iavg and the valley value I_VAL of the inductor current IIND is 0.5I_ripple.

[0128] The relationship between the first current ICOMP, the load current IO, and the average inductor current Iavg can be specifically expressed by formula (3):

[0129] ICOMP*K=Iavg=IO (3)

[0130] Wherein, ICOMP is the first current, Iavg is the average inductor current, IO is the load current, and K is the sampling coefficient.

[0131] Since the DC-DC converter 1000 operates in a constant-frequency mode, that is, the switching period Ts of the DC-DC converter 1000 is fixed, the DC-DC converter 1000 eliminates the effects of subharmonics on the DC-DC converter 1000 by introducing an additional ramp compensation current Islope, thereby improving the stability of the DC-DC converter 1000.

[0132] Typically, the DC-DC converter 1000 uses a valley comparison mode. Therefore, a ramp compensation current Islope is added during the decreasing phase of the inductor current IIND, ensuring that the slope of the ramp compensation current Islope is the same as the increasing slope of the inductor current IIND. Furthermore, by adding the ramp compensation current Islope, the ratio of the time required for the inductor current IIND to decrease relative to the switching period Ts can be adjusted, thereby adjusting the duty cycle of the DC-DC converter 1000. This eliminates the impact of subharmonics on the DC-DC converter 1000.

[0133] The valley comparison mode is also called the constant on-time control mode.

[0134] Based on this, due to the addition of the ramp compensation current Islope in the DC-DC converter 1000, the change IDetla between 0.5I_ripple and the ramp compensation current Islope can be specifically calculated using the following formula (4):

[0135] IDetla=0.5I_ripple-Islope (4)

[0136] Wherein, IDetla is the change between 0.5I_ripple and the ramp compensation current Islope, 0.5I_ripple is the half ripple of the inductor current ripple, and Islope is the ramp compensation current.

[0137] At the same time, since the waveform of the inductor current IIND is sawtooth-shaped and the inductor current IIND includes two half-ripples of the inductor current ripple I_ripple, one half-ripple of the inductor current ripple I_ripple is located above the average inductor current Iavg, and the other half-ripple of the inductor current ripple I_ripple is located below the average inductor current Iavg. Thus, the relationship between the first current ICOMP and the inductor current IIND can be specifically expressed by formula (5):

[0138] Iavg-0.5*I_ripple=ICOMP*K (5)

[0139] Wherein, ICOMP is the first current, K is the sampling coefficient, Iavg is the average inductor current, and I_ripple is the inductor current ripple.

[0140] Based on formula (5), it can be found that if the average inductor current Iavg is to be equal to the first current ICOMP, so that the first current ICOMP is equal to the load current IO, and the output voltage VOUT of the DC-DC converter 1000 is to avoid the generation of output voltage ripple VOUT_RIPPLE, it is necessary to eliminate the influence of 0.5I_ripple on the first current ICOMP. At the same time, due to the addition of the ramp compensation current Islope, the essence of the influence of the input voltage VIN of the DC-DC converter 1000 on the DC-DC converter 1000 is the influence on 0.5I_ripple and the ramp compensation current Islope.

[0141] Since the DC-DC converter 1000 can be a buck converter, a boost converter, or a buck-boost converter, the following describes the change IDetla caused by the input voltage VIN affecting the DC-DC converter 1000 when the DC-DC converter 1000 is in the buck converter, boost converter, and buck-boost converter modes, respectively. The contents are as follows:

[0142] When the DC-DC converter 1000 is a step-down transformer Buck, the inductor current ripple I_ripple is specifically calculated according to the following formula (6), and the ramp compensation current Islope is specifically calculated according to the following formula (7):

[0143] I_ripple=[(VIN-VOUT) / VIN)]*Ts*(-VOUT) / L (6)

[0144] Islope=0.5*[(VIN-VOUT) / VIN)]*Ts*(VIN-VOUT) / L (7)

[0145] Wherein, VIN is the input voltage of the DC-DC converter 1000 , VOUT is the output voltage of the DC-DC converter 1000 , Ts is the switching period of the DC-DC converter 1000 , and L is the inductance of the inductor IND in the DC-DC converter 1000 .

[0146] In addition, (VIN-VOUT) / VIN) is the duty cycle 1-D in the DC-DC converter 1000, (-VOUT) / L is the falling slope of the inductor current IIND, and (VIN-VOUT) / L is the rising slope of the inductor current IIND, where D is the duty cycle in the DC-DC converter 1000.

[0147] Thus, based on formula (4), formula (6) and formula (7), the change IDetla between 0.5I_ripple and the ramp compensation current Islope can be calculated according to the following formula (8):

[0148] IDetla=0.5*Ts*(VIN-VOUT) / L (8)

[0149] Wherein, IDetla is the variation between 0.5I_ripple and the ramp compensation current Islope, Ts is the switching period of the DC-DC converter 1000, VIN is the input voltage of the DC-DC converter 1000, and VOUT is the output voltage of the DC-DC converter 1000.

[0150] In the case where the DC-DC converter 1000 is a boost transformer Boost, the inductor current ripple I_ripple can be specifically calculated according to the following formula (9), and the ramp compensation current Islope can be specifically calculated according to the following formula (10):

[0151] I_ripple=(VIN / VOUT)*Ts*(VIN-VOUT) / L (9)

[0152] Islope=0.5*(VIN / VOUT)*Ts*VIN / L (10)

[0153] Wherein, VIN is the input voltage of the DC-DC converter 1000 , VOUT is the output voltage of the DC-DC converter 1000 , Ts is the switching period of the DC-DC converter 1000 , and L is the inductance of the inductor IND in the DC-DC converter 1000 .

[0154] In addition, (VIN-VOUT) / VIN) is the duty cycle D in the DC-DC converter 1000, (VIN-VOUT) / L is the falling slope of the inductor current IIND, and VIN / L is the rising slope of the inductor current IIND.

[0155] Thus, based on formula (4), formula (9) and formula (10), the change IDetla between 0.5I_ripple and the ramp compensation current Islope can be calculated according to the following formula (11):

[0156] IDetla=0.5*Ts*VIN / L (11)

[0157] Wherein, IDetla is the variation between 0.5I_ripple and the ramp compensation current Islope, Ts is the switching period of the DC-DC converter 1000, VIN is the input voltage of the DC-DC converter 1000, and VOUT is the output voltage of the DC-DC converter 1000.

[0158] In the case where the DC-DC converter 1000 is a buck-boost transformer, the inductor current ripple I_ripple can be calculated according to the following formula (12), and the slope compensation current Islope can be calculated according to the following formula (13):

[0159] I_ripple=VIN / (VIN+|VOUT|)*Ts*(-|VOUT|) / L (12)

[0160] Islope=0.5*VIN / (VIN+|VOUT|)*Ts*(VIN / L) (13)

[0161] Wherein, VIN is the input voltage of the DC-DC converter 1000 , VOUT is the output voltage of the DC-DC converter 1000 , Ts is the switching period of the DC-DC converter 1000 , and L is the inductance of the inductor IND in the DC-DC converter 1000 .

[0162] When the DC-DC converter 1000 is a buck-boost transformer, the output voltage VOUT of the DC-DC converter 1000 is a negative voltage.

[0163] In addition, VIN / (VIN+|VOUT|) is the duty cycle D of the DC-DC converter 1000 , (−|VOUT|) / L is the falling slope of the inductor current IIND, and VIN / L is the rising slope of the inductor current IIND.

[0164] Thus, based on formula (4), formula (12) and formula (13), the change IDetla between 0.5I_ripple and the ramp compensation current Islope can be calculated according to the following formula (14):

[0165] IDetla=|0.5*I_ripple-Islope|=0.5*Ts*VIN / L (14)

[0166] Wherein, IDetla is the variation between 0.5I_ripple and the ramp compensation current Islope, Ts is the switching period of the DC-DC converter 1000, VIN is the input voltage of the DC-DC converter 1000, and VOUT is the output voltage of the DC-DC converter 1000.

[0167] Based on the above description, it can be seen that when the relationship between the first current ICOMP and the inductor current IIND satisfies the following formula (15), the valley value IVAL of the inductor current IIND is an ideal valley value, so that the first current ICOMP is always equal to the load current IO. Therefore, the time when the signal VAL_PULSE switches from the first level to the second level also changes with the change of the input voltage VIN of the DC-DC converter 1000.

[0168] (ICOMP-IDetla)*K=Iavg-0.5I_ripple-Islope (15)

[0169] Wherein, ICOMP is the first current, IDetla is the change between 0.5I_ripple and the ramp compensation current Islope, K is the sampling coefficient, Iavg is the average inductor current, I_ripple is the inductor current ripple, and Islope is the ramp compensation current.

[0170] in, Figure 6 COMP_POINT represents the set of valley values ​​IVAL of the inductor current IIND.

[0171] Based on this, the ripple elimination circuit 100 in the embodiment of the present application introduces a third current I_DC, i.e., 0.5I_ripple-Islope, which can change with the input voltage VIN. This allows the valley value IVAL of the inductor current IIND to change with the input voltage VIN of the DC-DC converter 1000, and the moment when the first signal VAL_PULSE flips from the first level to the second level also changes with the change of the input voltage VIN of the DC-DC converter 1000.

[0172] Reference Figure 7-Figure 9 , Figure 7-Figure 9These are schematic diagrams of the structure of a DC-DC converter provided in one embodiment of the present application. Figure 7-Figure 9 As shown, the DC-DC converter 1000 may include: a first current output circuit 200 , a second current output circuit 300 , a voltage conversion circuit 400 and a ripple elimination circuit 100 .

[0173] The input end of the voltage conversion circuit 400 is used to receive the input voltage VIN of the DC-DC converter 1000, and the output end of the voltage conversion circuit 400 is used to output the output voltage VOUT of the DC-DC converter 1000. The output end of the voltage conversion circuit 400 is also electrically connected to the input end of the first current output circuit 200. The output end of the first current output circuit 200 is electrically connected to the first input end of the ripple elimination circuit 100. The input end of the second current output circuit 300 is used to collect the inductor current IIND of the inductor IND in the voltage conversion circuit 400. The output end of the second current output circuit 300 is electrically connected to the second input end of the ripple elimination circuit 100. The output end of the ripple elimination circuit 100 is electrically connected to the control end of the voltage conversion circuit 400.

[0174] The voltage conversion circuit 400 can convert the input voltage VIN of the DC-DC converter 1000 to obtain the output voltage VOUT of the DC-DC converter 1000. In addition, the voltage conversion circuit 400 can transmit the output voltage VOUT of the DC-DC converter 1000 to the first current output circuit 200, so that the first current output circuit 200 can obtain the output voltage VOUT of the DC-DC converter 1000.

[0175] In this manner, the first current output circuit 200 can generate the first current ICOMP based on the output voltage VOUT of the DC-DC converter 1000 and the reference voltage VREF. Furthermore, the first current output circuit 200 can transmit the first current ICOMP to the ripple cancellation circuit 100, so that the ripple cancellation circuit 100 can obtain the first current ICOMP.

[0176] The second current output circuit 300 can generate a second current I2 based on the collected inductor current IIND, and can transmit the second current I2 to the ripple elimination circuit 100 so that the ripple elimination circuit 100 can obtain the second current I2.

[0177] Thus, the ripple cancellation circuit 100 can generate a pulse-width modulation signal PWM based on the first current ICOMP, the second current I2, and the third current I_DC. Furthermore, the ripple cancellation circuit 100 can transmit the pulse-width modulation signal PWM to the voltage conversion circuit 400, so that the voltage conversion circuit 400 can use the pulse-width modulation signal PWM to control the high-side power transistor HS and the low-side power transistor LS in the voltage conversion circuit 400, thereby regulating and controlling the DC-DC converter 1000.

[0178] In summary, the voltage conversion circuit can convert the input voltage of the DC-DC converter to obtain the output voltage of the DC-DC converter. Furthermore, the voltage conversion circuit can transmit the output voltage of the DC-DC converter to the first current output circuit, allowing the first current output circuit to obtain the output voltage of the DC-DC converter. In this way, the first current output circuit can generate a first current based on the output voltage of the DC-DC converter and a reference voltage. Furthermore, the first current output circuit can transmit the first current to the ripple cancellation circuit, allowing the ripple cancellation circuit to obtain the first current. The second current output circuit can generate a second current based on the collected inductor current. Furthermore, the second current output circuit can transmit the second current to the ripple cancellation circuit, allowing the ripple cancellation circuit to obtain the second current. Consequently, the ripple cancellation circuit can transmit a pulse-width modulation signal to the voltage conversion circuit based on the first, second, and third currents. The voltage conversion circuit can use the pulse-width modulation signal to control the high-side power transistor and the low-side power transistor in the voltage conversion circuit, thereby regulating and controlling the DC-DC converter.

[0179] Based on the description of the above embodiment, a possible implementation of the first current output circuit 200 is exemplified. Figure 7 As shown, when the DC-DC converter 1000 is a buck converter, the first current output circuit 200 may include: a feedback circuit 210 and a second comparator 220 .

[0180] The input end of the feedback circuit 210 is electrically connected to the output end of the voltage conversion circuit 400, the output end of the feedback circuit 210 is electrically connected to the second input end of the second comparator 220, the first input end of the second comparator 220 is used to access the reference voltage VREF, and the output end of the second comparator 220 is electrically connected to the first input end of the ripple elimination circuit 100.

[0181] The input end of the feedback circuit 210 is the input end of the first current output circuit 200 , and the output end of the second comparator 220 is the output end of the first current output circuit 200 .

[0182] Exemplarily, the second input terminal of the second comparator 220 is a negative phase input terminal of the second comparator 220 , and the first input terminal of the second comparator 220 is a positive phase input terminal of the second comparator 220 .

[0183] The feedback circuit 210 can generate a feedback voltage VFB based on the output voltage VOUT of the DC-DC converter 1000. Furthermore, the feedback circuit 210 can transmit the feedback voltage VFB to the second comparator 220, so that the second comparator 220 can obtain the feedback voltage VFB. In this way, the second comparator 220 can generate a first current ICOMP based on the feedback voltage VFB and the reference voltage VREF. Consequently, the first current output circuit 200 can generate the first current ICOMP based on the output voltage VOUT of the DC-DC converter 1000 and the reference voltage VREF.

[0184] In summary, the feedback circuit can generate a feedback voltage based on the output voltage of the DC-DC converter. Furthermore, the feedback circuit can transmit the feedback voltage to the second comparator, allowing the second comparator to obtain the feedback voltage. In this way, the second comparator can generate a first current based on the feedback voltage and a reference voltage. Consequently, the first current output circuit can generate the first current based on the output voltage of the DC-DC converter and the reference voltage.

[0185] Based on the description of the above embodiment, a possible implementation of the voltage conversion circuit 400 is exemplified. Figure 7 As shown, when the DC-DC converter 1000 is a buck converter Buck, the voltage conversion circuit 400 may include: a high-side power transistor HS, a low-side power transistor LS and an inductor IND.

[0186] The drain terminal of the high-side power transistor HS is used to connect to the input voltage VIN, the source terminal of the high-side power transistor HS is electrically connected to the drain terminal of the low-side power transistor LS and the first terminal of the inductor IND respectively, the gate terminal of the high-side power transistor HS and the gate terminal of the low-side power transistor LS are both electrically connected to the output terminal of the ripple elimination circuit 100, the source terminal of the low-side power transistor LS is grounded, and the second terminal of the inductor IND is used to output the output voltage VOUT.

[0187] Among them, the drain end of the high-side power transistor HS is the input end of the voltage conversion circuit 400, the gate end of the high-side power transistor HS and the gate end of the low-side power transistor LS are both control ends of the voltage conversion circuit 400, and the second end of the inductor IND is the output end of the voltage conversion circuit 400.

[0188] When the inductor current IIND decreases to a valley value, the high-side power transistor HS is turned on, so that the inductor current IIND is in a rising stage.

[0189] The high-side power transistor HS is usually the upper transistor, and the low-side power transistor LS is usually the lower transistor. At the same time, the high-side power transistor HS is the control transistor, and the low-side power transistor LS is the synchronous transistor.

[0190] The high-side power transistor HS and the low-side power transistor LS can be field-effect transistors, such as metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs include N-type metal oxide semiconductor field effect transistors (NMOSFETs or NMOS transistors) and P-type metal oxide semiconductor field effect transistors (PMOSFETs or PMOS transistors). To simplify the description, this embodiment uses an example in which both the high-side power transistor HS and the low-side power transistor LS are enhancement-mode NMOS transistors.

[0191] Based on the description of the above embodiment, a possible implementation of the first current output circuit 200 is exemplified. Figure 8 and Figure 9 As shown, when the DC-DC converter 1000 is a boost converter Boost or a buck-boost converter Buck-Boost, the first current output circuit 200 may include: a feedback circuit 210 , a multiplier 230 and a second comparator 220 .

[0192] The input end of the feedback circuit 210 is electrically connected to the output end of the voltage conversion circuit 400, the output end of the feedback circuit 210 is electrically connected to the second input end of the second comparator 220, the first input end of the second comparator 220 is used to access the reference voltage VREF, the output end of the second comparator 220 is electrically connected to the first input end of the multiplier 230, the second input end of the multiplier 230 is used to access the input voltage VIN, the third input end of the multiplier 230 is used to access the output voltage VOUT, and the output end of the multiplier 230 is electrically connected to the first input end of the ripple elimination circuit 100.

[0193] The input end of the feedback circuit 210 is the input end of the first current output circuit 200 , and the output end of the multiplier 230 is the output end of the first current output circuit 200 .

[0194] Exemplarily, the second input terminal of the second comparator 220 is a negative phase input terminal of the second comparator 220 , and the first input terminal of the second comparator 220 is a positive phase input terminal of the second comparator 220 .

[0195] The feedback circuit 210 can generate a feedback voltage VFB based on the output voltage VOUT of the DC-DC converter 1000. Furthermore, the feedback circuit 210 can transmit the feedback voltage VFB to the second comparator 220, so that the second comparator 220 can obtain the feedback voltage VFB. In this way, the second comparator 220 can output an output signal of the second comparator 220 based on the feedback voltage VFB and the reference voltage VREF. In this way, the multiplier 230 amplifies the output signal of the second comparator 220 to obtain the first current ICOMP. Thus, the first current output circuit 200 can generate the first current ICOMP based on the output voltage VOUT of the DC-DC converter 1000 and the reference voltage VREF.

[0196] When the DC-DC converter 1000 is a boost converter Boost, the multiplier 230 amplifies the output signal of the second comparator 220 by a ratio equal to the ratio of the output voltage VOUT of the DC-DC converter 1000 to the input voltage VIN of the DC-DC converter 1000 .

[0197] The multiplier 230 dynamically tracks the changes in the output voltage VOUT of the DC-DC converter 1000 and the input voltage VIN of the DC-DC converter 1000 , so that the first current ICOMP is closer to the load current IO, and the accuracy of the DC-DC converter 1000 is higher.

[0198] In summary, the feedback circuit can generate a feedback voltage based on the output voltage of the DC-DC converter. Furthermore, the feedback circuit can transmit the feedback voltage to the second comparator, allowing the second comparator to obtain the feedback voltage. Thus, the second comparator can output an output signal of the second comparator based on the feedback voltage and a reference voltage. In this way, multiplication amplifies the output signal of the second comparator to obtain the first current. Thus, the first current output circuit can generate the first current based on the output voltage of the DC-DC converter and the reference voltage.

[0199] Based on the description of the above embodiment, a possible implementation of the voltage conversion circuit 400 is exemplified. Figure 8 As shown, when the DC-DC converter 1000 is a boost converter Boost, the voltage conversion circuit 400 may include: a high-side power transistor HS, a low-side power transistor LS and an inductor IND.

[0200] The source end of the high-side power transistor HS is used to output the output voltage VOUT, the drain end of the high-side power transistor HS is electrically connected to the first end of the inductor IND and the drain end of the low-side power transistor LS respectively, the gate end of the high-side power transistor HS and the gate end of the low-side power transistor LS are both electrically connected to the output end of the ripple elimination circuit 100, the second end of the inductor IND is used to access the input voltage VIN, and the source end of the low-side power transistor is grounded.

[0201] Among them, the source end of the high-side power transistor HS is the output end of the voltage conversion circuit 400, the second end of the inductor IND is the input end of the voltage conversion circuit 400, and the gate end of the high-side power transistor HS and the gate end of the low-side power transistor LS are both control ends of the voltage conversion circuit 400.

[0202] When the inductor current IIND decreases to a valley value, the low-side power transistor LS is turned on, so that the inductor current IIND is in a rising stage.

[0203] The high-side power transistor HS is usually the upper transistor, and the low-side power transistor LS is usually the lower transistor. In addition, the high-side power transistor HS is a synchronous transistor, and the low-side power transistor LS is a control transistor.

[0204] The high-side power transistor HS and the low-side power transistor LS can be field-effect transistors, such as metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs include N-type metal oxide semiconductor field effect transistors (NMOSFETs or NMOS transistors) and P-type metal oxide semiconductor field effect transistors (PMOSFETs or PMOS transistors). To simplify the description, this embodiment uses an example in which both the high-side power transistor HS and the low-side power transistor LS are enhancement-mode NMOS transistors.

[0205] Based on the description of the above embodiment, a possible implementation of the voltage conversion circuit 400 is exemplified. Figure 9 As shown, when the DC-DC converter 1000 is a Buck-Boost converter, the voltage conversion circuit 400 may include: a high-side power transistor HS, a low-side power transistor LS and an inductor IND.

[0206] The drain terminal of the high-side power transistor HS is used to access the input voltage VIN, the source terminal of the high-side power transistor HS is electrically connected to the first terminal of the inductor IND and the drain terminal of the low-side power transistor LS respectively, the gate terminal of the high-side power transistor HS and the gate terminal of the low-side power transistor LS are both electrically connected to the output terminal of the ripple elimination circuit 100, the source terminal of the low-side power transistor is used to output the output voltage VOUT, and the second terminal of the inductor IND is grounded.

[0207] Among them, the source end of the high-side power transistor HS is the input end of the voltage conversion circuit 400, the source end of the low-side power transistor is the output end of the voltage conversion circuit 400, and the gate end of the high-side power transistor HS and the gate end of the low-side power transistor LS are both control ends of the voltage conversion circuit 400.

[0208] When the inductor current IIND decreases to a valley value, the high-side power transistor HS is turned on, so that the inductor current IIND is in a rising stage.

[0209] The high-side power transistor HS is usually the upper transistor, and the low-side power transistor LS is usually the lower transistor. In addition, the high-side power transistor HS is a synchronous transistor, and the low-side power transistor LS is a control transistor.

[0210] The high-side power transistor HS and the low-side power transistor LS can be field-effect transistors, such as metal oxide semiconductor field effect transistors (MOSFETs). MOSFETs include N-type metal oxide semiconductor field effect transistors (NMOSFETs or NMOS transistors) and P-type metal oxide semiconductor field effect transistors (PMOSFETs or PMOS transistors). To simplify the description, this embodiment uses the high-side power transistor HS and the low-side power transistor L as examples, both of which are enhancement-mode NMOS transistors.

[0211] Based on the description of the above embodiment, a possible implementation of the feedback circuit 210 is exemplified. Figure 7-Figure 9 As shown, the feedback circuit 210 may include a first resistor R1 and a second resistor R2.

[0212] The first end of the first resistor R1 is electrically connected to the output end of the voltage conversion circuit 400, the first end of the first resistor R1 is electrically connected to the first end of the second resistor R2, the second input end of the second comparator 220 is electrically connected between the first end of the first resistor R1 and the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0213] The first end of the first resistor R1 is the input end of the feedback circuit 210 , and the output end of the feedback circuit 210 is located between the first end of the first resistor R1 and the first end of the second resistor R2 .

[0214] The output voltage VOUT of the DC-DC converter 1000 is divided by the first resistor R1 and the second resistor R2 to obtain the feedback voltage VFB. Thus, the feedback circuit 210 can generate the feedback voltage VFB according to the output voltage VOUT of the DC-DC converter 1000.

[0215] In summary, the output voltage of the DC-DC converter is divided by the first resistor and the second resistor to obtain the feedback voltage. Thus, the feedback circuit can generate the feedback voltage according to the output voltage of the DC-DC converter.

[0216] Figure 7 and Figure 8 The DCR in the figure represents the inductive reactance of the inductor IND.

[0217] The DC-DC converter 1000 provided in the embodiment of the present application has the same beneficial effects as the ripple elimination circuit 100 provided in the embodiment of the present application, and will not be described in detail here.

[0218] An embodiment of the present application further provides a chip, including: a ripple elimination circuit 100 , or a DC-DC converter 1000 .

[0219] The ripple elimination circuit 100 and other circuits or modules in the DC-DC converter 1000 except the ripple elimination circuit 100 may be integrated into one chip or into different chips, which is not specifically limited in the embodiment of the present application.

[0220] The chip provided in the embodiment of the present application has the same beneficial effects as the ripple elimination circuit 100 provided in the embodiment of the present application, and will not be described in detail here.

[0221] An embodiment of the present application also provides an electronic device, including: a chip.

[0222] In this application, electronic devices may include but are not limited to: tablet computers, routers, industrial robots and televisions.

[0223] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be repeated here.

[0224] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A ripple elimination circuit, characterized in that: The ripple elimination circuit is applied to a DC-DC converter; The first input terminal of the ripple elimination circuit is used to receive a first current, which is used to represent the load current of the DC-DC converter; the second input terminal of the ripple elimination circuit is used to receive a second current, which is used to represent the change of the inductor current in the DC-DC converter; the output terminal of the ripple elimination circuit is used to output a pulse width modulation signal, which is used to control the conduction or shutdown of the power transistor in the DC-DC converter; The ripple elimination circuit is configured to obtain a fourth current based on the first current and the third current, wherein the third current varies in response to a change in an input voltage of the DC-DC converter, and the fourth current is configured to represent a valley value of an inductor current in the DC-DC converter; The ripple elimination circuit is further configured to obtain a first signal according to the second current and the fourth current, wherein the first signal is used to determine a rising edge of the pulse width modulation signal; The ripple elimination circuit is further configured to generate the pulse width modulation signal according to the first signal and the second signal, wherein the second signal is used to determine a switching period of the DC-DC converter.

2. The circuit according to claim 1, characterized in that The ripple elimination circuit includes: a fourth current output circuit, a first comparator, an oscillator and a driver; The input end of the fourth current output circuit is used to receive the first current, the output end of the fourth current output circuit is electrically connected to the first input end of the first comparator, the second input end of the first comparator is used to receive the second current, the output end of the first comparator is electrically connected to the first input end of the driver, the output end of the oscillator is electrically connected to the second input end of the driver, and the output end of the driver is used to output the pulse width modulation signal; the fourth current output circuit is configured to determine a current difference between the first current and the third current as the fourth current, and transmit the fourth current to the first comparator; The first comparator is configured to compare the magnitude of the fourth current and the second current to obtain the first signal, and transmit the first signal to the driver; The oscillator is configured to generate the second signal and transmit the second signal to the driver; The driver is configured to generate the pulse width modulation signal according to the first signal and the second signal.

3. The circuit according to claim 2, characterized in that The fourth current output circuit includes: a first current source and a second current source; A first terminal of the first current source is used to receive a first current, a second terminal of the first current source is electrically connected to a first terminal of the second current source, a second terminal of the second current source is grounded, and a first input terminal of the first comparator is electrically connected between the second terminal of the first current source and the first terminal of the second current source; The first current source is configured to output the first current; The second current source is configured to output the third current.

4. The circuit according to claim 2, characterized in that The second current is calculated according to the following formula 1: I2=Iavg-(A*I_ripple-Islope) Formula 1 Wherein, I2 is the second current, Iavg is the average inductor current, A is the inductor current ripple coefficient, I_ripple is the inductor current ripple, Islope is the ramp compensation current, and the slope of the ramp compensation current is the same as the rising slope of the inductor current.

5. The circuit according to claim 2, characterized in that The third current is calculated according to the following formula 2: I_DC=A*I_ripple-Islope formula 2 Wherein, I_DC is the third current, A is the inductor current ripple coefficient, I_ripple is the inductor current ripple, Islope is the ramp compensation current, and the slope of the ramp compensation current is the same as the rising slope of the inductor current.

6. The circuit according to claim 4 or 5, characterized in that When the DC-DC converter is a buck converter, the inductor current ripple is calculated according to the following formula 3, and the ramp compensation current is calculated according to the following formula 4: I_ripple=[(VIN-VOUT) / VIN)]*Ts*(-VOUT) / LFormula 3 Islope=0.5*[(VIN-VOUT) / VIN)]*Ts*(VIN-VOUT) / L Formula 4 Wherein, VIN is the input voltage of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, Ts is the switching period of the DC-DC converter, and L is the inductance of the inductor in the DC-DC converter.

7. The circuit according to claim 4 or 5, characterized in that When the DC-DC converter is a boost converter, the inductor current ripple is calculated according to the following formula 5, and the ramp compensation current is calculated according to the following formula 6: I_ripple=(VIN / VOUT)*Ts*(VIN-VOUT) / LFormula 5 Islope=0.5*(VIN / VOUT)*Ts*VIN / L Formula 6 Wherein, VIN is the input voltage of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, Ts is the switching period of the DC-DC converter, and L is the inductance of the inductor in the DC-DC converter.

8. The circuit according to claim 4 or 5, characterized in that When the DC-DC converter is a buck-boost converter, the inductor current ripple is calculated according to the following formula 7, and the ramp compensation current is calculated according to the following formula 8: I_ripple=VIN / (VIN+|VOUT|)*Ts*(-|VOUT|) / LFormula 7 Islope=0.5*VIN / (VIN+|VOUT|)*Ts*(VIN / L) Formula 8 Wherein, VIN is the input voltage of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, Ts is the switching period of the DC-DC converter, and L is the inductance of the inductor in the DC-DC converter.

9. The circuit according to claim 4 or 5, characterized in that The inductor current ripple factor is 0.

5.

10. A DC-DC converter, characterized in that: The DC-DC converter comprises: a first current output circuit, a second current output circuit, a voltage conversion circuit and a ripple elimination circuit according to any one of claims 1 to 9; The input end of the voltage conversion circuit is used to connect to the input voltage of the DC-DC converter, and the output end of the voltage conversion circuit is used to output the output voltage of the DC-DC converter. The output end of the voltage conversion circuit is also electrically connected to the input end of the first current output circuit, and the output end of the first current output circuit is electrically connected to the first input end of the ripple elimination circuit. The input end of the second current output circuit is used to collect the inductor current of the inductor in the voltage conversion circuit, the output end of the second current output circuit is electrically connected to the second input end of the ripple elimination circuit, and the output end of the ripple elimination circuit is electrically connected to the control end of the voltage conversion circuit.

11. The DC-DC converter according to claim 10, wherein: When the DC-DC converter is a buck converter, the first current output circuit includes: a feedback circuit and a second comparator; The input end of the feedback circuit is electrically connected to the output end of the voltage conversion circuit, the output end of the feedback circuit is electrically connected to the second input end of the second comparator, the first input end of the second comparator is used to access the reference voltage, and the output end of the second comparator is electrically connected to the first input end of the ripple elimination circuit.

12. The DC-DC converter according to claim 10, wherein: When the DC-DC converter is a boost converter or a buck-boost converter, the first current output circuit includes: a feedback circuit, a multiplier, and a second comparator; The input end of the feedback circuit is electrically connected to the output end of the voltage conversion circuit, the output end of the feedback circuit is electrically connected to the second input end of the second comparator, the first input end of the second comparator is used to access the reference voltage, the output end of the second comparator is electrically connected to the first input end of the multiplier, the second input end of the multiplier is used to access the input voltage, the third input end of the multiplier is used to access the output voltage, and the output end of the multiplier is electrically connected to the first input end of the ripple elimination circuit.

13. The DC-DC converter according to claim 10, wherein: The voltage conversion circuit includes: a high-side power transistor, a low-side power transistor and an inductor; When the DC-DC converter is a buck converter, the drain terminal of the high-side power transistor is used to access the input voltage, the source terminal of the high-side power transistor is electrically connected to the drain terminal of the low-side power transistor and the first end of the inductor respectively, the gate terminal of the high-side power transistor and the gate terminal of the low-side power transistor are both electrically connected to the output terminal of the ripple elimination circuit, the source terminal of the low-side power transistor is grounded, and the second end of the inductor is used to output the output voltage; Alternatively, when the DC-DC converter is a boost converter, the source terminal of the high-side power transistor is used to output the output voltage, the drain terminal of the high-side power transistor is electrically connected to the first terminal of the inductor and the drain terminal of the low-side power transistor respectively, the gate terminal of the high-side power transistor and the gate terminal of the low-side power transistor are both electrically connected to the output terminal of the ripple elimination circuit, the second terminal of the inductor is used to access the input voltage, and the source terminal of the low-side power transistor is grounded; Alternatively, when the DC-DC converter is a buck-boost converter, the drain terminal of the high-side power transistor is used to access the input voltage, the source terminal of the high-side power transistor is electrically connected to the first end of the inductor and the drain terminal of the low-side power transistor respectively, the gate terminal of the high-side power transistor and the gate terminal of the low-side power transistor are both electrically connected to the output terminal of the ripple elimination circuit, the source terminal of the low-side power transistor is used to output the output voltage, and the second end of the inductor is grounded.

14. A ripple elimination method, characterized in that: The method is performed by a ripple elimination circuit, which is applied to a DC-DC converter. A first input terminal of the ripple elimination circuit is used to receive a first current, which is used to represent the load current of the DC-DC converter. A second input terminal of the ripple elimination circuit is used to receive a second current, which is used to represent the change of the inductor current in the DC-DC converter. An output terminal of the ripple elimination circuit is used to output a pulse width modulation signal, which is used to control the on or off of a power transistor in the DC-DC converter. The method includes: The ripple elimination circuit obtains a fourth current based on the first current and the third current, wherein the third current changes in accordance with the input voltage of the DC-DC converter, and the fourth current is used to represent a valley value of the inductor current in the DC-DC converter; The ripple elimination circuit obtains a first signal according to the second current and the fourth current, wherein the first signal is used to determine a rising edge of the pulse width modulation signal; The ripple elimination circuit generates the pulse width modulation signal according to the first signal and the second signal, and the second signal is used to determine the switching period of the DC-DC converter.

15. A chip, characterized in that: include: The ripple cancellation circuit according to any one of claims 1 to 9, or the DC-DC converter according to any one of claims 10 to 13.

16. An electronic device, characterized in that: include: The chip as claimed in claim 15.

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