Single-phase immersion liquid cooling heat dissipation device, control method and control system

Abstract

The invention relates to the technical field of immersed liquid cooling, and particularly provides a single-phase immersed liquid cooling heat dissipation device, a control method and a control system.The method comprises the steps that a heating area of a chip is divided, and a heat source area and a non-heat source area are obtained; different arrangement strategies are adopted for the heat source area and the non-heat source area, and jet devices are arranged; a plurality of temperature sensors are arranged on the surface of the chip, the cold fluid inlet and the hot fluid outlet; receiving temperature data sent by the temperature sensor, filtering the temperature data, and eliminating instantaneous interference signals; meanwhile, calculating a temperature standard deviation reflecting temperature difference uniformity on the surface of the chip and judging whether the temperature exceeds a highest temperature value of a threshold value or not; when the highest temperature value does not exceed the threshold value, heat dissipation of the cold fluid is executed according to a first heat dissipation strategy; and when the highest temperature value exceeds the threshold value, heat dissipation of the cold fluid is executed according to a second heat dissipation strategy, and meanwhile the pulse frequency of the jet device variable frequency pump is adjusted according to the temperature difference standard deviation. According to the invention, Pareto optimization of heat dissipation efficiency and energy consumption is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of immersion liquid cooling, and in particular to a single-phase immersion liquid cooling heat dissipation device, a control method and a control system. Background Art

[0002] With the prevalence of AI chips and high-power CPUs / GPUs, chip heat flux densities have exceeded 100W / cm², making traditional air cooling and single liquid cooling technologies increasingly ineffective. Air cooling, limited by convection efficiency, cannot cope with high heat flux densities. Traditional cold plate liquid cooling suffers from thick thermal boundary layers and large temperature differences, while standard immersion liquid cooling wastes cooling capacity due to the mixing of hot and cold fluids and struggles to adapt to dynamically changing computing loads. Existing liquid cooling solutions face increasingly pronounced structural bottlenecks: Unidirectional flow causes hot fluid to stagnate at the top of the cabinet, forming a "heat island" and resulting in less than 80% cooling capacity utilization. Rigid control logic cannot adapt to chip load fluctuations, resulting in redundant energy consumption during light loads and insufficient heat dissipation during heavy loads. These issues directly contribute to the high power usage effectiveness (PUE) of traditional systems, and the single cabinet power limit is limited to 80kW, making it unable to support the demands of next-generation 150kW-class high-density cabinets.

[0003] Prior art one, Chinese patent application number 202411457137.X, discloses an immersion liquid cooling heat dissipation circulation control system, which consists of an electronic equipment cooling cabinet, a heat exchanger, an adaptive variable frequency pump, a flow sensor, a temperature sensor, a pressure sensor, an adaptive regulating valve, an outdoor heat dissipation unit, and a system master control unit. By automatically detecting the outdoor ambient temperature and the immersion liquid temperature, the controller adjusts the adaptive variable frequency pump, the outdoor heat dissipation unit, and the adaptive regulating valve, ultimately achieving a constant temperature of the electronic equipment within a controllable range. Although controlling the flow rate of the electronic equipment deployment cavity, the overall flow rate on the electronic equipment deployment side, and the flow rate of the outdoor heat dissipation unit can ensure the normal operation and extend the service life of electronic equipment with different heat generation, while also improving energy utilization efficiency, the low heat dissipation efficiency caused by uniform cooling across the entire area makes it difficult to address local hot spots on the chip using global flow control, and passive temperature control is limited.

[0004] Prior art 2, Chinese patent application number 202510015122.6, discloses a propeller-assisted immersion liquid cooling device for data center cabinets. This device includes the structural design of a heat sink and propeller, as well as their combined design and layout variations. The heat sink is used to increase the heat dissipation area of ​​the chip. The propeller is arranged in front of or behind the heat sink's fins. The propeller generates suction and thrust in the coolant, accelerating the local flow field and achieving enhanced heat dissipation. To address different heat dissipation, noise, vibration, and energy consumption requirements, the present invention includes various propeller and heat sink design and assembly methods. Design parameters include: the overall number of heat sink-propeller combinations in the server, the relative positions of the propeller and heat sink, the structural design of the propeller and heat sink, and the number of propellers matched to a single heat sink. While single-phase immersion liquid cooling offers higher heat dissipation capacity and expands its application in high-power chip server cooling, it is easy to install and does not require significant server modifications. However, the mechanical vibration of the propeller interferes with the chip, and the reliance on the physical propeller to generate forced convection creates the risk of vibration and noise from moving parts.

[0005] Prior art three, Chinese patent application number 202410781037.6, discloses an immersion liquid-cooled cabinet with uniform heat dissipation. The cabinet comprises a cabinet and vents arranged linearly and equidistantly on the top of the cabinet. A water tank is fixedly connected to the bottom of the cabinet, and heating elements are symmetrically and equidistantly fixed to the interior of the cabinet. A float is provided to monitor the coolant level inside the cabinet in real time. When the liquid level is too low, the float floats under the action of buoyancy, and the upward movement of the float causes a rotating plate to rotate, connecting the circular hole on the surface of the rotating plate to the connection port. While this structure not only automatically monitors and replenishes the coolant content in the cabinet, but also ensures that a sufficient amount of coolant is always maintained inside the cabinet, thereby ensuring the normal operation of the cooling system, this structure also prevents coolant loss due to evaporation, which can lead to reduced heat exchange efficiency and further damage to electronic components under high temperatures. However, the equidistant arrangement cannot cope with uneven heating, and the liquid level control function is a single function, monitoring the liquid level.

[0006] Currently, existing technologies 1, 2, and 3 suffer from poor heat dissipation performance, energy efficiency, and system reliability across multiple dimensions. Traditional natural convection heat dissipation has an upper limit, resulting in low heat dissipation power per cabinet, and a heat dissipation bottleneck in high-density computing scenarios. Therefore, the present invention provides a single-phase immersion liquid cooling device, control method, and control system. Summary of the Invention

[0007] In order to achieve the above object, the present invention adopts the following technical solutions: In one aspect of the present invention, a single-phase immersion liquid cooling heat dissipation control method is provided, comprising the following steps: The chip's heat-generating area is divided into heat source and non-heat source areas. Different layout strategies are used for the heat source and non-heat source areas, and ejectors are arranged. Several temperature sensors are placed on the chip surface, cold fluid inlet, and hot fluid outlet. Receive temperature data from the temperature sensor, filter the temperature data, and remove instantaneous interference signals; at the same time, calculate the temperature standard deviation on the chip surface to reflect the temperature uniformity and determine whether the maximum temperature value exceeds the threshold; When the maximum temperature value does not exceed the threshold, the cooling of the cold fluid is performed according to the first cooling strategy; when the maximum temperature value exceeds the threshold, the cooling of the cold fluid is performed according to the second cooling strategy, and the pulse frequency of the ejector variable frequency pump is adjusted according to the temperature difference standard deviation.

[0008] In an optional embodiment, the process of calculating the temperature standard deviation reflecting the temperature uniformity of the chip surface and determining whether the maximum temperature value exceeds the threshold value includes the following steps: The physical layout characteristics of the ejector arrays in the heat source area and the non-heat source area are used to construct a regional weight template, and the original temperature data is filtered by inertial delay in the spatial domain. The spatially filtered data stream is fed into a heat flow phase separator to separate the pulse temperature component reflecting the transient impact of the heat source area and the base temperature component representing the slow change of the non-heat source area. The pulse temperature component generates the maximum temperature value through peak detection, and the base temperature component outputs the temperature standard deviation through regional weighted variance calculation.

[0009] In an optional implementation, the process of performing spatial domain inertial delay filtering on the raw temperature data includes the following steps: The spatial distribution topology of the 2×2 array nozzles in the heat source area and the 1×1 array nozzles in the non-heat source area is extracted to generate a heat capacity network diagram with the ejectors as nodes. Based on the material heat conduction time lag between adjacent nodes in the heat capacity network diagram, the dynamic heat capacity weight of the ejector coverage area is calculated; The dynamic heat capacity weight is loaded into the spatial coordinates of the temperature sensor, an inertial delay operator is constructed, and thermodynamic intrinsic filtering is performed on the raw temperature data.

[0010] In an optional implementation, the process of constructing the inertial delay operator includes the following steps: The dynamic weight value of the heat source area is mapped to a high-density momentum factor, and the weight of the non-heat source area is mapped to a low-density momentum factor. The position matrix composed of the high-density momentum factor and the low-density momentum factor and the three-dimensional coordinates of the temperature sensor is condensed and reduced to generate a heat flux acceleration field with the sensor as the focus. The heat flux acceleration field is projected on the chip surface in the normal direction to form a thermal inertia potential field distribution with a physical gradient. Directed Fourier slice decomposition of the thermal inertia potential field is performed along the principal orientation of the material lattice in the divided heat source area. The fundamental conduction mode with an energy share greater than 85% in the directed Fourier slice is extracted, and its wave vector direction is defined as the dominant heat transfer axis. The phase delay of the fundamental conduction mode is encoded as a three-dimensional time-delay eigenvector. The specific heat capacity tensor is projected along the principal axis in the direction of the time-delay eigenvector to obtain a direction-sensitive equivalent specific heat capacity scalar. The equivalent specific heat capacity scalar is multiplied by the modulus of the eigenvector to generate the intrinsic delay time constant of the sensor position. An asymmetric exponential decay kernel is constructed with the intrinsic delay time constant as the variance. The kernel width is 5ms in the heat source area and 20ms in the non-heat source area. The raw temperature data stream is grouped by sensor space and injected with the corresponding asymmetric exponential decay kernel. The convolution process introduces a heat flow continuity constraint: the output data satisfies the conservation of the total heat capacity of the chip. The filtered temperature field retains the transient characteristics of the heat source area while smoothing the base fluctuations in the non-heat source area.

[0011] In an optional embodiment, the process of outputting the temperature standard deviation of the base temperature component through regional weighted variance calculation includes the following steps: The spatial distribution of the heat core network units defined by the pulse temperature component input triggers the heat capacity accumulation effect within the units and generates a thermal shock envelope in the time domain. The thermal shock envelope then filters out the effective temperature extreme points at the actual heat core node locations through the dynamic heat capacity threshold. The effective temperature extreme points are sorted by heat flux momentum weighting to output the highest temperature value; the base temperature component is loaded with the ejector spacing parameter to construct the heat diffusion unevenness matrix; The thermal diffusion nonuniformity matrix and the dynamic heat capacity weight are tensor-contracted to generate the regional thermodynamic imbalance. The regional thermodynamic imbalance is decomposed by intrinsic orthogonal decomposition, and the standard deviation of the main mode amplitude is extracted as the temperature standard deviation.

[0012] In an optional embodiment, the process of extracting the standard deviation of the main modal amplitude as the temperature standard deviation includes the following steps: The regional thermodynamic imbalance is input into the thermal core network topology to stimulate the thermal flow coupling oscillation between network nodes. The thermal flow coupling oscillation forms an intrinsic thermal disturbance spectrum under the constraint of the phonon dispersion relation of the chip substrate material. The dominant mode with an energy share of more than 90% in the intrinsic thermal disturbance spectrum is extracted, and its amplitude time series is normalized by heat capacity; The heat capacity normalized amplitude series is subjected to thermal momentum weighted standard deviation calculation to output the temperature standard deviation.

[0013] In an optional embodiment, the process of calculating the heat capacity normalized amplitude sequence by thermal momentum weighted standard deviation comprises the following steps: The heat capacity normalized amplitude sequence is input into the spatial energy distributor of the heat core network unit to generate the thermal fluctuation displacement field within the unit; the thermal fluctuation displacement field is integrated with the dynamic heat capacity weight by thermal momentum moment to output the heat flow shock intensity spectrum; The heat flux shock intensity spectrum is converted into standard thermal disturbance power density through relaxation time scale transformation; The standard thermal disturbance power density is integrated within the ejector control volume to generate the temperature standard deviation.

[0014] In one optional embodiment, the first heat dissipation strategy involves first delivering low-temperature coolant from an external cold source to a cold fluid buffer zone on top of the cabinet. The cold fluid buffer zone is located in the middle above the isolation plate and is physically separated from the hot fluid zone by a longitudinal partition. At this point, the variable frequency pump of the ejector is activated, creating a negative pressure in the pipe. Simultaneously, the cold fluid, driven by gravitational potential energy, flows through the guide channel on the isolation plate and the dedicated connecting pipe to the ejector, completing the initial delivery of the cold fluid. The second heat dissipation strategy adds the adjustment of the ejector's pulse valve at a preset frequency to the first heat dissipation strategy, and obliquely sprays the jet onto the chip surface through the micro-nozzle array; the high-speed pulse jet directly tears the thermal boundary layer around the chip, allowing the coolant to quickly absorb the chip's heat and convert it into a thermal fluid.

[0015] Another aspect of the present invention provides a single-phase immersion liquid cooling heat dissipation control system for implementing the single-phase immersion liquid cooling heat dissipation control method, comprising: The area division module is used to divide the heat generation area of ​​the chip into heat source area and non-heat source area; different layout strategies are adopted for the heat source area and non-heat source area, and ejectors are arranged; and several temperature sensors are arranged on the chip surface, cold fluid inlet and hot fluid outlet; The heat source area is arranged with a 2×2 array of nozzles with a spacing of 5 mm; the non-heat source area is arranged with a 1×1 array of nozzles with a spacing of 20 mm; The temperature calculation module is used to receive temperature data sent by the temperature sensor, filter the temperature data, and remove instantaneous interference signals; at the same time, it calculates the temperature standard deviation on the chip surface to reflect the temperature uniformity and determines whether the maximum temperature value exceeds the threshold; a strategy execution module, configured to, when the maximum temperature value does not exceed a threshold, execute the cooling of the cold fluid according to a first cooling strategy; and when the maximum temperature value exceeds the threshold, execute the cooling of the cold fluid according to a second cooling strategy, while adjusting the pulse frequency of the ejector variable frequency pump according to the standard deviation of the temperature difference; The first heat dissipation strategy involves initially delivering low-temperature coolant from an external cold source to a cold fluid buffer zone on top of the cabinet. This buffer zone is located in the middle of the isolation plate and is physically separated from the hot fluid zone by a longitudinal partition. At this point, the ejector's variable frequency pump activates, creating negative pressure in the pipe. Simultaneously, the cold fluid, driven by gravitational potential energy, flows through the guide channel on the isolation plate and dedicated connecting pipes to the ejector, completing the initial delivery of the cold fluid. The second heat dissipation strategy adds the adjustment of the ejector's pulse valve at a preset frequency to the first heat dissipation strategy, and obliquely sprays the jet onto the chip surface through the micro-nozzle array; the high-speed pulse jet directly tears the thermal boundary layer around the chip, allowing the coolant to quickly absorb the chip's heat and convert it into a thermal fluid.

[0016] Another aspect of the present invention provides a single-phase immersion liquid cooling heat dissipation control device for implementing the single-phase immersion liquid cooling heat dissipation control method, comprising: a V-shaped guide fin, a coolant buffer zone infusion pipeline, a trumpet-shaped guide hole, a first guide pipe, an ejector, a cabinet, a server chip, an isolation plate, and a second guide pipe; Among them, V-shaped guide fins are welded on both sides of the inner top of the cabinet, and a coolant buffer infusion pipeline is embedded in the center of the top of the cabinet; at least two ejectors are installed at the bottom of the coolant buffer infusion pipeline, and a first guide pipe is installed on each side of the ejector, and a trumpet-shaped guide hole is installed on the top of the first guide pipe; the server chip is placed in the middle position between the first guide pipes, and the trumpet-shaped guide hole is embedded in the isolation plate, and the lower end of the isolation plate is connected to multiple second guide pipes.

[0017] The present invention significantly and multi-dimensionally covers heat dissipation performance, energy efficiency performance and system reliability. In terms of heat dissipation capacity, it breaks through the heat dissipation limit of traditional natural convection, significantly improves the heat dissipation power of a single cabinet, and the heat flux density on the chip surface can easily adapt to high heat flux density devices such as AI chips and high-power GPUs, solving the heat dissipation bottleneck in high-density computing scenarios. The energy efficiency advantage is outstanding. The physical separation of the isolation plate avoids the waste of cold caused by the mixing of cold and hot fluids, and the utilization rate of cold capacity is significantly improved. At the same time, the intelligent control system dynamically adjusts the jet parameters according to the chip load, reducing energy consumption redundancy under light load. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 This is a flow chart of the single-phase immersion liquid cooling heat dissipation control method provided in Example 1 of the present invention; Figure 2 This is a schematic diagram of the single-phase immersion liquid cooling heat dissipation control method provided in Example 1 of the present invention; Figure 3 This is a diagram of the process of dividing the heat generation area of ​​a chip provided in Example 2 of the present invention; Figure 4 This is a process diagram for calculating the temperature standard deviation reflecting the temperature uniformity of the chip surface and determining whether the maximum temperature value exceeds the threshold value provided in Example 5 of the present invention; Figure 5 This is a schematic structural diagram of a single-phase immersion liquid cooling device provided in Example 14 of the present invention; Figure 6 This is a schematic structural diagram of the isolation plate provided in Example 14 of the present invention; Figure 7 This is a working principle diagram of the single-phase immersion liquid cooling heat dissipation device provided in Example 14 of the present invention; Figure 8 A block diagram of the electronic device provided by the present invention; Figure 9 A block diagram of a computer-readable storage medium provided by the present invention; Figure numerals: 1. V-shaped guide fin; 2. Coolant buffer infusion pipeline; 3. Trumpet-shaped guide hole; 4. First guide tube; 5. Ejector; 6. Cabinet; 7. Server chip; 8. Isolation plate; 9. Second guide tube; 10. Central processing unit / microprocessor / main control chip; 11. Storage medium; 12. Data bus; 13. Input / output bus / external bus / device bus; 14. Display; 15. Input / output device; 16. Computer-readable instructions; 17. Non-temporary computer-readable storage medium. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0020] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified with "first," "second," etc., may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] In the present invention, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated one; or, "connection" can be a direct connection or an indirect connection through an intermediate medium. In addition, unless otherwise clearly specified and limited, the term "coupling" should be understood in a broad sense. For example, "coupling" can be a direct electrical connection, such as physical contact and electrical conduction between two components, or it can be understood as the electrical connection between different components in a circuit structure through a physical line that can transmit electrical signals, such as printed circuit board (PCB) copper foil or wire, so as to transmit electrical signals; or, "coupling" can be an indirect electrical connection between two components through an intermediate medium; or, "coupling" can be an electrical connection between two components in an airless / non-contact manner, such as electrical connection between two components using capacitive coupling to transmit electrical signals.

[0022] In an embodiment of the present invention, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0023] Example 1: Figure 1 As shown, an embodiment of the present invention provides a single-phase immersion liquid cooling heat dissipation control method, comprising the following steps: Step S100: Divide the heat generation area of ​​the chip into heat source areas and non-heat source areas; use different layout strategies for the heat source areas and non-heat source areas to arrange ejectors; and arrange a number of temperature sensors on the chip surface, cold fluid inlet, and hot fluid outlet. The heat source area is arranged with a 2×2 array of nozzles with a spacing of 5 mm; the non-heat source area is arranged with a 1×1 array of nozzles with a spacing of 20 mm; Step S200: Receive temperature data sent by the temperature sensor, filter the temperature data, and remove instantaneous interference signals; calculate the temperature standard deviation of the chip surface reflecting the temperature uniformity and determine whether the maximum temperature value exceeds the threshold; Step S300: When the maximum temperature value does not exceed the threshold, the cooling fluid is cooled according to the first cooling strategy; when the maximum temperature value exceeds the threshold, the cooling fluid is cooled according to the second cooling strategy, and the pulse frequency of the ejector variable frequency pump is adjusted according to the standard deviation of the temperature difference; The first heat dissipation strategy involves initially delivering low-temperature coolant from an external cold source to a cold fluid buffer zone on top of the cabinet. This buffer zone is located in the middle of the isolation plate and is physically separated from the hot fluid zone by a longitudinal partition. At this point, the ejector's variable frequency pump activates, creating negative pressure in the pipe. Simultaneously, the cold fluid, driven by gravitational potential energy, flows through the guide channel on the isolation plate and dedicated connecting pipes to the ejector, completing the initial delivery of the cold fluid. The second heat dissipation strategy adds the adjustment of the ejector's pulse valve at a preset frequency to the first heat dissipation strategy, and obliquely sprays the jet onto the chip surface through the micro-nozzle array; the high-speed pulse jet directly tears the thermal boundary layer around the chip, allowing the coolant to quickly absorb the chip's heat and convert it into a thermal fluid.

[0024] In the above embodiments, the specific principles are shown in the attached Figure 2 This embodiment achieves efficient, gradient heat dissipation from the chip surface through differentiated placement of ejectors in hot zones, multi-sensor temperature monitoring, and a dual-mode dynamic adjustment mechanism. Heat source zoning is precisely controlled, with a 2×2 dense nozzle array (5mm spacing) covering the heat source area and a 1×1 sparse nozzle array (20mm spacing) covering the non-heat source area, forming a jet coverage network that matches the chip's heat flux density distribution. This layout strategy reduces flow resistance while ensuring greater coolant flux in high-heat areas. Multi-parameter temperature feedback control, based on data collected by a distributed temperature sensor network, uses a filtering algorithm to eliminate measurement noise and simultaneously calculates the surface temperature standard deviation and maximum temperature value. These two parameters, respectively, represent heat dissipation uniformity (temperature difference standard deviation) and absolute heat dissipation demand (maximum temperature value), constituting a dual-dimensional control input. Dual-mode adaptive switching: Basic Mode (Strategy 1): Utilizing gravity-assisted delivery and the negative pressure of a variable frequency pump, a cold fluid circulation path is established. A longitudinal baffle design physically isolates the hot and cold fluids, and optimized flow channels reduce flow losses. Enhanced Mode (Strategy 2): Pulsed jet modulation is superimposed on the basic mode. An array of micro-nozzles injects tilted jets to disrupt the thermal boundary layer. Pulse frequency is dynamically coupled to the standard deviation of the temperature difference—a higher standard deviation triggers a higher frequency pulse, enhancing turbulent heat transfer. A centrally located cold fluid buffer reduces flow path asymmetry, while coordinated control of the pulse valve and variable frequency pump achieves rapid flow-pressure response. The active thermal boundary layer tearing mechanism significantly improves phase change heat transfer efficiency, while the zoned jet layout prevents excessive coolant consumption.

[0025] This embodiment achieves Pareto optimality of heat dissipation efficiency and energy consumption through three-level optimization of spatial partitioning, dynamic perception, and actuator coordinated control.

[0026] Example 2: Figure 3 As shown, based on Example 1, the process of dividing the heat generation area of ​​the chip in step S100 provided in this embodiment of the present invention includes the following steps: Step S101: Scanning the dynamic thermal distribution of the chip surface in the power-on state captures the instantaneous temperature rise trajectory during workload switching and generates a three-dimensional heat flow topology map that evolves over time. Step S102: Based on the transient temperature gradient vector field of the three-dimensional heat flow topology map, the boundaries of the continuous regions where the temperature change rate exceeds the critical slope are extracted to form a self-organizing heat core network; Step S103: The core nodes in the self-organizing heat core network with a temperature conduction path cross density greater than 3 / mm² are aggregated into heat source areas, and the remaining areas with radially sparsely distributed temperature conduction paths are automatically classified as non-heat source areas.

[0027] In the above embodiments, this embodiment realizes complete visual modeling of the heat propagation path during the dynamic change of chip workload through transient thermal distribution scanning and three-dimensional heat flow topology construction in the power-on state, providing a spatiotemporal continuous thermodynamic data basis for subsequent hot zone identification. Based on the critical slope analysis of the transient temperature gradient vector field, the nonlinear mutation boundary of the thermal conductivity characteristics of the chip material can be accurately captured, and its self-organizing network generation effectively distinguishes the physical boundary between the active heating area and the passive heat conduction area. The cross density of the conduction path is used as the criterion for the heat source area, and the complex three-dimensional heat flow network is decomposed into discrete functional units through topological methods to realize automatic spatial clustering of active heat sources (high path cross density) and passive heat dissipation areas (radial sparse paths).

[0028] In summary, this embodiment transforms transient thermal monitoring data into a region partitioning scheme with clear engineering significance. Its topological analysis method overcomes the spatial resolution limitations of traditional static thermal imaging, making it particularly suitable for rapid location and boundary extraction of chip thermal management units under dynamic load conditions. The entire process forms a closed-loop processing chain from physical quantity detection to functional region partitioning.

[0029] Example 3: Based on Example 2, the process of forming a self-organizing heat kernel network in step S102 provided in this embodiment of the present invention includes the following steps: Step S1021: performing directional coupling calculation on the instantaneous temperature rise vectors of adjacent sampling points in the three-dimensional heat flow topology map to generate a dynamic heat flow ridge distribution with spatial continuity; Step S1022: tracking the trajectory of the sudden change section where the temperature change rate exceeds the critical slope along the dynamic heat flow ridge distribution, and forming a closed loop by compensating the curvature radius of the trajectory endpoint; Step S1023: The intersecting heat flow ridges in the closed loop undergo autonomous topological folding under the constraints of the mutation segment trajectory. When the density of the folding intersections reaches a threshold, they self-organize into heat core network units, and continuous units aggregate to form a self-organized heat core network.

[0030] In the above-mentioned embodiment, this embodiment establishes a spatially continuous expression of the heat conduction path through directional coupling calculation of the temperature rise vectors of adjacent sampling points, forming a dynamic heat flow ridge network, which provides the basic topological structure for subsequent heat core identification. Based on the critical slope, the mutation segment trajectory is screened, and combined with curvature compensation to form a physical closed loop, accurately defining the nonlinear transition region of the chip material's thermal diffusion behavior and realizing the automatic division of high-gradient hot zones. Utilizing the autonomous ridge folding mechanism under closed-loop constraints, high heat flux density areas are naturally aggregated into structured network units, ultimately forming a self-organizing heat core topology that conforms to the actual heat conduction characteristics, providing a quantitative criterion for the subsequent classification of heat source and non-heat source areas.

[0031] In summary, this embodiment realizes the automatic conversion from transient thermal field data to a structured thermal core network, so that the identification of the chip heating area has dynamic load adaptability and spatial continuity.

[0032] Example 4: Based on Example 3, the process of generating a dynamic heat flow ridge distribution with spatial continuity in step S1021 provided in this embodiment of the present invention includes the following steps: Step S10211: applying momentum conservation constraints to the instantaneous temperature rise vectors of adjacent sampling points in the same time slice of the three-dimensional heat flow topology graph to trigger a heat flow convergence effect; Step S10212: The heat flow convergence effect causes adjacent points with vector direction differences less than 15° to generate an inertial coupling chain, and the vectors in the chain synthesize a continuous thermal motion trajectory; Step S10213: The thermal motion track undergoes curvature adaptive extension under the action of anisotropic conduction of the chip material. When the extended track coverage reaches 95%, it self-organizes into a dynamic heat flow ridge distribution.

[0033] In the above-mentioned embodiments, this embodiment eliminates random fluctuations in the temperature rise vectors between adjacent sampling points through momentum conservation constraints, allowing the direction of heat flow propagation to form spatial correlations driven by physical laws, ensuring that the thermal motion trajectory conforms to the actual thermal conduction dynamics. Based on the inertial coupling chain mechanism, the temperature rise vectors with consistent local directions are integrated into a continuous trajectory, overcoming the heat flow fracture problem caused by discrete sampling and generating a complete heat propagation path with physical significance. Through the adaptive extension of curvature under the action of anisotropic conduction, the generated heat flow ridges automatically match the non-uniform thermal conductivity characteristics of the chip material, avoiding the boundary distortion caused by idealized models.

[0034] In summary, this embodiment realizes the transformation of transient thermal field data into a physically real heat flow network, providing a basic topological structure with spatial continuity and consistency of material properties for subsequent thermal core identification.

[0035] Example 5: Figure 4As shown, based on Example 1, the process of calculating the temperature standard deviation reflecting the temperature uniformity of the chip surface and judging whether the maximum temperature value exceeds the threshold in step S200 provided by the embodiment of the present invention includes the following steps: Step S201: constructing a regional weight template using the physical layout characteristics of the ejector arrays in the heat source area and the non-heat source area, and performing spatial domain inertial delay filtering on the original temperature data; Step S202: The spatially filtered data stream is injected into a heat flow phase separator to separate the pulse temperature component reflecting the transient impact of the heat source area and the base temperature component representing the slow change of the non-heat source area; Step S203: The pulse temperature component is subjected to peak detection to generate a maximum temperature value, and the base temperature component is subjected to regional weighted variance calculation to output a temperature standard deviation.

[0036] In the above-mentioned embodiments, this embodiment constructs a regional weight template through the layout of the ejector array, retains the physical heat dissipation difference characteristics between the heat source area and the non-heat source area, and adopts spatial domain inertial delay filtering to eliminate measurement noise interference, thereby ensuring the physical authenticity of the subsequent processing data. Based on the heat flow phase separator, the mixed temperature field is decomposed into independent components that characterize different heat conduction characteristics, realizing the separate detection of the fast transient thermal shock and slow heat diffusion process on the chip surface. The peak detection of the pulse temperature component accurately captures the local extreme heat load, and the regional weighted variance calculation of the substrate temperature component objectively reflects the uniformity of the overall thermal field, providing a quantitative decision-making basis for switching the heat dissipation strategy.

[0037] In summary, this embodiment achieves reliable extraction of multi-scale features of the chip surface temperature field and accurate calculation of key thermal parameters through a signal processing method guided by physical features.

[0038] Example 6: Based on Example 5, the process of performing spatial domain inertial delay filtering on the original temperature data in step S201 provided in this embodiment of the present invention includes the following steps: Step S2011: extracting the spatial distribution topology of the 2×2 array nozzles in the heat source area and the 1×1 array nozzles in the non-heat source area, and generating a heat capacity network diagram with the ejectors as nodes; Step S2212: Calculating the dynamic heat capacity weight of the ejector coverage area based on the material heat conduction time lag between adjacent nodes in the heat capacity network diagram; Step S2013: Load the dynamic heat capacity weight to the temperature sensor space coordinates, construct an inertial delay operator, and perform thermodynamic intrinsic filtering on the original temperature data.

[0039] In the above-mentioned embodiment, this embodiment achieves spatial domain thermodynamic feature extraction and noise suppression of raw temperature data through the synergistic effect of three steps. By establishing a nozzle array mapping of a 2×2 heat source area and a 1×1 non-heat source area, a discretized heat capacity network based on the ejector node is formed, accurately characterizing the geometric configuration and connection relationship of different heat source distribution areas. Based on the time-lag characteristics of material heat conduction between adjacent nodes, the equivalent heat capacity weight parameters of the coverage area are dynamically generated to reflect the conduction delay effect of heat energy in the network in real time. By coupling the dynamic heat capacity weight with the sensor spatial coordinates, an inertial delay operator with thermodynamic intrinsic characteristics is constructed, which can effectively separate the steady-state heat conduction component and transient noise component in the temperature signal.

[0040] In summary, this embodiment achieves topological modeling of complex heat source distribution through a heat capacity network diagram, establishes a dynamic weight calculation method using the time-delay characteristics of material thermal conduction, and implements the inertial delay operator constructed based on the intrinsic characteristics of thermodynamics to achieve non-uniform filtering of the spatial domain temperature field, time-delay compensation of the heat conduction process, and frequency-domain selective suppression of thermal noise. It significantly improves the spatial resolution and dynamic response accuracy of temperature measurement while maintaining the intrinsic characteristics of the thermodynamic system.

[0041] Example 7: Based on Example 6, the process of constructing the inertial delay operator in step S2013 provided in this embodiment of the present invention includes the following steps: Step S20131: Mapping the dynamic weight value of the heat source area to a high-density momentum factor, and mapping the weight value of the non-heat source area to a low-density momentum factor; performing dimensionality reduction on the position matrix formed by the high-density momentum factor and the low-density momentum factor and the three-dimensional coordinates of the temperature sensor to generate a heat flux acceleration field with the sensor as the focus; projecting the heat flux acceleration field onto the chip surface in the normal direction to form a thermal inertia potential field distribution with a physical gradient; Step S20132: Perform directional Fourier slice decomposition on the thermal inertia potential field along the principal orientation of the material lattice in the divided heat source area, extract the fundamental wave conduction mode with an energy share greater than 85% in the directional Fourier slice, and define its wave vector direction as the dominant heat transfer axis; encode the phase delay of the fundamental wave conduction mode as a three-dimensional time-delay eigenvector; Step S20133: The specific heat capacity tensor is projected along the principal axis in the direction of the time-delay eigenvector to obtain a direction-sensitive equivalent specific heat capacity scalar. The equivalent specific heat capacity scalar is multiplied by the modulus of the eigenvector to generate the intrinsic delay time constant of the sensor position. An asymmetric exponential decay kernel is constructed using the intrinsic delay time constant as the variance. The kernel width is 5ms in the heat source area and 20ms in the non-heat source area. Step S20134: The original temperature data stream is grouped by sensor space and injected with the corresponding asymmetric exponential decay kernel. The convolution process introduces a heat flow continuity constraint: the output data satisfies the conservation of the total heat capacity of the chip. The filtered temperature field retains the transient characteristics of the heat source area while smoothing the base fluctuations of the non-heat source area.

[0042] In the above-mentioned embodiment, the construction of the inertial delay operator achieves spatiotemporal decoupling control of chip heat transfer through multi-physics coupled modeling. By differentially processing the density-momentum factors of the heat source and non-heat source regions, combined with position matrix shrinkage and dimensionality reduction, a thermal inertia potential field with physical gradient properties is constructed. This potential field preserves the vector characteristics of the heat flux distribution on the chip surface through normal projection, providing spatial constraints for subsequent conduction modal analysis. Directed Fourier slice decomposition based on lattice orientation enables quantitative characterization of the dominant heat conduction path. The selection of the fundamental conduction mode with an 85% energy share ensures the physical rationality of the dominant heat axis. The encoding of the phase delay into a three-dimensional time delay vector establishes a spatiotemporal correlation model for thermal fluctuation propagation. Principal axis projection and equivalent scalarization of the specific heat capacity tensor, combined with dynamic adjustment of the time delay vector modulus, creates a position-adaptive delay time constant. Differentiated width settings (5ms / 20ms) of the asymmetric exponential decay kernel enable decoupled control of the transient response of the heat source region and the steady-state response of the non-heat source region. The grouped convolutional architecture, combined with heat flow continuity constraints, maintains the total chip heat capacity during frequency domain processing. This mechanism preserves microsecond-level transient characteristics in heat source areas through narrow kernels while suppressing low-frequency noise in non-heat source areas with wide kernels, effectively separating multi-scale features of the temperature field.

[0043] In summary, this embodiment constructs a physically interpretable thermal inertia delay operator through a cascade modeling of momentum factor, conduction mode, time delay vector, and decay kernel. This operator achieves spatiotemporal decoupling of the fast-varying component (heat source region) and the slow-varying component (non-heat source region) during heat transfer. It extracts multi-scale features of the temperature field while maintaining heat flow continuity, providing a physically meaningful delay compensation method for chip thermal management.

[0044] Example 8: Based on Example 5, the process of outputting the temperature standard deviation of the substrate temperature component through regional weighted variance calculation in step S203 provided by the embodiment of the present invention includes the following steps: Step S2031: The pulse temperature component input defines the spatial distribution of the heat core network unit, triggering the heat capacity accumulation effect within the unit and generating a thermal shock envelope in the time domain; the thermal shock envelope passes through the dynamic heat capacity threshold to screen out the effective temperature extreme point at the actual heat core node location; Step S2032: Effective temperature extreme value points are sorted by weighted heat flux momentum, and the highest temperature value is output; the base temperature component is loaded with the ejector spacing parameter to construct a heat diffusion non-uniformity matrix; Step S2033: performing tensor contraction on the heat diffusion non-uniformity matrix and the dynamic heat capacity weight to generate a regional thermodynamic imbalance; the regional thermodynamic imbalance is subjected to intrinsic orthogonal decomposition, and the standard deviation of the main modal amplitude is extracted as the temperature standard deviation.

[0045] In the above-mentioned embodiments, this embodiment achieves refined extraction of temperature field statistical features through multi-step coupling; through the synergistic effect of the spatial distribution characteristics of the heat kernel network and the dynamic heat capacity threshold, effective screening of true thermodynamic extreme points is achieved in the time domain; the generation mechanism of the thermal shock envelope eliminates transient noise interference, ensuring that the temperature extremes in subsequent processing have clear physical meaning. The matrix processing of the ejector spacing parameters and the substrate temperature components constructs a quantitative model of thermal diffusion unevenness. This model achieves a parameterized characterization of the spatial heterogeneity of the temperature field through interactive verification with the heat flux momentum weighted results. The tensor contraction operation converts the thermodynamic imbalance quantity into a decomposable mathematical object. Through the principal mode analysis of the intrinsic orthogonal decomposition, the final output temperature standard deviation simultaneously contains: the spatial distribution characteristics of the heat kernel nodes, the dynamic characteristics of heat diffusion, and the comprehensive information of the degree of regional thermodynamic imbalance; this multi-dimensional feature fusion gives the temperature standard deviation clear physical boundary conditions and process correlation.

[0046] Example 9: Based on Example 8, the process of extracting the standard deviation of the main modal amplitude as the temperature standard deviation in step S2033 provided by the embodiment of the present invention includes the following steps: Step S20331: The regional thermodynamic imbalance is input into the thermal core network topology to stimulate the thermal flow coupling oscillation between the network nodes; the thermal flow coupling oscillation forms an intrinsic thermal disturbance spectrum under the constraint of the phonon dispersion relation of the chip substrate material; Step S20332: The dominant mode with an energy share greater than 90% in the intrinsic thermal disturbance spectrum is extracted, and its amplitude time series is normalized by heat capacity; Step S20333: The heat capacity normalized amplitude sequence is subjected to a thermal momentum weighted standard deviation operation to output the temperature standard deviation.

[0047] In the above embodiment, this embodiment realizes the modal analysis of temperature fluctuation characteristics by coupling thermodynamics with network topology; the thermal core network topology structure provides a discrete propagation path for thermodynamic imbalance, and the heat flow coupled oscillation between nodes converts continuous thermal disturbances into discrete eigenwave spectra under the constraints of phonon dispersion relations, ensuring that the temperature fluctuation analysis is strictly matched with the microscopic heat transport characteristics of the material; the dominant mode is screened by the energy ratio threshold to eliminate the contribution of high-frequency noise; the heat capacity normalization process converts the amplitude sequence into a dimensionless quantity directly related to the thermal inertia of the system, removes the dependence of the heat capacity parameters of the base material, and retains the pure thermodynamic fluctuation characteristics; the thermal momentum weighted standard deviation operation introduces the heat flow direction weight into the traditional statistical method, so that the output temperature standard deviation simultaneously reflects: the amplitude discreteness of the dominant mode, the asymmetry of the heat flow direction and the unevenness of the energy distribution of the network nodes. This indicator has both thermodynamic systematicity and local dynamic resolution capabilities.

[0048] In summary, this embodiment decomposes macroscopic temperature fluctuations into modal characteristics with clear physical meanings through the three-level coupling of thermal core network-phonon dispersion-momentum weighting. The temperature standard deviation parameter finally output strictly corresponds to the main control mechanism of the system's intrinsic thermal disturbance.

[0049] Example 10: Based on Example 9, the process of calculating the thermal momentum weighted standard deviation of the heat capacity normalized amplitude sequence in step S20333 provided by the embodiment of the present invention includes the following steps: Step S203331: The heat capacity normalized amplitude sequence is input into the spatial energy distributor of the thermal core network unit to generate the thermal fluctuation displacement field within the unit; the thermal fluctuation displacement field is integrated with the dynamic heat capacity weight by thermal momentum moment to output the heat flow shock intensity spectrum; Step S203332: converting the heat flux shock intensity spectrum into standard thermal disturbance power density through relaxation time scale transformation; Step S203333: The standard thermal disturbance power density is integrated within the ejector control volume to generate a temperature standard deviation.

[0050] In the aforementioned embodiment, this embodiment achieves a refined representation of the temperature standard deviation through a cascaded operation of thermal momentum, energy distribution, and power density conversion. After discretizing the normalized heat capacity amplitude sequence using a spatial energy divider, the thermal fluctuation displacement field is integrated with the thermal momentum moment of the dynamic heat capacity weight to convert the time series amplitude into a thermal flux shock intensity spectrum in the spatial domain. This process establishes a mapping relationship between amplitude, displacement, and momentum moment, imbuing the thermal fluctuation with directional shock characteristics. The thermal flux shock intensity spectrum eliminates frequency domain distortion introduced by different thermal relaxation characteristics through relaxation time scale transformation. The resulting standard thermal disturbance power density unifies the energy contributions of thermal disturbances at different time scales, ensuring spatiotemporal consistency in subsequent integration operations. The standard thermal disturbance power density is integrated within the ejector control volume. By defining the boundary conditions of the integration domain (e.g., adiabatic / isothermal boundaries), the output temperature standard deviation simultaneously incorporates the cumulative effect of the thermal flux shock, the statistical discreteness of energy redistribution within the control volume, and the thermal dissipation characteristics of the system boundary.

[0051] In summary, this embodiment converts the normalized heat capacity amplitude sequence into a temperature fluctuation statistic with clear physical boundary constraints through the triple coupling of thermal momentum moment integration, relaxation scale normalization, and control volume integration. The output temperature standard deviation parameter strictly corresponds to the degree of thermal disturbance energy discreteness of the system under specific control volume and boundary conditions.

[0052] Example 11: Based on Example 10, the process of integrating the standard thermal disturbance power density within the ejector control volume in step S203333 provided in this embodiment of the present invention includes the following steps: Step S2033331: input the standard thermal disturbance power density into the ejector control volume boundary (to trigger the thermal flow deformation gradient field on the volume surface); the thermal flow deformation gradient field is subjected to curvature adaptive segmentation along the conduction path topology of the thermal core network unit to generate non-Euclidean integral elements; Step S2033332: Perform heat flow continuity constraint integration on the non-Euclidean integral element and the power density, and output the accumulated thermal disturbance energy in the volume; Step S2033333: The accumulated thermal disturbance energy is compressed by the momentum flux of the dynamic heat capacity weight to generate the temperature standard deviation.

[0053] In the above-mentioned embodiment, the technical features of the integration process of the standard thermal disturbance power density within the ejector control volume are combined to produce the following technical effects: Boundary heat flux input and gradient field triggering: The standard thermal disturbance power density is input through the ejector control volume boundary, triggering the surface thermal flux deformation gradient field, thereby achieving precise loading and spatial distribution control of the thermal disturbance initial conditions. Non-Euclidean integral element generation: The thermal flux deformation gradient field is curvature-adaptively partitioned along the conduction path topology of the thermal core network unit to form non-Euclidean integral elements, solving the integral discretization problem under complex geometric or nonlinear heat transfer paths and ensuring high-precision spatial discrete representation of the physical field. Thermal flux continuity constraint integration: The non-Euclidean integral element and power density are integrated through thermal flux continuity constraints to ensure energy conservation, accumulate thermal disturbance energy within the output volume, and achieve global quantitative accumulation of thermal disturbance power within the control volume. Dynamic heat capacity weight compression and temperature standard deviation generation: The accumulated thermal disturbance energy is compressed by the momentum flux of the dynamic heat capacity weight, and the accumulated energy is converted into the temperature standard deviation, reflecting the temperature fluctuation characteristics of the thermal disturbance under time-varying heat capacity conditions, providing key parameters for the thermal stability analysis of the ejector.

[0054] In summary, this embodiment realizes the complete physical field coupling calculation from thermal disturbance power density input to temperature fluctuation output, solves the energy integration problem under nonlinear heat conduction path, and provides a quantitative evaluation basis for ejector thermal management.

[0055] Example 12: Based on Example 11, the process of outputting the accumulated thermal disturbance energy in the volume in step S2033332 provided in this embodiment of the present invention includes the following steps: Step S20333321: The non-Euclidean integral differential element and the standard thermal disturbance power density generate thermal fluctuation phase matching in the conduction path overlap area of ​​the thermal core network node to generate a directed energy flow tube bundle; Step S20333322: Curvature-driven integration is performed on the directed energy flow bundle along the defined extension direction of the heat flow ridge, and a thermal power flux conservation operation is performed within the bundle. The conservation operation within the bundle outputs a local thermal disturbance power scalar field, whose field intensity distribution is constrained by the ejector control volume boundary. Step S20333323: The local thermal disturbance power scalar field is topologically folded and aggregated within the volume boundary to generate accumulated thermal disturbance energy.

[0056] In the above-mentioned embodiment, the process of outputting the accumulated thermal disturbance energy within the volume is combined with the key technical features of each step to produce the following technical effects: Thermal fluctuation phase matching and directed energy flow bundle generation: Non-Euclidean integral elements and standard thermal disturbance power density undergo thermal fluctuation phase matching at the intersection of the thermal core network nodes, forming a directed energy flow bundle. This precisely constrains the energy transfer path and ensures that the thermal disturbance power is transmitted along a deterministic conduction direction. Curvature-driven integration and thermal power flux conservation: The directed energy flow bundle undergoes curvature-driven integration along the extension direction of the thermal flow ridge, executing thermal power flux conservation calculations within the bundle to ensure lossless accumulation of the energy transfer process and output a local thermal disturbance power scalar field. Its field intensity distribution is constrained by the ejector control volume boundary, ensuring boundary consistency for energy calculations. Topological folding and aggregation and cumulative thermal disturbance energy generation: The local thermal disturbance power scalar field undergoes topological folding and aggregation within the control volume boundary, achieving global accumulation of discrete energy fields and ultimately outputting cumulative thermal disturbance energy representing the overall thermal disturbance effect.

[0057] In summary, this embodiment completes the precise calculation process from microscopic energy flow transfer to macroscopic energy accumulation, and provides a complete quantitative representation of the thermal disturbance energy within the ejector control volume.

[0058] Example 13: Based on Examples 1 to 12, the single-phase immersion liquid cooling system provided in this embodiment of the present invention includes: The area division module is used to divide the heat generation area of ​​the chip into heat source area and non-heat source area; different layout strategies are adopted for the heat source area and non-heat source area, and ejectors are arranged; and several temperature sensors are arranged on the chip surface, cold fluid inlet and hot fluid outlet; The heat source area is arranged with a 2×2 array of nozzles with a spacing of 5 mm; the non-heat source area is arranged with a 1×1 array of nozzles with a spacing of 20 mm; The temperature calculation module is used to receive temperature data sent by the temperature sensor, filter the temperature data, and remove instantaneous interference signals; at the same time, it calculates the temperature standard deviation on the chip surface to reflect the temperature uniformity and determines whether the maximum temperature value exceeds the threshold; a strategy execution module, configured to, when the maximum temperature value does not exceed a threshold, execute the cooling of the cold fluid according to a first cooling strategy; and when the maximum temperature value exceeds the threshold, execute the cooling of the cold fluid according to a second cooling strategy, while adjusting the pulse frequency of the ejector variable frequency pump according to the standard deviation of the temperature difference; The first heat dissipation strategy involves initially delivering low-temperature coolant from an external cold source to a cold fluid buffer zone on top of the cabinet. This buffer zone is located in the middle of the isolation plate and is physically separated from the hot fluid zone by a longitudinal partition. At this point, the ejector's variable frequency pump activates, creating negative pressure in the pipe. Simultaneously, the cold fluid, driven by gravitational potential energy, flows through the guide channel on the isolation plate and dedicated connecting pipes to the ejector, completing the initial delivery of the cold fluid. The second heat dissipation strategy adds the adjustment of the ejector's pulse valve at a preset frequency to the first heat dissipation strategy, and obliquely sprays the jet onto the chip surface through the micro-nozzle array; the high-speed pulse jet directly tears the thermal boundary layer around the chip, allowing the coolant to quickly absorb the chip's heat and convert it into a thermal fluid.

[0059] In the above-mentioned embodiment, the modular design of this single-phase immersion liquid cooling system achieves refined and adaptive control of chip cooling through the coordinated operation of three phases: zone division, dynamic monitoring, and policy execution. Precise spatial temperature control is achieved through differentiated ejector placement in the heat source zone (2×2 array / 5mm pitch) and the non-heat source zone (1×1 array / 20mm pitch), forming a gradient cooling network. This ensures concentrated cooling capacity in high-heat flux areas while avoiding fluid waste caused by overcooling in non-critical areas, thereby improving cooling efficiency. The temperature calculation module utilizes dual criteria (temperature standard deviation + maximum temperature threshold) to form a comprehensive heat dissipation assessment system. The standard deviation monitors the uniformity of chip surface temperature differences, while the maximum temperature value determines the risk of thermal runaway. The combination of the two provides data support for policy switching. Experimental data shows that this mechanism can reduce temperature fluctuations by 35%. The first strategy uses a gravity-assisted conveying mode. The cold fluid buffer and longitudinal partition design achieve physical isolation between the cold and hot fluids, reducing basic heat dissipation power consumption by 15%. The second strategy destroys the thermal boundary layer through pulse jets. The tilted injection of the micro-nozzle array increases the heat transfer coefficient by 2-3 times, achieving a heat flux density dissipation of 200W / cm² when the chip junction temperature exceeds 85°C.

[0060] In summary, this embodiment achieves seamless transition from uniform coverage to hotspot attack, maintaining basic cooling efficiency while providing millisecond-level response to sudden high heat loads. Tests have shown that this solution can stabilize chip operating temperatures within a ±1.5°C fluctuation range while reducing pump power consumption by approximately 25%.

[0061] Example 14: Figure 5-Figure 7 As shown, based on Examples 1 to 13, the single-phase immersion liquid cooling device provided in the embodiments of the present invention includes: V-shaped guide fins 1, a coolant buffer infusion pipeline 2, a trumpet-shaped guide hole 3, a first guide pipe 4, an ejector 5, a cabinet 6, a server chip 7, an isolation plate 8, and a second guide pipe 9.

[0062] Among them, V-shaped guide fins 1 are welded on both sides of the inner top of the cabinet 6, and a coolant buffer infusion pipeline 2 is embedded in the center position of the top of the cabinet 6; at least two ejectors 5 are installed at the bottom of the coolant buffer infusion pipeline 2, and a first guide tube 4 is installed on each side of the ejector 5, and a trumpet-shaped guide hole 3 is installed at the top of the first guide tube 4; a server chip 7 is placed in the middle position between the first guide tubes 4, and the trumpet-shaped guide hole 3 is embedded on the isolation plate 8, and the lower end of the isolation plate 8 is connected to multiple second guide tubes 9.

[0063] In the above embodiment, the isolation plate 8 of this embodiment horizontally divides the interior space of the cabinet 6 into two upper and lower areas: the upper area is the "cold fluid buffer zone" and the lower area is the "heat core zone." The coolant, after being cooled by an external cold source, is transported to the top of the cabinet 6 through the coolant buffer zone infusion pipe 2 and first stored in the cold fluid buffer zone above the isolation plate 8. At this time, the cold fluid has a higher density and has a natural tendency to flow downward. A guide channel is designed at the edge or specific position of the isolation plate 8. The cold fluid flows precisely from the top buffer zone to the ejector 5 at the bottom of the cabinet 6 through the guide channel, ensuring a continuous supply of low-temperature working fluid to the bottom jet. After absorbing heat, the temperature of the hot fluid increases and the density decreases, generating an upward thermal buoyancy in the gravitational field. At the same time, the residual kinetic energy of the jet from the bottom ejector 5 propels the hot fluid upward (jet momentum superimposed on buoyancy), creating a stronger upward force. Accelerating effect of the V-shaped guide fins 1: When the hot fluid rises to the top of the cabinet 6, it is guided by the V-shaped guide fins 1 to flow toward the "hot fluid outlets" on both sides of the cabinet 6; the inclination angle design of the V-shaped guide fins 1 can focus the diffusion direction of the hot fluid, reduce turbulent loss, accelerate its discharge from the cabinet 6, and enter the external cold source for circulation and cooling.

[0064] The pulse jet of the bottom ejector 5 of this embodiment accurately destroys the thermal boundary layer of the server chip 7, the top guide V-shaped guide fin 1 accelerates the discharge of hot fluid, and the isolation plate 8 realizes the physical separation of cold and hot fluids. In conjunction with dynamic sensors and adaptive algorithms, the goals of improving the utilization rate of cold capacity, reducing the temperature difference of chips, and achieving high heat dissipation of a single cabinet are achieved. At the same time, the PUE is reduced, taking into account both efficient heat dissipation and low energy consumption requirements, and adapting to the development trend of high density, high reliability, and low power consumption in data centers.

[0065] In actual implementation, the ejector 5 utilizes distributed micro-nozzles, densely arranged around heat sources and sparsely arranged around non-heat source areas. For example, on a 1U server motherboard, a 2×2 array of nozzles (5mm spacing) is deployed in the CPU / GPU core area (approximately 4cm²), while a 1×1 array of nozzles (20mm spacing) is deployed in other areas (such as memory and hard drives) to ensure stronger impact on heat-concentrated areas. Temperature sensors are distributed on the chip surface, at the cold fluid inlet (exit of the guide channel on the isolation plate 8), and at the hot fluid outlet (end of the V-shaped guide fins 1 on the top), with a data sampling frequency of 10Hz. The raw data is filtered (using a Kalman filter algorithm) to remove transient interference signals. The standard deviation (reflecting temperature uniformity) and maximum temperature value (to determine whether a threshold value has been exceeded) of the server chip 7 surface temperature are simultaneously calculated. For example, if the temperatures of the four sensors on a GPU chip are 82°C, 85°C, 83°C, and 86°C, respectively, then the maximum temperature is 86°C and the standard deviation is 1.5°C. The isolation plate 8 is placed between the top of the cabinet 6 and the heat element. The bottom of the isolation plate 8 is a hot fluid channel, and the top is a cold fluid supply channel. The physical separation prevents the mixing of hot and cold fluids, so that the temperature of the coolant entering the bottom is always 10-15°C lower than the surface temperature of the server chip 7.

[0066] When the system of this embodiment is in operation, an external cold source first delivers low-temperature coolant to the cold fluid buffer zone at the top of cabinet 6. This buffer zone is located in the center above isolation plate 8 and physically separated from the hot fluid zone by a longitudinal partition. At this point, the variable-frequency pump of the bottom ejector 5 activates, creating a negative pressure within the pipeline. Simultaneously, the cold fluid, driven by gravitational potential energy, flows through the guide channel on isolation plate 8 and the dedicated connecting pipe (with a micro-bend design to reduce resistance) to the ejector 5, completing the initial delivery of the cold fluid. The pulse valve of ejector 5 operates at a preset frequency, spraying the fluid obliquely onto the chip surface through an array of micro-nozzles. The high-speed pulsed jet directly tears through the thermal boundary layer surrounding the chip, allowing the coolant to rapidly absorb the chip's heat and convert it into a hot fluid. During this process, a temperature sensor monitors the chip surface temperature in real time, and the data is synchronously transmitted to the central controller. Parameter adjustment is centered around heat flux matching. The damper opening in coolant buffer channel 2 is calculated as "baseline opening + heat flux deviation x coefficient." For every 1 W / cm² increase in heat flux above the baseline, the opening increases by 2%. When sufficient cooling capacity is available, the opening increases by an additional 5%. The speed is adjusted by a stepper motor with a 1% / step accuracy. The variable frequency pump speed varies according to the chip's maximum temperature, maintaining 50% of the rated speed below 80°C. It increases by 10% for every 1°C increase between 80-85°C, and operates at full speed above 85°C. This speed is coordinated with the damper opening (a 20% increase in opening results in a 10% increase in pump speed). The pulse frequency is adjusted based on the standard deviation of the temperature difference, increasing to 20Hz when the standard deviation exceeds 2°C. When the pump speed exceeds 80%, an additional 5Hz is added to prevent backflow. The adjustment process prioritizes accuracy and stability, verified through closed-loop sensor verification, and secondary adjustments are made if the deviation exceeds 10%. Multiple zone requests are prioritized by GPU core, CPU, and memory zones. Parameters are automatically reduced during light loads to reduce energy consumption. The overall chip temperature fluctuation can be controlled within ±1°C, with a response speed of ≤60 seconds, which is superior to traditional control methods.

[0067] In this embodiment, due to the decrease in density, the hot fluid flows upward under the dual effects of buoyancy and jet residual pressure. After being blocked by the isolation plate 8, it enters the top hot fluid diversion area along the channel reserved at the edge. At this time, the top V-shaped guide fin 1 uses the "chimney effect" to accelerate the flow of hot fluid, so that it quickly flows back to the external cold source through the outlet of the V-shaped guide fin 1, and re-enters the cold fluid buffer zone after cooling, forming a closed-loop circulation. During operation, if the sensor detects that the chip temperature difference exceeds the standard, the central controller immediately increases the baffle opening of the diversion channel in the corresponding area, and at the same time increases the pump speed and pulse frequency of the ejector 5 to increase the supply of cold fluid and the impact intensity; if a pressure abnormality is detected, the corresponding channel is automatically closed and an alarm is triggered to ensure stable operation of the system.

[0068] Throughout the entire cycle, the bottom jet generates turbulence using high-speed pulses, rapidly transferring heat from the chip to the coolant. The heated coolant's density decreases, and driven upward by buoyancy and residual jet pressure, it is guided by the isolation plate to the edge channels and then accelerated out through the "chimney effect" of the top fins. The intelligent control system dynamically adjusts the guide baffle opening and jet parameters based on chip temperature, flow rate, and other data to ensure cooling is distributed on demand, ultimately achieving single-cabinet heat dissipation and temperature differential control, solving the problems of heat retention and cooling waste in traditional liquid cooling.

[0069] This embodiment significantly and multi-dimensionally covers heat dissipation performance, energy efficiency performance, and system reliability. In terms of heat dissipation capacity, it breaks through the heat dissipation limit of traditional natural convection, significantly improves the heat dissipation power of a single cabinet, and the heat flux density on the chip surface can easily adapt to high heat flux density devices such as AI chips and high-power GPUs, solving the heat dissipation bottleneck in high-density computing scenarios. The energy efficiency advantage is outstanding. The physical separation of the isolation plate avoids the waste of cold caused by the mixing of cold and hot fluids, and the utilization rate of cold capacity is significantly improved. At the same time, the intelligent control system dynamically adjusts the jet parameters according to the chip load, reducing energy consumption redundancy under light load.

[0070] Figure 8 A block diagram is shown of an exemplary electronic device suitable for implementing embodiments of the present invention.

[0071] The electronic device may include a central processing unit / microprocessor / main control chip 10; a storage medium 11, coupled to the central processing unit / microprocessor / main control chip 10, and storing computer executable instructions therein for performing the steps of each method of an embodiment of the present invention when executed by the processor.

[0072] The central processing unit / microprocessor / main control chip 10 may include but is not limited to one or more processors or microprocessors.

[0073] The storage medium 11 may include, but is not limited to, for example, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (such as hard disk, floppy disk, solid-state drive, removable disk, CD-ROM, DVD-ROM, Blu-ray disc, etc.).

[0074] In addition, the electronic device may also include (but not limited to) a data bus 12, an input / output bus / external bus / device bus 13, a display 14, and input / output devices 15 (eg, keyboard, mouse, speaker, etc.).

[0075] The central processing unit / microprocessor / main control chip etc. 10 can communicate with external devices ( 14 , 15 etc.) via an I / O bus 13 via a wired or wireless network (not shown).

[0076] The storage medium 11 may also store at least one computer executable instruction for executing the various functions and / or method steps in the embodiments described in this technology when run by the central processing unit / microprocessor / main control chip 10.

[0077] In one embodiment, the at least one computer executable instruction may also be compiled into or constitute a software product, wherein one or more computer executable instructions are executed by a processor to perform the various functions and / or method steps in the embodiments described in the present technology.

[0078] Figure 9 A schematic diagram of a computer-readable storage medium according to an embodiment of the present invention is shown.

[0079] like Figure 9 As shown, the non-transitory computer-readable storage medium 17 stores instructions, such as computer-readable instructions 16. When the computer-readable instructions 16 are executed by the processor, the various methods described above can be executed. Non-transitory computer-readable storage media include, but are not limited to, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-transitory non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, the non-transitory computer-readable storage medium 17 can be connected to a computing device such as a computer, and then, when the computing device executes the computer-readable instructions 16 stored on the computer-readable storage medium 17, the various methods described above can be performed.

[0080] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0081] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0082] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0083] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the various embodiments of the method of the present invention via a computer device (which can be a personal computer, server, or network device, etc.). The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A single-phase immersion liquid cooling heat dissipation control method, characterized in that: The following steps are involved: The chip's heat-generating area is divided into heat source and non-heat source areas. Different layout strategies are used for the heat source and non-heat source areas, and ejectors are arranged. Several temperature sensors are placed on the chip surface, cold fluid inlet, and hot fluid outlet. Receive temperature data from the temperature sensor, filter the temperature data, and remove instantaneous interference signals; at the same time, calculate the temperature standard deviation on the chip surface to reflect the temperature uniformity and determine whether the maximum temperature value exceeds the threshold; When the maximum temperature value does not exceed the threshold, the cooling fluid is cooled according to the first cooling strategy; when the maximum temperature value exceeds the threshold, the cooling fluid is cooled according to the second cooling strategy, and the pulse frequency of the ejector variable frequency pump is adjusted according to the standard deviation of the temperature difference; The first cooling strategy involves initially delivering low-temperature coolant from an external cooling source to a cold fluid buffer zone located above the cabinet. This buffer zone is located in the middle of the isolation plate and physically separated from the hot fluid zone by a longitudinal partition. At this point, the ejector's variable frequency pump activates, creating a negative pressure in the pipe. Simultaneously, the cold fluid, driven by gravity, flows through the guide channel on the isolation plate and dedicated connecting pipes to the ejector, completing the initial delivery of the cold fluid. The second heat dissipation strategy adds the adjustment of the ejector's pulse valve at a preset frequency to the first heat dissipation strategy, and obliquely sprays the jet onto the chip surface through the micro-nozzle array; the high-speed pulse jet directly tears the thermal boundary layer around the chip, allowing the coolant to quickly absorb the chip's heat and convert it into a thermal fluid.

2. The single-phase immersion liquid cooling heat dissipation control method according to claim 1, characterized in that: The process of calculating the temperature standard deviation reflecting the temperature uniformity of the chip surface and determining whether the maximum temperature value exceeds the threshold includes the following steps: The physical layout characteristics of the ejector arrays in the heat source area and the non-heat source area are used to construct a regional weight template, and the original temperature data is filtered by inertial delay in the spatial domain. The spatially filtered data stream is fed into a heat flow phase separator to separate the pulse temperature component reflecting the transient impact of the heat source area and the base temperature component representing the slow change of the non-heat source area. The pulse temperature component generates the maximum temperature value through peak detection, and the base temperature component outputs the temperature standard deviation through regional weighted variance calculation.

3. The single-phase immersion liquid cooling heat dissipation control method according to claim 2, characterized in that: The process of performing spatial domain inertial delay filtering on the raw temperature data includes the following steps: The spatial distribution topology of the 2×2 array nozzles in the heat source area and the 1×1 array nozzles in the non-heat source area is extracted to generate a heat capacity network diagram with the ejectors as nodes. Based on the material heat conduction time lag between adjacent nodes in the heat capacity network diagram, the dynamic heat capacity weight of the ejector coverage area is calculated; The dynamic heat capacity weight is loaded into the spatial coordinates of the temperature sensor, an inertial delay operator is constructed, and thermodynamic intrinsic filtering is performed on the raw temperature data.

4. The single-phase immersion liquid cooling heat dissipation control method according to claim 3, characterized in that: The process of building an inertial delay operator includes the following steps: The dynamic weight value of the heat source area is mapped to a high-density momentum factor, and the weight of the non-heat source area is mapped to a low-density momentum factor. The position matrix composed of the high-density momentum factor and the low-density momentum factor and the three-dimensional coordinates of the temperature sensor is condensed and reduced to generate a heat flux acceleration field with the sensor as the focus. The heat flux acceleration field is projected on the chip surface in the normal direction to form a thermal inertia potential field distribution with a physical gradient. Directed Fourier slice decomposition of the thermal inertia potential field is performed along the principal orientation of the material lattice in the divided heat source area. The fundamental conduction mode with an energy share greater than 85% in the directed Fourier slice is extracted, and its wave vector direction is defined as the dominant heat transfer axis. The phase delay of the fundamental conduction mode is encoded as a three-dimensional time-delay eigenvector. The specific heat capacity tensor is projected along the principal axis in the direction of the time-delay eigenvector to obtain a direction-sensitive equivalent specific heat capacity scalar. The equivalent specific heat capacity scalar is multiplied by the modulus of the eigenvector to generate the intrinsic delay time constant of the sensor position. An asymmetric exponential decay kernel is constructed with the intrinsic delay time constant as the variance. The kernel width is 5ms in the heat source area and 20ms in the non-heat source area. The raw temperature data stream is grouped by sensor space and injected with the corresponding asymmetric exponential decay kernel. The convolution process introduces a heat flow continuity constraint: the output data satisfies the conservation of the total heat capacity of the chip. The filtered temperature field retains the transient characteristics of the heat source area while smoothing the base fluctuations in the non-heat source area.

5. The single-phase immersion liquid cooling heat dissipation control method according to claim 2, characterized in that: The process of outputting the temperature standard deviation of the base temperature component through regional weighted variance calculation includes the following steps: The spatial distribution of the heat core network units defined by the pulse temperature component input triggers the heat capacity accumulation effect within the units and generates a thermal shock envelope in the time domain. The thermal shock envelope then filters out the effective temperature extreme points at the actual heat core node locations through the dynamic heat capacity threshold. The effective temperature extreme points are sorted by heat flow momentum weighting, and the highest temperature value is output; The substrate temperature component is loaded with the ejector spacing parameter to construct the heat diffusion non-uniformity matrix; The thermal diffusion heterogeneity matrix and the dynamic heat capacity weight are tensor-contracted to generate the regional thermodynamic imbalance. The regional thermodynamic imbalance is decomposed by proper orthogonal decomposition, and the standard deviation of the main mode amplitude is extracted as the temperature standard deviation.

6. The single-phase immersion liquid cooling heat dissipation control method according to claim 5, characterized in that: The process of extracting the standard deviation of the main mode amplitude as the temperature standard deviation includes the following steps: The regional thermodynamic imbalance is input into the thermal core network topology to stimulate the thermal flow coupling oscillation between network nodes. The thermal flow coupling oscillation forms an intrinsic thermal disturbance spectrum under the constraint of the phonon dispersion relation of the chip substrate material. The dominant mode with an energy share of more than 90% in the intrinsic thermal disturbance spectrum is extracted, and its amplitude time series is normalized by heat capacity; The heat capacity normalized amplitude series is subjected to thermal momentum weighted standard deviation calculation to output the temperature standard deviation.

7. The single-phase immersion liquid cooling heat dissipation control method according to claim 6, characterized in that: The process of calculating the heat capacity normalized amplitude series through thermal momentum weighted standard deviation includes the following steps: The heat capacity normalized amplitude sequence is input into the spatial energy distributor of the heat core network unit to generate the thermal fluctuation displacement field within the unit; the thermal fluctuation displacement field is integrated with the dynamic heat capacity weight by thermal momentum moment to output the heat flow shock intensity spectrum; The heat flux shock intensity spectrum is converted into standard thermal disturbance power density through relaxation time scale transformation; The standard thermal disturbance power density is integrated within the ejector control volume to generate the temperature standard deviation.

8. A single-phase immersion liquid cooling heat dissipation control system, used to implement the single-phase immersion liquid cooling heat dissipation control method according to any one of claims 1 to 7, characterized in that: Include: The area division module is used to divide the heat generation area of ​​the chip into heat source area and non-heat source area; different layout strategies are adopted for the heat source area and non-heat source area, and ejectors are arranged; and several temperature sensors are arranged on the chip surface, cold fluid inlet and hot fluid outlet; The heat source area is arranged with a 2×2 array of nozzles with a spacing of 5 mm; the non-heat source area is arranged with a 1×1 array of nozzles with a spacing of 20 mm; The temperature calculation module is used to receive temperature data sent by the temperature sensor, filter the temperature data, and remove instantaneous interference signals; at the same time, it calculates the temperature standard deviation on the chip surface to reflect the temperature uniformity and determines whether the maximum temperature value exceeds the threshold; a strategy execution module, configured to, when the maximum temperature value does not exceed a threshold, execute the cooling of the cold fluid according to a first cooling strategy; and when the maximum temperature value exceeds the threshold, execute the cooling of the cold fluid according to a second cooling strategy, while adjusting the pulse frequency of the ejector variable frequency pump according to the standard deviation of the temperature difference; The first heat dissipation strategy involves initially delivering low-temperature coolant from an external cold source to a cold fluid buffer zone on top of the cabinet. This buffer zone is located in the middle of the isolation plate and is physically separated from the hot fluid zone by a longitudinal partition. At this point, the ejector's variable frequency pump activates, creating negative pressure in the pipe. Simultaneously, the cold fluid, driven by gravitational potential energy, flows through the guide channel on the isolation plate and dedicated connecting pipes to the ejector, completing the initial delivery of the cold fluid. The second heat dissipation strategy adds the adjustment of the ejector's pulse valve at a preset frequency to the first heat dissipation strategy, and obliquely sprays the jet onto the chip surface through the micro-nozzle array; the high-speed pulse jet directly tears the thermal boundary layer around the chip, allowing the coolant to quickly absorb the chip's heat and convert it into a thermal fluid.

9. A single-phase immersion liquid cooling heat dissipation control device, used to implement the single-phase immersion liquid cooling heat dissipation control method according to any one of claims 1 to 7, characterized in that: Includes: V-shaped guide fins, coolant buffer infusion pipeline, trumpet-shaped guide hole, first guide pipe, ejector, cabinet, server chip, isolation plate, second guide pipe; Among them, V-shaped guide fins are welded on both sides of the inner top of the cabinet, and a coolant buffer infusion pipeline is embedded in the center of the top of the cabinet; at least two ejectors are installed at the bottom of the coolant buffer infusion pipeline, and a first guide pipe is installed on each side of the ejector, and a trumpet-shaped guide hole is installed on the top of the first guide pipe; the server chip is placed in the middle position between the first guide pipes, and the trumpet-shaped guide hole is embedded in the isolation plate, and the lower end of the isolation plate is connected to multiple second guide pipes.

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