Miniaturized monolithic integration method of geomagnetic sensor and MCU (Microprogrammed Control Unit)

Abstract

The invention discloses a miniaturized monolithic integration method of a geomagnetic sensor and an MCU (Microprogrammed Control Unit). The method comprises the following steps of (1) low-temperature CMOS circuit layer preparation, (2) TSV three-dimensional interconnection structure processing, (3) magnetic-core-free planar coil manufacturing, (4) low-temperature electromagnetic shielding layer integration and (5) structure release and vacuum packaging. Process conflicts and hysteresis errors introduced by ferromagnetic materials are eliminated through a non-magnetic-core design, a TSV (through silicon via) three-dimensional interconnection technology is adopted to replace traditional plane wiring, the size of the module is compressed to the millimeter level, meanwhile, a broadband electromagnetic shielding layer is integrated, and it is ensured that in a weak magnetic field (lt; and the signal-to-noise ratio in a detection scene is greater than or equal to 30dB. The low-temperature compatibility with a CMOS (complementary metal oxide semiconductor) process can be realized, the mass production feasibility needs to adapt to a standard semiconductor production line, the cost of a single chip is reduced by more than 30%, and the method is suitable for navigation equipment, consumer electronics and industrial sensing systems.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of micro-electro-mechanical system (MEMS) and semiconductor integration, and particularly relates to a miniaturized monolithic integration method of a geomagnetic sensor and a micro control unit (MCU). BACKGROUND

[0002] The integration scheme of traditional geomagnetic sensors and MCUs has long been faced with multiple contradictions of volume, power consumption and process compatibility. The existing technology usually adopts discrete packaging or high-temperature process to realize the integration of sensors and circuits, resulting in a large volume of sensor modules (usually more than 5*5mm 2 ), which is difficult to meet the needs of wearable devices, micro navigation modules and other compact spaces. Moreover, the high-temperature processing steps (such as annealing temperature exceeding 600℃) are easy to damage the metal interconnection layer (such as aluminum or copper) in the CMOS circuit, resulting in low yield (usually less than 80%) and high cost.

[0003] At the same time, the signal crosstalk problem of the integrated sensor is particularly prominent. The geomagnetic sensor relies on the design of ferromagnetic materials (such as NiFe alloy), which further limits the miniaturization potential. Moreover, the noise of the MCU circuit is coupled to the sensor through the shared substrate, resulting in a signal-to-noise ratio (SNR) lower than 10dB in the weak magnetic field (<1μT) detection scenario, which seriously restricts the detection accuracy. Although some schemes try to optimize the volume through multi-chip packaging (SiP) or planar stacking, the process complexity and cost are significantly increased, which is difficult to meet the comprehensive needs of miniaturization, low power consumption and high reliability of consumer electronics and industrial Internet of Things.

[0004] The document (Design and Measurement of Microelectromechanical Three-Axis Magnetic Field Sensors Based on the CMOS Technique, doi:10.3390 / mi14051038.) designs a three-axis magnetic field sensor with a magnetic transistor structure based on the TSMC 0.18 μm CMOS process, and the CMOS front is about 350-400 DEG C. The scheme adopts a magnetic sensitive transistor, does not adopt a TSV three-dimensional interconnection, and the structure is a 2D interconnection; there is no vacuum packaging and magnetic shielding layer design; the magnetic hysteresis error and anti-interference problem are not solved; there is no integrated MCU function. The document (Design, Fabrication, Characterization and Reliability Study of CMOS-MEMS Lorentz-Force Magnetometers, doi:10.48550 / arXiv.2109.10980.) is based on the CMOS process to manufacture a Lorentz force magnetometer, but only a single-layer coil design; there is no TSV interconnection, and it cannot realize vertical high-density integration; no magnetic shielding layer and structure release packaging design are introduced; there is no single-chip scheme compatible with MCU. The document (S. Tumanski, Thin Film Magnetoresistive Sensors. Bristol, UK: IOP Publishing, 2007.) adopts NiFe and other ferromagnetic materials to construct AMR / GMR magnetic resistance sensors, which seriously depend on ferromagnetic materials and have the problems of magnetic hysteresis and temperature drift; the discrete packaging structure has low integration; there is no packaging optimization and three-dimensional interconnection, and it cannot be used in weak magnetic field scenes; it is not compatible with standard CMOS logic circuits.

[0005] In view of the above problems, there is an urgent need for a low-temperature compatible, high-integration and anti-interference geomagnetic sensor and MCU single-chip integration scheme to break through the dependence of traditional technology on ferromagnetic materials and the high-temperature process limitation. SUMMARY

[0006] In order to solve the problems of large volume, high power consumption, process incompatibility and serious magnetic hysteresis error in the traditional geomagnetic sensor and MCU integration scheme, the present application proposes a miniaturized single-chip integration method of geomagnetic sensor and MCU. For the first time in the magnetic sensor + MCU single-chip integration, the three-stage temperature control strategy is systematically distinguished, the whole process is low-temperature compatible, and the metal interconnection electromigration and thermal failure are avoided; the present application adopts a multi-layer non-magnetic core spiral coil structure, a TSV three-dimensional interconnection and a low-temperature magnetic shielding composite layer.

[0007] The method of the present invention adopts coreless design and vertical three-dimensional interconnection technology to break through the volume limitation of traditional discrete packaging and ultimately achieve millimeter-level size (2.5×2.5×0.4mm 3 ), low power consumption (≤295μW), high signal-to-noise ratio (≥30dB) and >95% yield single-chip magnetic sensor module, significantly improving the accuracy of weak magnetic field detection and integrated manufacturing efficiency.

[0008] The present invention adopts the following technical solutions:

[0009] A method for miniaturized single-chip integration of a geomagnetic sensor and an MCU comprises the following steps:

[0010] (a) forming an MCU circuit layer on a silicon substrate using a CMOS-MEMS process, wherein the MCU circuit layer includes a signal amplification module, a digital processing unit, and a communication interface;

[0011] (b) fabricating a coreless planar coil of a Lorentz force geomagnetic sensor on the MCU circuit layer, and vertically interconnecting the coil with the MCU circuit layer through vertical through-holes (TSVs);

[0012] (c) depositing a tantalum nitride (TaN) composite electromagnetic shielding layer between the MCU circuit layer and the planar coil;

[0013] (d) The suspended support structure of the planar coil is released by etching, and the subsequent structure release and packaging process is packaged using non-magnetic vacuum packaging materials. The packaging process uses a bonding temperature of 250-300°C and a vacuum degree of <10 - 3Pa.

[0014] Furthermore, the vertical through hole TSV in step (b) has a diameter of 3-5 μm and an aspect ratio of 8:1-12:1.

[0015] Furthermore, the maximum temperature of the front-end process of the CMOS-MEMS process is controlled at 350-400° C., the metal interconnection layer is a copper dual damascene structure, and the process yield is >95%.

[0016] Furthermore, the planar coil is a multi-layer stacked structure with a line width of ≤2μm, an interlayer spacing of ≥3 times the line width, a total thickness of 0.4-0.5mm, and a chip area of ​​2.5×2.5-3×3mm 2 .

[0017] Furthermore, the diameter of the TSV through hole is 3-5 μm, the filling material is copper or polysilicon, and the sidewall of the through hole is covered with a titanium nitride TiN diffusion barrier layer.

[0018] Furthermore, the TSV through-hole resistance is 40-50mΩ, the parasitic capacitance is ≤0.1pF, and the signal transmission delay is <10ps.

[0019] Furthermore, the electromagnetic shielding layer is a composite material of tantalum nitride TaN and Fe3O4 nanoparticles, with a thickness of 100-500nm, a Fe3O4 doping ratio of 1-5wt%, and a noise attenuation capability of ≥25dB.

[0020] Furthermore, the magnetic permeability of the non-magnetic vacuum packaging material in step (d) is ≥95%.

[0021] As a preferred embodiment of the present invention, the present invention provides a method for miniaturized monolithic integration of a geomagnetic sensor and an MCU, the method comprising the following steps:

[0022] (1) Preparation of low-temperature CMOS circuit layer

[0023] The MCU circuit layer is fabricated on a silicon substrate using an 180nm CMOS process, with the maximum front-end process temperature strictly controlled between 350°C and 400°C. PMOS / NMOS transistors are formed through ion implantation and photolithography, with a gate oxide layer thickness of 3.2nm. The metal interconnects utilize a dual-Damascene copper interconnect structure, and the dielectric layer is deposited using PECVD SiO2 at a temperature controlled between 200°C and 300°C, with a dielectric thickness of 0.5μm. Finally, a 0.5μm-thick silicon nitride (SiN) passivation layer is deposited as a protective layer.

[0024] This low-temperature process enables copper interconnect resistivity to ≤2.2μΩ·cm with a yield of >95%. It integrates a low-noise amplifier (noise figure <1dB) and a 24-bit ADC to support weak signal processing.

[0025] (2) TSV three-dimensional interconnection structure processing

[0026] A 1.2μm-thick SiO2 insulating layer is deposited on the MCU circuit layer using PECVD at a temperature of 200-300°C. TSV vias (diameter 3-5μm, aspect ratio 8:1-10:1) are etched using the Bosch process. A 5nm-thick TiN diffusion barrier layer is deposited on the inner walls of the vias using ALD. After copper is electroplated, chemical mechanical polishing (CMP) is used to achieve a surface roughness of ≤5nm.

[0027] The TSV through-hole resistance is 40-50mΩ, the parasitic capacitance is reduced to 0.1pF (traditional planar wiring is 0.5pF), and the signal transmission delay is shortened to less than 10ps.

[0028] (3) Production of coreless planar coils

[0029] A quasi-heterogeneous multilayer stacking process is used to fabricate high-density planar coils with line widths ≤ 2μm and pitches ≥ 6μm. After sputtering a Ti / Cu seed layer, the spiral coil pattern is defined using deep ultraviolet (DUV) lithography. Copper is electroplated to a thickness of 2μm, and a 0.5μm-thick SiO2 insulating layer is deposited between layers using PECVD. After stacking 30 layers, the total thickness is controlled to 0.4-0.5mm.

[0030] The Z-axis coil is directly connected to the MCU analog front end through TSV, with an inductance value of 25-35μH (compared to 50μH for traditional magnetic core solutions), an 80% reduction in volume, and supports three-axis magnetic field detection (X / Y / Z), with sensitivity deviation of each axis less than 5%.

[0031] The specific process flow of the multi-layer stacking process of quasi-heterogeneous integration described in step (3) is as follows:

[0032] First, a 20nm thick Ti / 300nm Cu seed layer is deposited by magnetron sputtering on the CMOS circuit layer with completed TSV interconnect structure. Then, deep ultraviolet (DUV) lithography technology (exposure wavelength 193nm, resolution <0.5μm) is used to define the spiral coil pattern, and copper is electroplated in an electrolytic bath to a single layer thickness of approximately 2μm to form a single-layer conductor structure.

[0033] To achieve interlayer insulation, after each layer of conductor structure is completed, a 500nm thick SiO2 layer is deposited at 200–250°C using a PECVD process to ensure dielectric strength and low parasitic capacitance. Chemical mechanical polishing (CMP) is then performed to ensure interlayer flatness, with a surface roughness Ra of <5nm after polishing. After repeating this process for 30 layers, the total thickness is controlled to 0.4–0.5mm.

[0034] To ensure the continuity of the vertical interconnection path, the Z-axis coil layers are connected vertically through a local TSV structure, and the wafer-level structure release process (HF vapor phase etching) is used to reduce mechanical stress accumulation while maintaining structural stability.

[0035] (4) Low-temperature electromagnetic shielding layer integration

[0036] A TaN-Fe3O4 composite shielding layer (at a temperature of 250°C-300°C) with a thickness of 100-500nm and a Fe3O4 doping ratio of 1-5wt% is magnetron sputtered between the MCU circuit layer and the planar coil. This composite film effectively shields electromagnetic interference generated by the CMOS circuitry. Patterning is performed using a reactive ion etching (RIE) process using a Cl2 / BCl3 gas combination, covering the MCU digital circuit area. This shielding layer achieves noise attenuation of ≥25dB ​​in the 1-10MHz frequency band, and the baseline noise of the geomagnetic sensor is ≤0.05nT / √Hz.

[0037] (5) Structural release and vacuum packaging

[0038] The sacrificial layer under the coil is removed by HF vapor etching (etching rate 1μm / min). After release, the suspended height is 1μm, and the mechanical resonance frequency is ≥10kHz. Vacuum packaging is completed by glass-silicon anodic bonding (250-300℃, 5kN pressure), and the vacuum degree is <10 - 3Pa, magnetic permeability ≥95%, total chip thickness is 0.4mm-0.5mm.

[0039] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0040] (1) The present invention completely eliminates traditional ferromagnetic conductive materials such as NiFe in the sensor's sensitive structure through a coreless design, and instead uses a high-density planar multi-layer spiral coil to construct a three-axis sensing unit, thereby avoiding the damage of hysteresis errors and high-temperature magnetic annealing processes to CMOS circuits, and achieving improved stability of magnetoelectric characteristics and full-process low-temperature compatibility.

[0041] (2) This invention is the first to vertically interconnect the coil structure and the MCU logic circuit within the same wafer through TSV (Through Silicon Via) technology, achieving a signal short-pass path with a through-hole with a diameter of 3-5 μm and an aspect ratio of 8:1-12:1, effectively compressing the module size to the millimeter level ([2.5×2.5,3×3]mm 2 × [0.4, 0.5] mm), and significantly outperforms traditional planar interconnects in terms of integration density and interconnect efficiency. This integration approach is a key technical approach of the present invention, significantly reducing volume and improving interconnect quality while ensuring triaxial magnetic response.

[0042] (3) To solve the coupling interference problem between the MCU digital circuit and the analog magnetic induction unit in single-chip integration, the present invention introduces a tantalum nitride (TaN) composite shielding layer doped with Fe3O4 nanoparticles between the two. The shielding layer is optimized in the two parameter spaces of thickness (100-500nm) and doping ratio (1-5wt%), and has good magnetic field transparency and high-frequency noise attenuation performance. In actual tests, the noise suppression capability in the 1-10MHz frequency band is more than 25dB, thereby improving the overall system signal-to-noise ratio to ≥30dB in the weak magnetic field (<1μT) detection scenario. This shielding method is structurally embedded in the sensitive area in layers, and functionally takes into account both signal fidelity and interference suppression, which is a unique composite shielding implementation path of the present invention.

[0043] (4) The application constructs a full-process low-temperature process system, controls the temperature of key processes at <= 400 DEG C (as shown in Table 1), wherein the CMOS front-end process temperature is in the range of 350-400 DEG C, the purpose is to avoid the thermal damage of high-temperature annealing on copper interconnection, dielectric layer and subsequent MEMS structure while ensuring the performance of transistor and the quality of medium, to realize the replacement of traditional high-temperature process (> 600 DEG C), so as to be compatible with subsequent low-temperature integrated process, improve the overall yield and packaging reliability. PECVD deposition and packaging bonding are limited in the range of 250-300 DEG C, which effectively avoids the thermal damage problem of high-temperature processing on copper interconnection structure, dielectric layer and suspended structure, realizes the process yield of > 95%. At the same time, the packaging stage adopts the non-magnetic glass-silicon anode bonding packaging method with vacuum degree < 10 - 3Pa and magnetic permeability >= 95%, which guarantees the stable work of magnetic sensitive structure and further improves the product reliability.

[0044] Table 1

[0045]

[0046] In summary, the application solves the problem that the traditional magnetic sensor integration scheme cannot consider the volume, precision, power consumption and manufacturing adaptability by the integration and synergistic innovation of non-magnetic core induction structure, TSV three-dimensional interconnection, nanometer composite shielding layer and low-temperature full-process technology, and forms a single-chip integration method with structural originality, parameter controllability and process transformation feasibility. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 The application is a miniaturized single-chip integration method for geomagnetic sensor and MCU.

[0048] Figure 2 The integrated wafer cross-sectional structure diagram, wherein 1 is a borosilicate glass cover plate, 2 is a vacuum layer, 3 is an electromagnetic shielding layer, 4 is an insulating layer, 5 is a TSV interconnection structure, 6 is a non-magnetic core planar coil, 7 is a SiO2 dielectric layer, 8 is a copper interconnection layer, 9 is a transistor area, and 10 is a silicon substrate. DETAILED DESCRIPTION

[0049] In order to better introduce the technical scheme and advantages of the application, the application will be further explained and described below in combination with specific embodiments, and the described embodiments are part of the embodiments of the application, rather than all the embodiments.

[0050] Figure 1The process flow chart for the micro-fabrication of the geomagnetic sensor and MCU monolithic integrated method of the application comprises five steps: (1) low-temperature CMOS circuit layer preparation, (2) TSV three-dimensional interconnection structure processing, (3) non-magnetic core planar coil manufacturing, (4) low-temperature electromagnetic shielding layer integration, and (5) structure release and vacuum packaging.

[0051] Figure 2 The integrated wafer cross-sectional structure diagram comprises the following parts:

[0052] 1) Borosilicate glass cover plate: located at the uppermost layer of the device, used as the upper packaging material for anodic bonding, having high magnetic permeability (≥ 95%) and excellent sealing performance, ensuring the stability and long-term air tightness of the packaging cavity.

[0053] 2) Vacuum layer: formed between the cover plate and the device functional layer, used to provide a suspended structure working environment, with a vacuum degree controlled at <10 - 3Pa, effectively improving the mechanical Q value and anti-vibration performance of the coil and reducing the influence of air damping.

[0054] 3) Electromagnetic shielding layer: deposited at the interface position between the induction structure and the CMOS circuit, the shielding layer is a TaN composite material doped with Fe3O4 nanoparticles, with a thickness range of 100-500 nm and a doping ratio of 1-5 wt%, used to suppress the electromagnetic interference of the digital circuit on the magnetic induction structure and improve the signal-to-noise ratio under weak magnetic fields.

[0055] 4) Insulating layer: acts as a buffer and interface transition between the shielding layer and other layers, which can be silicon nitride or SiO2 material.

[0056] 5) TSV interconnection structure: connects the non-magnetic core planar coil and the vertical silicon through-hole structure of the MCU analog front end below, with a through-hole diameter of 3-5 μm, an aspect ratio of 8:1-12:1, a filling material of copper or polysilicon, a side wall covered with a TiN diffusion barrier layer, realizing low-resistance and high-density interconnection, with an electrical resistance controlled at 40-50 mΩ and a parasitic capacitance ≤ 0.1 pF. Figure 2 The TSV interconnection structure is shown in an array distribution

[0057] 6) Non-magnetic core planar coil: the key induction structure of the application, using multi-layer spiral stacked wiring with a line width ≤ 2 μm, SiO2 dielectric material for interlayer isolation, 30 layers of stacking, a total thickness of about 0.4-0.5 mm, forming a three-axis magnetic field detection structure (X / Y / Z axis), coupled with the analog circuit through TSV.

[0058] 7) SiO2 dielectric layer: Serves as the dielectric layer between the stacked coils and the circuit structure below. It is deposited by PECVD with a thickness of approximately 0.5μm to ensure electrical insulation performance and low dielectric loss.

[0059] 8) Copper interconnect layer: It is a multi-layer metal wiring layer that uses a dual damascene structure to achieve high-density signal interconnection. The metal used is copper, and the dielectric layer is SiO2 deposited by PECVD. The maximum temperature does not exceed 400°C.

[0060] 9) Transistor area: Located above the silicon substrate, it is the MCU core logic unit, analog amplifier, ADC and communication circuit area built according to the 180nm CMOS process, with low noise and low power consumption characteristics.

[0061] 10) Silicon substrate: provides mechanical support for the entire chip and forms the lower boundary of the package cavity through anodic bonding with the glass cover.

[0062] Example 1: Preparation and integrated verification of a miniaturized geomagnetic sensor chip

[0063] On an 8-inch SOI silicon wafer, the following process operations are performed according to the following flow:

[0064] 1. Preparation of CMOS circuit layer

[0065] Using 180nm low-temperature CMOS technology, the maximum temperature of the front-end process is within the range of 350-400℃ to complete the integration of MCU logic unit, ADC module, and communication interface. The area of ​​the circuit chip is about 2.5×2.5mm 2 .

[0066] 2. TSV three-dimensional interconnection preparation

[0067] TSVs with a diameter of 5μm and an aspect ratio of 10:1 were fabricated by deep silicon etching and copper electroplating to achieve low-resistance interconnection between the planar coil and the MCU. Test results showed that the average TSV resistance was 46.3mΩ with a standard deviation of <3%.

[0068] 3. Integration of coreless planar coils

[0069] A three-axis spiral structure coil was prepared in a multi-layer stacking form with a single layer thickness of 2μm, a total of 30 layers, and a total height of approximately 0.45mm. TSV was used to achieve a short-path connection with the MCU analog front end. The coil inductance was measured to be 28.4μH on the X axis, 29.7μH on the Y axis, and 30.1μH on the Z axis, with an inter-axis deviation of <5%.

[0070] 4. Electromagnetic shielding layer integration

[0071] A TaN-Fe3O4 composite material with a thickness of 300 nm and a Fe3O4 doping ratio of 3% is deposited above the MCU circuit layer, and the shielding layer covers an area of 1.8*1.8 mm 2 . After shielding, the noise coupling of the digital circuit area to the magnetic sensor is reduced by 25-30 dB.

[0072] 5. Structure release and packaging

[0073] The sacrificial layer is released using HF vapor etching to form a 1 μm thick suspended structure. The chip is packaged by anodically bonding a borosilicate glass cover at 300°C, and the final module size is 2.9*2.9*0.48 mm 3 .

[0074] Example 2: Packaging reliability enhancement verification of a larger area package

[0075] 1. Preparation of the CMOS circuit layer

[0076] Using a 180 nm CMOS process, the preparation and passivation protection of the MCU core circuit are completed at a process condition of 370°C. The integrated circuit module includes a signal amplifier, an ADC, and a digital communication interface. The chip area is expanded to 3.0*3.0 mm to adapt to a larger size electromagnetic shielding structure. 2 .

[0077] 2. TSV three-dimensional interconnection structure processing

[0078] TSV through holes are prepared on the surface of the MCU circuit layer. A through hole structure with a diameter of 4 μm and an aspect ratio of 12:1 is used. The through hole is filled with copper, and the sidewall is covered with a titanium nitride (TiN) diffusion barrier layer. After chemical mechanical polishing (CMP) treatment, an average interconnection resistance of 43.8 mΩ is obtained.

[0079] 3. Integration of planar coils without magnetic cores

[0080] A single-layer process with a thickness of 2 μm, a line width of ≤2 μm, and a line spacing of 7 μm is used to stack 28 layers to form a three-axis spiral coil with a total thickness of 0.44 mm. The actual measured values of the inductance of each axis are: X-axis 27.1 μH, Y-axis 28.6 μH, and Z-axis 30.0 μH, with an axis-to-axis deviation of ±5%.

[0081] 4. Integration of electromagnetic shielding layer

[0082] A TaN composite shielding layer with a thickness of 400 nm and a Fe3O4 doping ratio of 4% is deposited between the sensing structure and the MCU circuit, and covers the MCU digital area through patterned etching. The actual measured shielding gain is about 28 dB, which performs excellently in the medium and low frequency bands.

[0083] 5. Structure release and packaging

[0084] HF vapor etching to release the sacrificial layer, forming 1 μm high overhang structure. Anodic bonding process is used for packaging, temperature 280℃, vacuum degree <5x10 -4 Pa, borosilicate glass cover plate is used. The final module thickness is 0.49mm, and the packaging reliability is verified by 1500 thermal cycle tests.

[0085] Example 3: Low power consumption optimized version verification

[0086] On an 8-inch SOI silicon wafer, the following process operations are performed according to the following flow:

[0087] 1. CMOS circuit layer preparation

[0088] The MCU core circuit and ADC module are optimized under low temperature process conditions of 350℃, especially the transistor parameters of the standby current path are adjusted to realize low power consumption characteristics. The chip area is 2.7x2.7mm 2 , and the overall power consumption is controlled to be no more than 295μW in low load mode.

[0089] 2. TSV three-dimensional interconnection structure processing

[0090] The TSV via hole design diameter is 3μm, the aspect ratio is 9:1, the filling material is copper, the sidewall forms a TiN diffusion barrier layer, and the interconnection resistance after CMP is 48.9mΩ, maintaining the interconnection integrity and conductivity.

[0091] 3. Integration of planar coil without magnetic core

[0092] The coil structure with a line width of 1.8μm and a pitch of ≥6μm is used, stacked for 30 layers, and the total thickness is about 0.43mm. The actual measured three-axis inductance values are: X-axis 26.0μH, Y-axis 27.4μH, and Z-axis 28.9μH, meeting the high sensitivity magnetic field sensing requirements.

[0093] 4. Integration of electromagnetic shielding layer

[0094] The shielding layer material is a 200nm thick TaN-based composite layer, with a Fe3O4 doping ratio of 2%, which focuses on optimizing the noise attenuation performance in the medium frequency band (2-6MHz), with a suppression ability of more than 25dB.

[0095] 5. Structure release and packaging

[0096] HF vapor etching is used to release the sacrificial layer under the coil, forming a 1μm overhang height. Anodic bonding at 250℃ is used in the packaging process, with a vacuum degree <10 - 3Pa. The final module total thickness is controlled to be 0.45mm, and the power consumption is reduced by more than 22% compared with the traditional scheme.

[0097] The structure and performance index of the above-mentioned embodiments 1-3 and the traditional integrated scheme are shown in Table 2 below, and the power consumption and sealing performance index of the above-mentioned embodiments 1-3 and the traditional integrated scheme are shown in Table 3 below.

[0098] As can be seen from Table 2, the embodiments of the present application are significantly better than the traditional integrated scheme in terms of structure size, inductance characteristics, noise shielding ability and interconnection performance. The chip area of the traditional scheme is generally greater than 5.0*5.0mm 2 , while the chip size of each embodiment of the present application is compressed to 3.0*3.0mm 2 and below, with a volume reduction of 67%-75%, which is more suitable for micro-embedded systems. At the same time, the traditional packaging thickness is generally more than 1.2mm, while the present application realizes an overall thickness of 0.45-0.49mm through structure stacking optimization and suspension release, with a thickness reduction of more than 60%. In terms of inductance performance, embodiments 1-3 maintain a deviation of less than ±5% under a three-axis structure, and the inductance density per unit volume is better than the traditional magnetic core scheme. Especially in terms of noise suppression, the traditional scheme has a noise shielding ability of less than 10dB due to the lack of effective shielding structure, while the present application introduces a Fe3O4-TaN composite shielding layer, with noise attenuation improved to 25-30dB, and the geomagnetic signal detection accuracy is significantly improved. In addition, the TSV interconnection technology realizes a low impedance of <50mΩ and a low parasitic capacitance of <0.1pF in the three examples, greatly optimizing the signal transmission path and anti-interference ability, and providing support for high-speed and high-precision operation of the system.

[0099] As can be seen from Table 3, the present application also performs well in terms of power consumption control and packaging reliability. The power consumption of a single chip of the traditional scheme is usually higher than 850μW, which is difficult to meet the needs of low-power scenarios such as wearable devices. While the embodiments of the present application optimize the low-temperature CMOS process and low-bias amplification structure to control the power consumption in the range of 295-410μW, with the lowest power consumption version (embodiment 3) reduced by more than 65% compared with the traditional scheme, greatly extending the system battery life. In terms of packaging, the traditional vacuum degree is only at the level of 10 - 2Pa, which is difficult to maintain the stability of magnetic induction for a long time, while the present application uses anode bonding to form a vacuum cavity, with the vacuum degree improved to <10 - 3Pa or even <5*10 -4 Pa, greatly improving the purity of the magnetic environment. The packaging temperature is reduced from the traditional ≥350℃ to 250-300℃, effectively avoiding high-temperature damage to the circuit structure; the packaging yield is stably improved to more than 95%, which is much better than the traditional scheme of ≤80%. In terms of manufacturing cost, the present application reduces the single chip cost to 0.68-0.72 dollars through process integration and area compression, which is 30-40% lower than the traditional scheme, and has the basis for large-scale industrial application.

[0100] Table 2 structure and electrical performance index comparison

[0101]

[0102] Table 3 Power consumption and closure performance indicators comparison

[0103]

[0104]

Claims

1. A method for miniaturized single-chip integration of a geomagnetic sensor and an MCU, characterized by: The following steps are involved: (a) forming an MCU circuit layer on a silicon substrate using a CMOS-MEMS process, wherein the MCU circuit layer includes a signal amplification module, a digital processing unit, and a communication interface; (b) fabricating a coreless planar coil of a Lorentz force geomagnetic sensor on the MCU circuit layer, and vertically interconnecting the coil with the MCU circuit layer through vertical through-holes (TSVs); (c) depositing a tantalum nitride (TaN) composite electromagnetic shielding layer between the MCU circuit layer and the planar coil; (d) The suspended support structure of the planar coil is released by etching, and the subsequent structure release and packaging process is packaged using non-magnetic vacuum packaging materials. The packaging process uses a bonding temperature of 250-300°C and a vacuum degree of <10 - 3Pa.

2. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The vertical through hole TSV in step (b) has a diameter of 3-5 μm and an aspect ratio of 8:1-12:

1.

3. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The maximum temperature of the front-end process of the CMOS-MEMS process is controlled at 350-400° C., and the metal interconnection layer is a copper dual damascene structure.

4. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The planar coil has a multi-layer stacked structure with a line width of ≤2μm, an interlayer spacing of ≥3 times the line width, a total thickness of 0.4-0.5mm, and a chip area of ​​2.5×2.5-3×3mm 2 .

5. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The diameter of the TSV through hole is 3-5 μm, the filling material is copper or polysilicon, and the sidewall of the through hole is covered with a titanium nitride TiN diffusion barrier layer.

6. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The resistance of TSV through-hole is 40-50mΩ, the parasitic capacitance is ≤0.1pF, and the signal transmission delay is <10ps.

7. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The tantalum nitride (TaN) composite electromagnetic shielding layer is a composite material of tantalum nitride (TaN) and Fe3O4 nanoparticles.

8. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 7, wherein: The thickness of the tantalum nitride TaN composite electromagnetic shielding layer is 100-500nm, the Fe3O4 doping ratio is 1-5wt%, and the noise attenuation capability is ≥25dB.

9. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to claim 1, wherein: The magnetic permeability of the non-magnetic vacuum packaging material in step (d) is ≥95%.

10. The method for miniaturized single-chip integration of a geomagnetic sensor and an MCU according to any one of claims 1 to 9, characterized in that: The geomagnetic sensor has good magnetic field transparency and high-frequency noise attenuation performance, with a noise suppression capability of more than 25dB in the 1-10MHz frequency band. In the weak magnetic field <1μT detection scenario, the overall system signal-to-noise ratio is improved to ≥30dB.

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