Differential phase self-calibration single power supply variable gain distributed balun circuit

Abstract

The invention relates to the technical field of radio frequency, and discloses a differential phase self-calibration single-power-supply variable gain distributed balun circuit which comprises a differential phase calibration module, an ultra-wideband matching gain adjustment module and a distributed balun amplifier core module connected with the differential phase calibration module and the ultra-wideband matching gain adjustment module. On the basis of a traditional differential-to-single-ended distributed balun circuit, the defect that a traditional distributed balun needs multiple sets of power voltages is overcome by only needing one set of power voltages, and meanwhile, the distributed balun circuit provided by the invention also has a digital gain calibration function, so that the balun has a higher degree of freedom in use. In addition, a differential signal self-calibration circuit is further used, and it is guaranteed that the phase error of balun differential input is minimized.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency technology, and in particular to a differential phase self-calibration single-power supply variable gain distributed balun circuit. Background Art

[0002] Distributed baluns are widely used in ultra-wideband communications and radar systems. This is particularly true within transmit circuits. Since antennas are single-ended, a differential-to-single-ended balun ensures that the majority of circuit modules within the transmit system are single-ended, ensuring sufficient system linearity and image rejection. However, traditional distributed differential-to-single-ended baluns often require multiple power supply voltages and struggle to implement digital variable gain. Furthermore, the 180° phase difference of the balun's differential ports often suffers from phase errors due to process or component mismatches, making them difficult to achieve in practice.

[0003] Figure 1 This is the schematic diagram of an existing differential-to-single-ended distributed balun circuit. The differential positive signal enters through the positive input port, the differential negative signal enters through the negative input port, and the final output signal is transmitted to the outside of the circuit through the output port. To ensure proper operation of the balun, this circuit requires three power supply voltages: VDD, VDD1, and VDD2, which is relatively complex. Furthermore, existing technology cannot ensure that the positive and negative input signals maintain a 180-degree angle after entering the balun, resulting in poor balun performance.

[0004] The shortcomings of existing technologies are clear. First, they require three sets of power supply voltages, which complicates the design. Second, if the design model has errors, the balun cannot achieve gain calibration or adjust the gain according to actual usage requirements. Performance will fluctuate due to process or temperature fluctuations. Finally, existing baluns also have difficulty achieving 180° phase calibration. Process and device variations during actual chip manufacturing will also lead to deterioration in balun performance. Summary of the Invention

[0005] The present invention provides a differential phase self-calibration single-power supply variable gain distributed balun circuit, aiming to solve at least one of the above technical problems.

[0006] To achieve the above objectives, the present invention provides a differential phase self-calibration single-power supply variable gain distributed balun circuit, comprising: a differential phase calibration module, an ultra-wideband matching gain adjustment module, and a distributed balun amplifier core module connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module; The differential phase calibration module is connected to the positive input terminal and the negative input terminal of the differential signal, and is configured to eliminate the phase error of the differential positive terminal signal inputted at the positive input terminal and the differential negative terminal signal inputted at the negative input terminal with an error, and transmit the differential positive terminal signal and the differential negative terminal signal after the phase error elimination to the first input terminal and the second input terminal of the distributed balun amplifier core module respectively; The ultra-wideband matching gain adjustment module is connected to the digital signal input terminal and is configured to convert the digital input signal into an analog DC voltage signal and transmit the analog DC voltage signal to the third input terminal of the distributed balun amplifier core module; Among them, the distributed balun amplifier core module includes a distributed amplifier architecture connected to a first input end, a second input end and a third input end. The first input end and the second input end are configured to transmit a differential positive end signal and a differential negative end signal to the distributed amplifier architecture, driving the distributed amplifier architecture to convert the differential signal into a single-ended signal. The third input end is configured to transmit an analog DC voltage signal to the distributed amplifier architecture, and is configured to adjust the DC voltage of several transistors in the distributed amplifier architecture.

[0007] Optionally, the differential phase calibration module includes: The first distributed amplifying unit is connected to the negative input terminal of the differential signal, includes an inductor Li0, an inductor Li1 and a transistor Mc1, and is configured to invert the differential negative terminal signal inputted at the negative input terminal and transmit the inverted differential negative terminal signal to the transistor Mc3; The second distributed amplification unit is connected to the positive input terminal of the differential signal, includes inductors Lm0 and Lm1 and transistor Mc2, and is configured to maintain the phase of the differential positive terminal signal input to the positive input terminal; The transistor Mc2 and the transistor Mc3 are connected to form an analog multiplier, which is configured to perform phase error self-calibration on the differential negative terminal signal and the differential positive terminal signal in the differential signal.

[0008] Optionally, the source of the transistor Mc2 is connected to the drain of the transistor Mc3, and the transistors Mc2 and Mc3 are connected to form an analog multiplier. The expressions of the gate voltage of the transistor Mc2, the gate voltage of the transistor Mc3, and the drain voltage of the transistor Mc2 are:

[0009] ; ; ; Where, is the gate voltage of transistor Mc2, is the gate voltage of transistor Mc3, is the drain voltage of transistor Mc2, is the amplification factor of transistor Mc2, is the amplification factor of the transistor Mc3, Δ is the phase error between the differential negative terminal signal and the differential positive terminal signal, ω is the angular frequency, and t is the time.

[0010] Optionally, the drain of the transistor Mc2 is connected to the VDD input terminal and is provided with a low-pass filter. The low-pass filter filters out high-frequency signals in the drain voltage of the transistor Mc2. The expression of the signal obtained after filtering is: ; Where, is the proportional coefficient, set to 1, , derive , k is the proportional coefficient.

[0011] Optionally, the differential phase calibration module further includes a voltage-controlled capacitor connected to the drain of the transistor Mc2 and the positive input terminal. , the voltage-controlled capacitor The expression is: ; Where m is the proportional coefficient, set to 1, V is the DC voltage of the substrate, and the phase error Δ between the differential negative signal and the differential positive signal and the voltage-controlled capacitance are derived. The relationship is .

[0012] Optionally, the distributed amplifier architecture includes: a first distributed amplification group, comprising a transistor M10, a transistor M20, and a transistor M30, the gates of which are connected to the second input terminal, and configured to invert the differential negative terminal signal inputted from the second input terminal; The second distributed amplification group includes transistors M11, M12 and M13, whose gates are connected to the drains of transistors M10, M20 and M30, so that transistors M10 and M11, transistors M20 and M12, and transistors M30 and M13 respectively form independent amplification units.

[0013] Optionally, the distributed balun amplifier core module also includes an input negative end signal gain adjustment circuit, which is connected to the gates of transistor M10, transistor M20 and transistor M30. The input negative end signal gain adjustment circuit includes resistor R4 and resistor R5 connected between the VDD input terminal and the ground, and the gates of transistor M10, transistor M20 and transistor M30 are connected between resistor R4 and resistor R5.

[0014] Optionally, the ratio of the resistance R4 and the resistance R5 is configured such that the gain of the amplifier composed of the transistor M10, the transistor M20 and the transistor M30 is 1.

[0015] Optionally, the gates of the transistor M11, the transistor M12 and the transistor M13 are connected to the first input end and the third input end, and are configured to control the gain of the distributed amplifier architecture according to the analog DC voltage signal input by the third input end.

[0016] Optionally, the ultra-wideband matching gain adjustment module comprises: a differential input single output operational amplifier EA, a digital-to-analog converter DAC1 connected to the positive input end of the operational amplifier EA, a power transistor MP connected to the output end of the operational amplifier EA, and a voltage dividing resistor unit connected between the source of the power transistor MP and the negative input end of the operational amplifier EA. Wherein, the positive input end of the operational amplifier EA is provided with a filter capacitor Cf, the drain of the power transistor MP is connected to the VDD input end through a high-frequency resonance capacitor Lr, and the voltage dividing resistor unit comprises a resistor R1 connected between the source of the power transistor MP and the negative input end of the operational amplifier EA, and resistors R2 and R3 connected between the source of the power transistor MP and the ground. Wherein, the source of the power transistor MP and the voltage dividing resistor unit are connected to the third input end of the distributed balun amplifier core module as the output of the ultra-wideband matching gain adjustment module.

[0017] The beneficial effects of the present application are: a differential phase self-calibration single power variable gain distributed balun circuit is proposed, which only needs one group of power supply voltage to overcome the shortcoming of multiple groups of power supply voltage required by the traditional distributed balun based on the traditional differential to single-ended distributed balun circuit, and the distributed balun circuit proposed by the present application also has a digital gain calibration function, so that the balun has higher freedom when used. In addition, the differential signal self-calibration circuit is also used to minimize the phase error of the differential input of the balun. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a schematic diagram of the differential to single-ended distributed balun circuit in the prior art; Figure 2 It is a schematic diagram of the differential phase self-calibration single power variable gain distributed balun circuit of the present application; Figure 3 It is an equivalent circuit schematic diagram of the power transistor in different conditions in the present application; Figure 4 It is an example diagram of the ultra-wideband matching gain adjustment module in the differential phase self-calibration single power variable gain distributed balun circuit of the present application; Figure 5 The simulation results of the balun gains of C1, C2 and C3 in different control words in the present invention are as follows; Figure 6 The simulation results of the present invention with and without self-calibration when inputting positive and negative port differential signals are shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 2 As shown, an embodiment of the present invention provides a differential phase self-calibration single-power supply variable gain distributed balun circuit, including: a differential phase calibration module, an ultra-wideband matching gain adjustment module, and a distributed balun amplifier core module connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module.

[0021] (1) For the differential phase calibration module: The differential positive signal enters the positive input port Cp2 from the left plate, while the differential negative signal enters the negative input port Cp1 from the left plate. After passing through the distributed amplifier formed by Li0, Li1, and transistor Mc1, the negative input signal undergoes a 180° phase inversion and enters the gate of calibration transistor Mc3. After passing through the distributed amplifier formed by Lm0, Lm1, and Mc2, the phase of the positive input signal at Mc2's gate remains unchanged. Ideally, the gate signals at Mc3 and Mc2 are in phase.

[0022] At this time, as mentioned above, due to device or process deviations, there will be errors in the phases of Mc2 and Mc3. If the phase error is Δ, and considering that the angular frequencies of the two signals are the same and set to ω, the gate voltages of Mc2 and Mc3 can be written as: ;

[0023] ; At this point, Mc2 and Mc3 form an analog multiplier, so the voltage at the drain of Mc2 can be written as: ; Where ω is the angular frequency and t is the time; At this time, Cp4 is a low-pass filter, and the signal with a frequency of 2ω will be filtered out. ; if is k, and the phase difference is relatively small, then the voltage at this time is: ; Therefore, the DC voltage with phase error signal can control the capacitor To adjust Voltage controlled variable capacitor The relationship with the DC voltage of its substrate is as follows: ; m and k are both proportional coefficients. We can simply assume that m is 1, and then we can get the relationship between the phase error of Mc2 and Mc3 and the capacitance of the voltage-controlled capacitor: ; The phase of the positive input is affected by The capacitance is controlled by changing The value of can change the phase of the input positive terminal signal, so if there is Δ, it can be adjusted by Δ By changing the value of Δ to 0, the phase error self-calibration of the differential signal is realized. After the differential phase self-calibration, the positive and negative signals maintain an accurate 180° phase difference.

[0024] (2) For the distributed balun amplifier core module: Both the positive and negative inputs utilize a distributed amplifier architecture, ensuring a sufficiently high operating bandwidth. The negative input signal, after being inverted by M10, M20, and M30, has the same phase as the positive input signal. By adjusting the ratio of R4 and R5, the amplifier formed by M10, M20, and M30 achieves a gain of 1. This ensures that the balun's positive and negative input signals have the same gain and a phase difference of 180°, achieving differential-to-single-ended conversion.

[0025] The gain of the negative input signal can be adjusted by the ratio of R4 and R5. In addition, by selecting the values ​​of R4 and R5, the load viewed to the right by Li4 is the characteristic impedance of the system. This ensures that the port impedance of the distributed amplifier for the negative input signal is the characteristic impedance of the system, and does not require a new set of power supply voltages.

[0026] (3) For the ultra-wideband matching gain adjustment module: The DC voltage of the transistor at the positive input is ensured by the negative feedback loop composed of the digital-to-analog converter DAC1, the differential input single-ended output operational amplifier EA, the filter capacitor Cf, the power transistor MP, the voltage divider resistors R1, R2, R3 and the high-frequency resonant capacitor Lr shown in the present invention. The digital input signal is converted into the required analog DC voltage signal by DAC1 to control the gate voltage of the positive input transistor and the drain voltage of the negative transistor. MP is a power transistor with a source follower structure, and Lr is the resonant inductor at high frequencies. Figure 3Figure (a) shows the small-signal equivalent circuit of the impedance seen by the source of power transistor MP. To ensure that the impedance seen by the balun port is the characteristic impedance of the distributed balun system, this impedance must be 50Ω over a very wide bandwidth. In this case, by setting the resistance values ​​of R1, R2, and R3 significantly higher than 50Ω, the impedance seen by the balun port is completely determined by the impedance seen by the source of MP.

[0027] At low frequencies, the small signal equivalent circuit seen from the source of MP is as follows Figure 3 As shown in (b), Cgs, Cgd, and Cf are open circuits and are therefore not drawn. Point X is the port node of the MP source, so Vx / Ix is the port impedance seen by the distributed balun. In addition, at low frequencies, the MP gate is equivalent to a DC voltage, so AC signals can use this port as a signal ground. Figure 3 As shown in (b), the impedance at point X can be written as 1 / gmmp, where gmmp is the transconductance of the power transistor MP. By selecting the size of the transistor MP, 1 / gmmp can achieve 50Ω, which ensures the port impedance requirement at low frequencies. At high frequencies, the small signal equivalent circuit viewed from the source of MP is as follows: Figure 3 As shown in (c) above. At this point, Cgs, Cgd, and Cf are effectively short-circuited. The short-circuit of Cgs causes the current generated by gmmp to be zero, thus effectively an open circuit. Furthermore, due to the presence of Lr, the path from Cgd in series with Lr to the small-signal ground is also an open circuit. Therefore, the impedance seen from the source of MP is Ro2. This is because the short-circuit of Cf effectively connects the right side of Ro2 to ground. In summary, by setting 1 / gmmp to 50Ω and Ro2 to 50Ω, the impedance seen from the balun port can be the system's characteristic impedance of 50Ω.

[0028] In addition, by adjusting the digital input of the DAC, under the normal voltage clamping of the EA, the output DC potential of the MP transistor source can be adjusted, thereby adjusting the gate voltage of M11, M12 and M13 to change their gain to achieve the effect of digitally controlled variable gain.

[0029] It should be noted that the port impedance of the positive or negative input transmission line in this embodiment must be used as follows: Figure 2As shown, the negative feedback loop, including MP, Lr, Ro2, R1, R2, R3, Cf, EA, and DAC, is an ultra-wideband matching gain adjustment module, which maintains the impedance seen through the balun port at 50Ω. MP is a source follower structure, and its dimensions ensure that its gm value is within 0.02S, or 1 / gm, of 50Ω. Ro2 is also 50Ω. The balun uses a differential phase self-calibration circuit for the input signal to minimize the differential phase error between the positive and negative signals at the balun. The characteristic impedance of the artificial transmission line formed by the gate capacitances of Li0, Li1, and Mc1 is 50Ω, and the characteristic impedance of the artificial transmission line formed by the gate capacitances of Lm0, Lm1, and Mc2 is also 50Ω. This does not affect the characteristics of the distributed balun itself.

[0030] In order to explain the present invention more clearly, a circuit example of a differential phase self-calibration single-supply variable gain distributed balun circuit is provided below.

[0031] like Figure 4 As shown, C1, C2, and C3 are digital input ports that control the on / off switching of switching transistors MSW1-MSW3, thereby adjusting the DC voltage input to the gate of transistor M2. M1-M6 form the EA circuit. Through the negative feedback of the EA circuit, the DC output voltage of the MP can be controlled by the digital inputs of C1, C2, and C3. All modules share a common power supply, VDD, and the balun gain can be adjusted using the digital inputs of C1, C2, and C3.

[0032] Figure 5 The following are simulation results of the balun gain for C1, C2, and C3 under different control words, using only a single supply voltage. It can be seen that the balun gain can achieve different values ​​under different numerical control states, while a traditional distributed balun must use multiple supply voltages and can only achieve a fixed gain.

[0033] Figure 6 The simulation results for the positive and negative differential input signals with and without self-calibration are shown below. The differential phase error is optimized with self-calibration.

[0034] The following is a set of possible size parameters for a circuit example of a differential phase self-calibration single-supply variable gain distributed balun circuit: MS4 is 40nm / 6um, MS5 is 40nm / 12um, and MS6 is 40nm / 24um; Rs1 and Rs2 are 500Ω; MSW1~MSW3 are 40nm / 48um; M1~M6 are 40nm / 12um; MP is 40nm / 52um; Cf is 1pF; R1 is 1KΩ, R2 is 1KΩ, and R3 is 1.5KΩ; M10, M20, M30, M11, M12, M13, are 40nm / 48um; Li2, Li3: 50pH, Li4: 25pH, Li1: 35pH, Li0: 15pH; Ld2, Ld3: 60pH, Ld1, Ld4: 30pH; Lm2, Lm3: 70pH, Lm4: 35pH, Lm1: 50pH, Lm0: 20pH; Ro1, Ro2: 50Ω; Cp1: 50pF, Lr5nH, Cp2: 50pF; R4: 150Ω, R5: 75Ω; Mc1: 40nm / 12um; Mc2 and Mc3: 40nm / 6um; Cp4: 50pF, Cp3: 25pF; :The initial value is 85fF; Rb1: 75Ω; Rb3: 50Ω.

[0035] Thus, this embodiment addresses the issues of existing differential-to-single-ended distributed balun circuits, which require multiple supply voltages and are difficult to calibrate, by proposing a circuit that only requires a single supply voltage and can simultaneously perform digitally controlled gain adjustment. This simplifies the use of the balun circuit while ensuring that the balun can operate normally under different processes and temperatures. Furthermore, the present invention utilizes differential phase self-calibration technology to adaptively maintain the positive and negative input signals at 180°, thereby improving the balun's performance.

[0036] It should be understood that, in the description of this specification, reference to terms such as "one embodiment," "another embodiment," "other embodiments," or "first to Nth embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any appropriate manner in any one or more embodiments or examples.

[0037] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a", "comprising", or "comprises" does not, without further restriction, exclude the existence of additional elements of a like kind in the process, method, article, or apparatus that comprises the element.

[0038] The above merely describes the preferred embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, made by using the content of the present application specification and drawings, are also included in the patent protection scope of the present application.

Claims

1. A differential phase self-calibration single-supply variable gain distributed balun circuit, characterized in that: include: A differential phase calibration module, an ultra-wideband matching gain adjustment module, and a distributed balun amplifier core module connecting the differential phase calibration module and the ultra-wideband matching gain adjustment module; The differential phase calibration module is connected to the positive input terminal and the negative input terminal of the differential signal, and is configured to eliminate the phase error of the differential positive terminal signal inputted at the positive input terminal and the differential negative terminal signal inputted at the negative input terminal with an error, and transmit the differential positive terminal signal and the differential negative terminal signal after the phase error elimination to the first input terminal and the second input terminal of the distributed balun amplifier core module respectively; The ultra-wideband matching gain adjustment module is connected to the digital signal input terminal and is configured to convert the digital input signal into an analog DC voltage signal and transmit the analog DC voltage signal to the third input terminal of the distributed balun amplifier core module; Among them, the distributed balun amplifier core module includes a distributed amplifier architecture connected to a first input end, a second input end and a third input end. The first input end and the second input end are configured to transmit a differential positive end signal and a differential negative end signal to the distributed amplifier architecture, driving the distributed amplifier architecture to convert the differential signal into a single-ended signal. The third input end is configured to transmit an analog DC voltage signal to the distributed amplifier architecture, and is configured to adjust the DC voltage of several transistors in the distributed amplifier architecture.

2. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 1, characterized in that: The differential phase calibration module includes: The first distributed amplifying unit is connected to the negative input terminal of the differential signal, includes an inductor Li0, an inductor Li1 and a transistor Mc1, and is configured to invert the differential negative terminal signal inputted at the negative input terminal and transmit the inverted differential negative terminal signal to the transistor Mc3; The second distributed amplification unit is connected to the positive input terminal of the differential signal, includes inductors Lm0 and Lm1 and transistor Mc2, and is configured to maintain the phase of the differential positive terminal signal input to the positive input terminal; The transistor Mc2 and the transistor Mc3 are connected to form an analog multiplier, which is configured to perform phase error self-calibration on the differential negative terminal signal and the differential positive terminal signal in the differential signal.

3. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 2, characterized in that: The source of the transistor Mc2 is connected to the drain of the transistor Mc3. The transistors Mc2 and Mc3 are connected to form an analog multiplier. The gate voltage of the transistor Mc2, the gate voltage of the transistor Mc3 and the drain voltage of the transistor Mc2 are expressed as follows: ; ; Where, is the gate voltage of transistor Mc2, is the gate voltage of transistor Mc3, is the drain voltage of transistor Mc2, is the amplification factor of transistor Mc2, is the amplification factor of the transistor Mc3, Δ is the phase error between the differential negative terminal signal and the differential positive terminal signal, ω is the angular frequency, and t is the time.

4. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 3, characterized in that: The drain of the transistor Mc2 is connected to the VDD input terminal and is provided with a low-pass filter. The low-pass filter filters out the high-frequency signal in the drain voltage of the transistor Mc2. The expression of the signal obtained after filtering is: Where, is the proportional coefficient, set to 1, , derive , k is the proportional coefficient.

5. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 4, characterized in that: The differential phase calibration module further includes a voltage-controlled capacitor connected between the drain of the transistor Mc2 and the positive input terminal. , the voltage controlled capacitor The expression is: ； Where m is the proportional coefficient, set to 1, V is the DC voltage of the substrate, and the phase error Δ between the differential negative signal and the differential positive signal and the voltage-controlled capacitance are derived. The relationship is .

6. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 1, wherein: The distributed amplifier architecture comprises: a first distributed amplification group, comprising a transistor M10, a transistor M20, and a transistor M30, the gates of which are connected to the second input terminal, and configured to invert the differential negative terminal signal inputted from the second input terminal; The second distributed amplification group includes transistors M11, M12 and M13, whose gates are connected to the drains of transistors M10, M20 and M30, so that transistors M10 and M11, transistors M20 and M12, and transistors M30 and M13 respectively form independent amplification units.

7. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 6, characterized in that: The distributed balun amplifier core module also includes an input negative end signal gain adjustment circuit, which is connected to the gates of transistors M10, M20 and M30. The input negative end signal gain adjustment circuit includes resistors R4 and R5 connected between the VDD input terminal and the ground, and the gates of transistors M10, M20 and M30 are connected between resistors R4 and R5.

8. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 7, characterized in that: The ratio of the resistor R4 to the resistor R5 is configured such that the gain of the amplifier formed by the transistors M10 , M20 , and M30 is 1.

9. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 6, characterized in that: The gates of the transistors M11 , M12 and M13 are connected to the first input terminal and the third input terminal, and are configured to control the gain of the distributed amplifier architecture according to the analog DC voltage signal inputted from the third input terminal.

10. The differential phase self-calibration single-supply variable gain distributed balun circuit according to claim 1, characterized in that: The ultra-wideband matching gain adjustment module includes: an operational amplifier EA with differential input and single-ended output, a digital-to-analog converter DAC1 connected to the positive input terminal of the operational amplifier EA, a power transistor MP connected to the output terminal of the operational amplifier EA, and a voltage divider resistor unit connected to the source of the power transistor MP and the negative input terminal of the operational amplifier EA; The positive input terminal of the operational amplifier EA is provided with a filter capacitor Cf, the drain of the power transistor MP is connected to the VDD input terminal through a high-frequency resonant capacitor Lr, and the voltage divider resistor unit includes a resistor R1 connected between the source of the power transistor MP and the negative input terminal of the operational amplifier EA, and resistors R2 and R3 connected between the source of the power transistor MP and ground; The source of the power transistor MP and the voltage-dividing resistor unit are connected to the third input terminal of the distributed balun amplifier core module as the output of the ultra-wideband matching gain adjustment module.

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